Until now, STM32 MCUs classic CAN support is coded in can.c file.
However CAN FD in STM32G4 family is designed in a very different way:
* CAN FD channels are independant
* CAN FD channel configuration is done in a dedicated RAM block called
message RAM, with one message RAM per channel
* Each message RAM is divided this way:
- 11-bit filter (28 elements / 28 words)
- 29-bit filter (8 elements / 16 words)
- Rx FIFO 0 (3 elements / 54 words)
- Rx FIFO 1 (3 elements / 54 words)
- Tx event FIFO (3 elements / 6 words)
- Tx buffers (3 elements / 54 words)
Due to these design differences with other STM32 MCUs, the choice is
made to split the driver in two files:
* classiccan.c for STM32 MCUs that support classical CAN. This file
has just been renamed (previously can.c) to avoid build conflicts
but does not introduce changes
* fdcan.c for STM32 MCUs that support CAN FD
Message RAM definitions is not provided in CMSIS headers of the STM32G4
family, they are defined in fdcandev_stm32.h. Those definitions could be
extracted to a new file for each STM32 families as some differences
exist with other STM32 families that support CAN FD (for instance
STM32H7). This could be done in a futher commit, according to new
families requirements.
CAN hardware parameters stay similar and are kept in can_params.h.
There are 36 filters per channel:
* 28 first filters are standard ID (11 bit) filters
* 8 last filters are extended ID (29 bit) filters
On each Tx frame sent, the STM32G4 can store Tx events in a dedicated
FIFO. This feature is not yet implemented and Tx event FIFO is disabled
by default.
Automatic retransmission on arbitration loss is enabled by default by
the STM32G4.
About Rx, if no filter is configured, all frames are accepted by
default.
Signed-off-by: Gilles DOFFE <gilles.doffe@rtone.fr>
This doesn't change the firmware, since for all STM32 MCUs with an
SPI driver the register setting in the mode did match the SPI mode
number by chance. But for some STM32 MCUs with no SPI driver yet
the register layout is indeed different. This will help to provide an
SPI driver for them as well.
Use the largest instead of the smallest number of available EPs for this definition. This became necessary to be able to use all EPs of a USB OTG HS peripheral if enabled.
The peripheral register addresses are fixed, properly aligned addresses. Storing
them as uintptr_t makes live easier when casting them to helper structs, as no
intermediate cast to uintptr_t is needed to silence -Wcast-align.
As stm32mp1 family accesses gpio pins with a different
offset than other stm32, create a specific macro.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
* Setup i2c speed to I2C_SPEED_LOW by default
* enable i2c_write_regs() function.
* i2c frequency needs to be specified into board periph_conf.h
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
This adds a placeholder define for when the DMA peripheral available on
the MCU doesn't support channel/trigger filtering. This is the case on
the stm32f1 and stm32f3 family.
The stm32_eth driver was build on top of the internal API periph_eth, which
was unused anywhere. (Additionally, with two obscure exceptions, no functions
where declared in headers, making them pretty hard to use anyway.)
The separation of the driver into two layers incurs overhead, but does not
result in cleaner structure or reuse of code. Thus, this artificial separation
was dropped.
If any incoming frame is bigger than a single DMA buffer, the Ethernet DMA will
split the content and use multiple DMA buffers instead. But only the DMA
descriptor of the last Ethernet frame segment will contain the frame length.
Previously, the frame length calculation, reassembly of the frame, and the
freeing of DMA descriptors was completely broken and only worked in case the
received frame was small enough to fit into one DMA buffer. This is now fixed,
so that smaller DMA buffers can safely be used now.
Additionally the interface was simplified: Previously two receive flavors were
implemented, with only one ever being used. None of those function was
public due to missing declarations in headers. The unused interface was
dropped and the remaining was streamlined to better fit the use case.
- Add missing `volatile` to DMA descriptor, as memory is also accessed by the
DMA without knowledge of the compiler
- Dropped `__attribute__((packed))` from DMA descriptor
- The DMA descriptor fields need to be aligned on word boundries to
properly function
- The compiler can now more efficiently access the fields (safes ~300 B ROM)
- Moved the DMA descriptor struct and the flags to `periph_cpu.h`
- This allows Doxygen documentation being build for it
- Those types and fields are needed for a future PTP implementation
- Renamed DMA descriptor flags
- They now reflect to which field in the DMA descriptor they refer to, so
that confusion is avoided
- Added documentation to the DMA descriptor and the corresponding flags
The available GPIO ports may also differ within a family. Therefore, the vendor definitions GPIO* are used instad of CPU_FAM_STM definitions to determine which ports are available for a certain MCU.
The STM32 line of microcontrollers comes with a bootloader in the ROM.
It provides the option to flash the device firmware in DFU mode (USB)
or via UART or SPI.
To enter the bootloader we have to jump to a specific address in memory,
but before reset the CPU to make sure the system is in a known state.
This enables us to use the usb_board_reset module on all STM32 platforms.
