# SPDX-FileCopyrightText: 2020 HAW Hamburg
# SPDX-License-Identifier: LGPL-2.1-only

config CPU
    default "esp32" if HAS_CPU_ESP32

config CPU_CORE_XTENSA_LX6
    bool
    select CPU_ARCH_XTENSA
    help
        CPU core of the ESP32x SoC is a Xtensa LX6.

config CPU_CORE_XTENSA_LX7
    bool
    select CPU_ARCH_XTENSA
    help
        CPU core of the ESP32x SoC is a Xtensa LX7.

config CPU_CORE_RV32IMC
    bool
    select CPU_ARCH_RISCV
    help
        CPU core of the ESP32x SoC is a RISC-V core.

config CPU_CORE_RV32IMAC
    bool
    select CPU_ARCH_RISCV
    help
        CPU core of the ESP32x SoC is a RISC-V core.

config CPU_CORE
    default "xtensa-lx6" if CPU_CORE_XTENSA_LX6
    default "xtensa-lx7" if CPU_CORE_XTENSA_LX7
    default "rv32imc" if CPU_CORE_RV32IMC
    default "rv32imac" if CPU_CORE_RV32IMAC

rsource "Kconfig.esp32x"
rsource "Kconfig.esp32"
rsource "Kconfig.esp32c3"
rsource "Kconfig.esp32c6"
rsource "Kconfig.esp32h2"
rsource "Kconfig.esp32s3"
rsource "Kconfig.esp32s2"

source "$(RIOTCPU)/esp_common/Kconfig"