mirror of
https://github.com/RIOT-OS/RIOT.git
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8cfc42b562
This commit allows to share GPIO, Timers and UARTs driver across SAM3/SAM4s MCUs as they relies on the same IPs Signed-off-by: dylad <dylan.laduranty@mesotic.com>
135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/*
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* Copyright (C) 2025 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam_common
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* @brief Common CPU specific definitions for all SAM3/SAM4x based CPUs
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* @{
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*
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* @file
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* @brief Common CPU specific definitions for all SAM3/SAM4x based CPUs
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*/
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#ifndef PERIPH_CPU_COMMON_H
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#define PERIPH_CPU_COMMON_H
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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#define GPIO_UNDEF (0xffffffff)
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#define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
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#endif /* DOXYGEN */
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/**
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* @brief We use one channel for each defined timer
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*
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* While the peripheral provides three channels, the current interrupt
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* flag handling leads to a race condition where calling timer_clear() on one
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* channel can disable a pending flag for other channels.
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* Until resolved, limit the peripheral to only one channel.
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*/
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#define TIMER_CHANNEL_NUMOF (1)
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/**
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* @brief Generate GPIO mode bitfields
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*
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* We use 3 bit to determine the pin functions:
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* - bit 0: in/out
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* - bit 1: PU enable
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* - bit 2: OD enable
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*/
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#define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
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#ifndef DOXYGEN
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = GPIO_MODE(0, 0, 0), /**< IN */
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GPIO_IN_PD = 0xf, /**< not supported by HW */
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GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< IN with pull-up */
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GPIO_OUT = GPIO_MODE(1, 0, 0), /**< OUT (push-pull) */
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GPIO_OD = GPIO_MODE(1, 0, 1), /**< OD */
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GPIO_OD_PU = GPIO_MODE(1, 1, 1), /**< OD with pull-up */
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} gpio_mode_t;
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_RISING = 1, /**< emit interrupt on rising flank */
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GPIO_FALLING = 2, /**< emit interrupt on falling flank */
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GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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} gpio_flank_t;
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#endif /* ndef DOXYGEN */
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/**
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* @brief GPIO mux configuration
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*/
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typedef enum {
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GPIO_MUX_A = 0, /**< alternate function A */
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GPIO_MUX_B = 1, /**< alternate function B */
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#ifdef CPU_FAM_SAM4S
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GPIO_MUX_C = 2, /**< alternate function C */
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GPIO_MUX_D = 3, /**< alternate function D */
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#endif
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} gpio_mux_t;
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/**
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* @brief Available ports on the SAM3/SAM4S based MCUs
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*/
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enum {
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PA = 0, /**< port A */
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PB = 1, /**< port B */
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PC = 2, /**< port C */
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#ifdef CPU_FAM_SAM3
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PD = 3, /**< port D */
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#endif
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};
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/**
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* @brief Configure the given GPIO pin to be used with the given MUX setting
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*
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* @param[in] pin GPIO pin to configure
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* @param[in] mux MUX setting to use
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*/
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void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
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/**
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* @brief Timer configuration data
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*/
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typedef struct {
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Tc *dev; /**< timer device */
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uint8_t id_ch0; /**< ID of the timer's first channel */
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} timer_conf_t;
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/**
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* @brief UART configuration data
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*/
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typedef struct {
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Uart *dev; /**< U(S)ART device used */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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gpio_mux_t mux; /**< MUX used for pins */
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uint8_t pmc_id; /**< bit in the PMC register of the device*/
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uint8_t irqn; /**< interrupt number of the device */
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} uart_conf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_COMMON_H */
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/** @} */
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