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10f65f1631
A backward incompatible change in the RISC-V resulting in instructions previously included by rv32imac to only be available with rv32imac_zicsr. All RISC-V CPUs supported by RIOT are hence either considered as rv32imac (from the old ISA spec point of view) or as rv32imac_zicsr (from the new ISA spec point of view). This adds a simple test if GCC understands rv32imac_zicsr and uses it then as march, but uses rv32imac as march if not.