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171 lines
6.0 KiB
C
171 lines
6.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Gunar Schorcht
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup cpu_esp32
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* @{
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*
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* @file
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* @brief SDK configuration used by the ESP-IDF for ESP32-C3 SoC variant (family)
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*
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* The SDK configuration can be partially overridden by application-specific
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* board configuration.
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef DOXYGEN
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name ESP32-C3 specific clock configuration
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* @{
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*/
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/* Mapping of Kconfig defines to the respective enumeration values */
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#if CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_2
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
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#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_5
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
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#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_10
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
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#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_20
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
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#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_40
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
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#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_80
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
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#elif CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ_160
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
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#endif
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/**
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* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160]
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*/
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#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
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#endif
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/** @} */
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/**
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* ESP32-C3 specific RTC clock configuration
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*/
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#define CONFIG_RTC_CLK_CAL_CYCLES 1024
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/**
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* ESP32-C3 specific EFUSE configuration
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*/
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#define CONFIG_EFUSE_MAX_BLK_LEN 256
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#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
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#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199
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/**
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* ESP32-C3 specific MAC configuration
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*/
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
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#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES 4
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/**
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* ESP32-C3 specific system configuration (DO NOT CHANGE)
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*/
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#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
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#define CONFIG_ESP32C3_DEBUG_OCDAWARE 1
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#define CONFIG_ESP32C3_REV_MIN 3
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#define CONFIG_ESP32C3_BROWNOUT_DET 1
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#define CONFIG_ESP32C3_BROWNOUT_DET_LVL 7
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/**
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* ESP32-C3 specific sleep configuration (DO NOT CHANGE)
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*/
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#define CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND 1
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#define CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB 1
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#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
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#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 0 /* we realize it */
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#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
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#define CONFIG_ESP_SLEEP_POWER_DOWN_FLASH 1
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#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
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#define CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP 1
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/**
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* ESP32-C3 specific USB configuration
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*/
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#define CONFIG_ESP_PHY_ENABLE_USB 1
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/**
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* ESP32-C3 BLE driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_BLE
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# define CONFIG_BT_ALARM_MAX_NUM 50
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# define CONFIG_BT_BLE_CCA_MODE 0
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# define CONFIG_BT_BLE_CCA_MODE_NONE 1
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# define CONFIG_BT_CTRL_ADV_DUP_FILT_MAX 30
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# define CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
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# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
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# define CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
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# define CONFIG_BT_CTRL_BLE_MAX_ACT 10
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# define CONFIG_BT_CTRL_BLE_MAX_ACT_EFF 10
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# define CONFIG_BT_CTRL_BLE_SCAN_DUPL 1
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# define CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB 0
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# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_EFF 0
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# define CONFIG_BT_CTRL_CE_LENGTH_TYPE_ORIG 1
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# define CONFIG_BT_CTRL_CHAN_ASS_EN 1
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# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
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# define CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF 0
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# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF 11
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# define CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_P9 1
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# define CONFIG_BT_CTRL_DUPL_SCAN_CACHE_REFRESH_PERIOD 0
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# define CONFIG_BT_CTRL_HCI_MODE_VHCI 1
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# define CONFIG_BT_CTRL_HCI_TL 1
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# define CONFIG_BT_CTRL_HCI_TL_EFF 1
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# define CONFIG_BT_CTRL_HW_CCA_EFF 0
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# define CONFIG_BT_CTRL_HW_CCA_VAL 20
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# define CONFIG_BT_CTRL_LE_PING_EN 1
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# define CONFIG_BT_CTRL_MODE_EFF 1
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# define CONFIG_BT_CTRL_PINNED_TO_CORE 0
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# define CONFIG_BT_CTRL_PINNED_TO_CORE_0 1
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# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_0 1
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# define CONFIG_BT_CTRL_RX_ANTENNA_INDEX_EFF 0
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# define CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE 100
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# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE 0
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# define CONFIG_BT_CTRL_SCAN_DUPL_TYPE_DEVICE 1
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# define CONFIG_BT_CTRL_SLEEP_CLOCK_EFF 0
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# define CONFIG_BT_CTRL_SLEEP_MODE_EFF 0
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# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_0 1
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# define CONFIG_BT_CTRL_TX_ANTENNA_INDEX_EFF 0
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# define CONFIG_BT_NIMBLE_COEX_PHY_CODED_TX_RX_TLIM_DIS 1
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#endif
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/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly.
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* To use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
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* has to be set (default). */
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#ifndef CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
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# define CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 1
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#endif
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/* According to the ESP32-C3 Errata Sheet ADC2 does not work correctly.
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* To use ADC2 and GPIO5 as ADC channel, CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
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* has to be set (default). */
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#ifndef CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3
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#define CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 1
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* DOXYGEN */
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/** @} */
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