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Code Releases Activity
RIOT/cpu/fe310/periph
History
Bas Stottelaar 22243aec7a cpu/*: realign ENABLE_DEBUG
2020-10-23 00:46:26 +02:00
..
cpucycle.c
cpu/fe310: add RISC-V cpu FE310
2018-05-29 15:21:45 -07:00
cpuid.c
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
2018-05-29 16:27:53 -07:00
gpio.c
Merge pull request #14887 from bergzand/pr/fe310/plic_periph
2020-08-31 21:25:03 +02:00
i2c.c
cpu/*: realign ENABLE_DEBUG
2020-10-23 00:46:26 +02:00
Makefile
cpu/fe310: add RISC-V cpu FE310
2018-05-29 15:21:45 -07:00
plic.c
cpu/*: add missing include of assert.h
2020-10-22 11:13:08 +02:00
pm.c
fe310: fix power management configuration
2020-01-30 10:43:01 +01:00
rtc.c
cpu/*: realign ENABLE_DEBUG
2020-10-23 00:46:26 +02:00
rtt.c
cpu/*: realign ENABLE_DEBUG
2020-10-23 00:46:26 +02:00
spi.c
cpu/*: realign ENABLE_DEBUG
2020-10-23 00:46:26 +02:00
timer.c
cpu/fe310: periph/timer: reset counter in timer_init()
2019-02-21 11:34:59 +01:00
uart.c
fe310: Adapt peripherals to use the plic driver
2020-08-31 16:26:43 +02:00
wdt.c
cpu/*: realign ENABLE_DEBUG
2020-10-23 00:46:26 +02:00