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62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2020 Koen Zandberg <koen@bergzand.net>
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* SPDX-FileCopyrightText: 2023 Gunar Schorcht <gunar@schorcht.net>
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup boards_common_gd32v
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* @{
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*
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* @file
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* @brief Common peripheral configuration for GD32VF103 boards
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#include "macros/units.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(MODULE_USBDEV_SYNOPSYS_DWC2) || defined(MODULE_TINYUSB_DEVICE)
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/* If the USB OTG peripheral is used, the USB clock of 48 MHz is derived by
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* dividing the PLL clock by 1, 1.5, 2, or 2.5. That is the maximum core clock
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* frequency can be 96 MHz. */
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#define CLOCK_CORECLOCK MHZ(96) /**< CPU clock frequency in Hz */
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#else
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#define CLOCK_CORECLOCK MHZ(108) /**< CPU clock frequency in Hz */
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#endif
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#define CLOCK_AHB CLOCK_CORECLOCK /**< Equal to the CPU clock */
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#define CLOCK_APB1 CLOCK_AHB/2 /**< Half AHB clock */
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#define CLOCK_APB2 CLOCK_AHB /**< Equal to the AHB clock */
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/**
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* @name RTT/RTC configuration
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* @{
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*/
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#if CONFIG_BOARD_HAS_LXTAL
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#define RTT_CLOCK_FREQUENCY (32768U) /**< Low frequency XTAL is used as clock source */
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#else
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#define RTT_CLOCK_FREQUENCY (40000U) /**< IRC40K is used as clock source */
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#endif
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#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* maximum RTT frequency in Hz */
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#ifndef RTT_FREQUENCY
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#define RTT_FREQUENCY (RTT_MAX_FREQUENCY) /* RTT frequency in Hz */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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