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https://github.com/RIOT-OS/RIOT.git
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103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Tom Hert <git@annsann.eu>
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* SPDX-FileCopyrightText: 2025 HAW Hamburg
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup cpu_rp2350
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* @{
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*
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* @file
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* @brief Peripheral CPU definitions for the RP2350
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*
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* @author Tom Hert <git@annsann.eu>
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "RP2350.h"
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#include "clock_conf.h"
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#include "cpu.h"
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#include "gpio_conf.h"
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#include "helpers.h"
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#include "uart_conf.h"
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/** Overwrite the default GPIO type to use uint32_t */
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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#include "periph/gpio.h"
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/** GPIO Pin ID for oscillator debugging */
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#define OSC_DEBUG_PIN_ID 15u
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/** Reset bit for the system PLL */
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#define RESET_PLL_SYS (1u << 14u)
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/** Reset bit for the pads bank 0 */
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#define RESET_PADS_BANK0 (1u << 9u)
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/** Reset bit for UART0 peripheral */
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#define RESET_UART0 (1u << 26u)
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/** Reset bit for UART1 peripheral */
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#define RESET_UART1 (1u << 27u)
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/** Reset bit for the IO bank 0 */
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#define RESET_IO_BANK0 (1u << 6u)
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/** Input enable bit for GPIO0 in PADS_BANK0 */
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#define PADS_BANK0_GPIO0_IE_BITS (1u << 6u)
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/** Isolation bits for PADS_BANK0 */
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#define PADS_BANK0_ISO_BITS (1u << 8u)
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Calculate the address of the GPIO pad register for a given pin
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* @param pin The GPIO pin number
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* @return The address of the GPIO pad register for the given pin
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*/
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static inline uint32_t calculate_gpio_pad_register_addr(gpio_t pin) {
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/* Each pin has a 4 byte register, so we can calculate the address
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* by adding 4 bytes for each pin, starting at the base address of PADS_BANK0
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* and adding 4 bytes to skip VOLTAGE_SELECT */
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return PADS_BANK0_BASE + 4 * (pin + 1);
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}
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/**
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* @brief Calculate the address of the GPIO IO status register for a given pin
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* @param pin The GPIO pin number
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* @return The address of the GPIO IO status register for the given pin
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*/
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static uint32_t calculate_gpio_io_status_register_addr(gpio_t pin) {
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/* Each status register is followed by a ctrl register, */
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return IO_BANK0_BASE + 8 * pin;
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}
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/**
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* @brief Calculate the address of the GPIO IO control register for a given
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* pin
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* @param pin The GPIO pin number
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* @return The address of the GPIO IO control register for the given pin
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*/
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static inline uint32_t calculate_gpio_io_ctrl_register_addr(gpio_t pin) {
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/* Each pin has a 8 byte register (4 Bytes of Status, 4 Bytes of CTRL),
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* so we can calculate the address by adding 8 bytes for each pin,
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* starting at the base address of IO_BANK0 */
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return calculate_gpio_io_status_register_addr(pin) + 4;
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}
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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