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4218fca673
This patch allows boards to select a max ADC clock speed. This could be handy if the board wants to clock the ADC differently according to the board's front end analog circuitry or MCU model's ADC capabilities.
147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/*
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* Copyright (C) 2016 Engineering-Spirit
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_periph_adc
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* @{
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*
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* @file
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* @brief Low-level ADC driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "periph/adc.h"
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#include "periph_conf.h"
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#include "periph/vbat.h"
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/**
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* @brief Maximum allowed ADC clock speed
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*/
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#ifndef ADC_CLK_MAX
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#define ADC_CLK_MAX MHZ(12)
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#endif
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/**
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* @brief Default VBAT undefined value
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*/
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#ifndef VBAT_ADC
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#define VBAT_ADC ADC_UNDEF
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#endif
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/**
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* @brief Allocate locks for all three available ADC devices
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*/
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static mutex_t locks[] = {
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#if ADC_DEVS > 1
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MUTEX_INIT,
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#endif
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#if ADC_DEVS > 2
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MUTEX_INIT,
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#endif
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MUTEX_INIT
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};
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static inline ADC_TypeDef *dev(adc_t line)
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{
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return (ADC_TypeDef *)(ADC1_BASE + (adc_config[line].dev << 8));
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}
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static inline void prep(adc_t line)
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{
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mutex_lock(&locks[adc_config[line].dev]);
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periph_clk_en(APB2, (RCC_APB2ENR_ADC1EN << adc_config[line].dev));
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}
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static inline void done(adc_t line)
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{
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periph_clk_dis(APB2, (RCC_APB2ENR_ADC1EN << adc_config[line].dev));
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mutex_unlock(&locks[adc_config[line].dev]);
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}
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int adc_init(adc_t line)
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{
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uint32_t clk_div = 2;
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/* check if the line is valid */
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if (line >= ADC_NUMOF) {
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return -1;
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}
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/* lock and power-on the device */
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prep(line);
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/* configure the pin */
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if (adc_config[line].pin != GPIO_UNDEF) {
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gpio_init_analog(adc_config[line].pin);
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}
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/* set clock prescaler to get the maximal possible ADC clock value */
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for (clk_div = 2; clk_div < 8; clk_div += 2) {
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if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
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break;
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}
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}
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ADC->CCR = ((clk_div / 2) - 1) << 16;
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/* enable the ADC module */
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dev(line)->CR2 = ADC_CR2_ADON;
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/* free the device again */
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done(line);
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return 0;
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}
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int32_t adc_sample(adc_t line, adc_res_t res)
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{
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int sample;
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/* check if resolution is applicable */
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if (res < 0xff) {
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return -1;
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}
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/* lock and power on the ADC device */
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prep(line);
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/* check if this is the VBAT line or another internal ADC channel */
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if (IS_USED(MODULE_PERIPH_VBAT) && line == VBAT_ADC) {
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vbat_enable();
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}
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else if (dev(line) == ADC1) {
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if (adc_config[line].chan == 16 || adc_config[line].chan == 17) {
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ADC->CCR |= ADC_CCR_TSVREFE;
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}
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}
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/* set resolution and conversion channel */
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dev(line)->CR1 = res;
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dev(line)->SQR3 = adc_config[line].chan;
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/* start conversion and wait for results */
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dev(line)->CR2 |= ADC_CR2_SWSTART;
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while (!(dev(line)->SR & ADC_SR_EOC)) {}
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/* finally read sample and reset the STRT bit in the status register */
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sample = (int)dev(line)->DR;
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/* check if this is the VBAT line or another internal ADC channel */
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if (IS_USED(MODULE_PERIPH_VBAT) && line == VBAT_ADC) {
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vbat_disable();
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}
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else if (dev(line) == ADC1) {
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if (adc_config[line].chan == 16 || adc_config[line].chan == 17) {
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ADC->CCR &= ~ADC_CCR_TSVREFE;
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}
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}
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/* power off and unlock device again */
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done(line);
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return sample;
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}
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