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718e4a8340
16782: drivers/mfrc522: add new driver r=benpicco a=HendrikVE ### Contribution description This PR adds support for the MFRC522. It is quite common in the Arduino world and it is quite cheap. The driver connects to the MFRC522 via SPI and is heavily based on the Arduino driver available [here](https://github.com/miguelbalboa/rfid). Basically it was ported, but with several improvements in readability and documentation. ### Testing procedure The given (manual) test provides single commands for some driver functions. 19201: cpu/gd32v: add periph_i2c support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_i2c` support and is one of a bunch of PRs that complete the peripheral drivers for GD32VF103. The driver is a modified version of the driver for STM32F1 with some changes that were necessary to get it working on GD32V. As for STM32F1, the driver is using polling instead of interrupts for now. It will be implemented interrupt-driven later. ### Testing procedure `tests/periph_i2c` as well as a test with any I2C sensor should work. The driver was tested with `tests/driver_l3gxxxx` and `tests/driver_bmp180`. ### Issues/PRs references Co-authored-by: Hendrik van Essen <hendrik.ve@fu-berlin.de> Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
368 lines
10 KiB
C
368 lines
10 KiB
C
/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_gd32v
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Koen Zandberg <koen@bergzand.net>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include <inttypes.h>
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#include "cpu.h"
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#include "clic.h"
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#include "kernel_defines.h"
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#include "macros/units.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Power management configuration
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* @{
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*/
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/**
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* @brief Number of usable low power modes
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*/
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#define PM_NUM_MODES (3U) /**< Number of usable low power modes */
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/**
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* @brief Power modes
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*
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* The GD32V has three power modes (terminology as defined by GigaDevice).
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* - Sleep: Only the clock of the RISC-V core is switched off.
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* - Deep sleep: The RISC-V core including all AHB and APB peripheralsa and all
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* high speed clocks are off. The LDO is in operation and the
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* SRAM is retained.
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* The MCU can be woken up by external interrupts or events
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* without restart.
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* - Standby: The RISC-V core including all AHB and APB peripherals, all
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* high-speed clocks, and the LDO are off. The SRAM is not
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* retained.
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* The MCU can be woken up by WKUP or the NRST pin, watchdog
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* reset and RTC alarms with restart.
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*/
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enum {
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GD32V_PM_STANDBY = 0, /**< STANDBY mode, */
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GD32V_PM_DEEPSLEEP = 1, /**< DEEPSLEEP mode, corresponds to STOP mode of STM32 */
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GD32V_PM_IDLE = 2 /**< IDLE mode */
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};
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/**
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* @brief Wake-up pin used
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*/
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#ifndef CONFIG_PM_EWUP_USED
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#define CONFIG_PM_EWUP_USED (0U)
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#endif
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/** @} */
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/**
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* @brief On-Chip buses
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*/
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typedef enum {
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AHB, /**< Advanced High-performance Bus */
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APB1, /**< Advanced Peripheral Bus 1 */
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APB2, /**< Advanced Peripheral Bus 2 */
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} bus_t;
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/**
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* @brief Available GPIO ports
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*/
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enum {
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#ifdef GPIOA
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PORT_A = 0, /**< port A */
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#endif
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#ifdef GPIOB
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PORT_B = 1, /**< port B */
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#endif
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#ifdef GPIOC
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PORT_C = 2, /**< port C */
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#endif
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#ifdef GPIOD
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PORT_D = 3, /**< port D */
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#endif
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#ifdef GPIOE
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PORT_E = 4, /**< port E */
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#endif
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};
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#ifndef DOXYGEN
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/**
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* @brief Overwrite the default gpio_t type definition
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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/** @} */
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/**
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* @brief Definition of a fitting UNDEF value
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*/
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#define GPIO_UNDEF (0xffffffff)
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/**
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* @brief Define a CPU specific GPIO pin generator macro
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*/
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#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
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/**
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* @brief Generate GPIO mode bitfields
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*
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* We use 5 bit to encode the mode:
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* - bit 0+1: pin mode (input / output)
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* - bit 2+3: pull resistor configuration
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* - bit 4: output type (0: push-pull, 1: open-drain)
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*/
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#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
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/**
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* @brief Override GPIO mode options
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*
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* We use 4 bit to encode CNF and MODE.
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* @{
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = GPIO_MODE(0, 1, 0), /**< input w/o pull R */
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GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
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GPIO_IN_PU = GPIO_MODE(0, 2, 1), /**< input with pull-up */
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GPIO_OUT = GPIO_MODE(3, 0, 0), /**< push-pull output */
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GPIO_OD = GPIO_MODE(3, 1, 0), /**< open-drain w/o pull R */
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GPIO_OD_PU = (0xff) /**< not supported by HW */
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} gpio_mode_t;
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/** @} */
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/**
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* @brief Override flank configuration values
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* @{
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*/
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_RISING = 1, /**< emit interrupt on rising flank */
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GPIO_FALLING = 2, /**< emit interrupt on falling flank */
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GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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} gpio_flank_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Override alternative GPIO mode options
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*/
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typedef enum {
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GPIO_AF_OUT_PP = 0xb, /**< alternate function output - push-pull */
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GPIO_AF_OUT_OD = 0xf, /**< alternate function output - open-drain */
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} gpio_af_t;
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/**
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* @brief GD32V timers have 4 capture-compare channels
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*/
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#define TIMER_CHANNEL_NUMOF (4U)
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/**
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* @brief Macro for accessing the capture/compare register of a timer channel
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*/
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#define TIMER_CHANNEL(tim, chan) *(&dev(tim)->CH0CV + (chan * 2))
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/**
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* @brief Timer configuration
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*/
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typedef struct {
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TIMER_Type *dev; /**< timer device */
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uint32_t max; /**< maximum value to count to (16/32 bit) */
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uint32_t rcu_mask; /**< corresponding bit in the RCC register */
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uint8_t bus; /**< APBx bus the timer is clock from */
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uint8_t irqn; /**< global IRQ channel */
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} timer_conf_t;
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/**
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* @brief Structure for UART configuration data
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*/
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typedef struct {
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USART_Type *dev; /**< UART device base register address */
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uint32_t rcu_mask; /**< bit in clock enable register */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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uint8_t bus; /**< APB bus */
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uint8_t irqn; /**< IRQ channel */
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} uart_conf_t;
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/**
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* @brief UART interrupt priority
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*/
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#define UART_ISR_PRIO (2)
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/**
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* @name This CPU makes use of the following shared SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
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#define PERIPH_SPI_NEEDS_TRANSFER_REG 1
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
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/** @} */
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/**
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* @brief Structure for SPI configuration data
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*/
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typedef struct {
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uint32_t addr; /**< SPI control register address */
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gpio_t mosi; /**< MOSI pin */
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gpio_t miso; /**< MISO pin */
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gpio_t sclk; /**< SCLK pin */
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} spi_conf_t;
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/**
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* @name Use the shared I2C functions
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* @{
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*/
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/** Use read reg function from periph common */
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#define PERIPH_I2C_NEED_READ_REG
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/** Use write reg function from periph common */
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#define PERIPH_I2C_NEED_WRITE_REG
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/** Use read regs function from periph common */
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#define PERIPH_I2C_NEED_READ_REGS
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/** Use write regs function from periph common */
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#define PERIPH_I2C_NEED_WRITE_REGS
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Default mapping of I2C bus speed values
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = KHZ(10), /**< low speed mode: ~10kit/s */
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I2C_SPEED_NORMAL = KHZ(100), /**< normal mode: ~100kbit/s */
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I2C_SPEED_FAST = KHZ(400), /**< fast mode: ~400kbit/s */
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I2C_SPEED_FAST_PLUS = MHZ(1), /**< fast plus mode: ~1Mbit/s */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C configuration options
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*/
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typedef struct {
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I2C_Type *dev; /**< i2c device */
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i2c_speed_t speed; /**< i2c bus speed */
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gpio_t scl_pin; /**< scl pin number */
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gpio_t sda_pin; /**< sda pin number */
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uint32_t rcu_mask; /**< bit in clock enable register */
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uint8_t irqn; /**< I2C event interrupt number */
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} i2c_conf_t;
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/**
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* @brief PWM channel
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*/
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typedef struct {
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gpio_t pin; /**< GPIO pin mapped to this channel */
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uint8_t cc_chan; /**< capture compare channel used */
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} pwm_chan_t;
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/**
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* @brief PWM configuration
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*/
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typedef struct {
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TIMER_Type *dev; /**< Timer used */
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uint32_t rcu_mask; /**< bit in clock enable register */
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uint32_t remap; /**< AFIO remap mask to route periph
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to other pins (or zero, if not
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needed) */
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pwm_chan_t chan[TIMER_CHANNEL_NUMOF]; /**< channel mapping set to
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{GPIO_UNDEF, 0} if not used */
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gpio_af_t af; /**< alternate function used */
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uint8_t bus; /**< APB bus */
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} pwm_conf_t;
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/**
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* @name WDT upper and lower bound times in ms
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* @{
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*/
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#define NWDT_TIME_LOWER_LIMIT (1)
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/* Ensure the internal "count" variable stays within the uint32 bounds.
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This variable corresponds to max_time * RTC_FREQ / MS_PER_SEC. On fe310,
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RTC_FREQ is 32768Hz. The 15 right shift is equivalent to a division by RTC_FREQ.
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*/
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#define NWDT_TIME_UPPER_LIMIT ((UINT32_MAX >> 15) * MS_PER_SEC + 1)
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/** @} */
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/**
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* @brief WDT interrupt priority: use highest priority
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*/
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#define WDT_INTR_PRIORITY (PLIC_NUM_PRIORITIES)
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/**
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* @brief No brakes on the WDT train
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*/
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#define WDT_HAS_STOP (0)
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/**
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* @name RTT/RTC configuration
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* @{
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*/
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#define RTT_DEV RTC /**< RTC is used as RTT device */
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#define RTT_IRQ RTC_ALARM_IRQn /**< RTC_ALARM_IRQn is used as IRQ number */
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#define RTT_IRQ_PRIORITY (2) /**< RTT interrupt priority */
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#define RTT_MAX_VALUE (0xffffffff) /**< maximum RTT value */
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#define RTT_MIN_FREQUENCY (1U) /**< minimum RTT frequency in Hz */
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/** @} */
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/**
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* @brief Enable the given peripheral clock
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*
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* @param[in] bus bus the peripheral is connected to
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* @param[in] mask bit in the RCU enable register
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*/
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void periph_clk_en(bus_t bus, uint32_t mask);
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/**
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* @brief Disable the given peripheral clock
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*
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* @param[in] bus bus the peripheral is connected to
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* @param[in] mask bit in the RCU enable register
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*/
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void periph_clk_dis(bus_t bus, uint32_t mask);
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/**
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* @brief Get the actual bus clock frequency for the APB buses
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*
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* @param[in] bus target APBx bus
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*
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* @return bus clock frequency in Hz
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*/
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uint32_t periph_apb_clk(bus_t bus);
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/**
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* @brief Configure the alternate function for the given pin
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*
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* @param[in] pin pin to configure
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* @param[in] af alternate function to use
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*/
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void gpio_init_af(gpio_t pin, gpio_af_t af);
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void gd32vf103_clock_init(void);
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void gd32v_enable_irc8(void);
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void gd32v_disable_irc8(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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