mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-12-24 05:53:49 +01:00
79198e92b9
Defining the SRAM4 start address as 0 when the SRAM4 length is not defined invalidates the corresponding heap entry.
42 lines
895 B
Plaintext
42 lines
895 B
Plaintext
/*
|
|
* Copyright (C) 2017 Inria
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU Lesser
|
|
* General Public License v2.1. See the file LICENSE in the top level
|
|
* directory for more details.
|
|
*/
|
|
|
|
/**
|
|
* @addtogroup cpu_cortexm_common
|
|
* @{
|
|
*
|
|
* @file
|
|
* @brief Memory definitions for the Cortex-M family
|
|
*
|
|
* @author Francisco Acosta <francisco.acosta@inria.fr>
|
|
*
|
|
* @}
|
|
*/
|
|
|
|
ccmram_length = DEFINED( _ccmram_len ) ? _ccmram_len : 0x0 ;
|
|
|
|
sram4_addr = DEFINED( _sram4_length ) ? 0x28000000 : 0x0 ;
|
|
sram4_length = DEFINED( _sram4_length ) ? _sram4_length : 0x0 ;
|
|
|
|
MEMORY
|
|
{
|
|
ccmram : ORIGIN = 0x10000000, LENGTH = ccmram_length
|
|
sram4 : ORIGIN = sram4_addr, LENGTH = sram4_length
|
|
}
|
|
|
|
SECTIONS
|
|
{
|
|
.heap2 ALIGN(4) (NOLOAD) :
|
|
{
|
|
_sheap2 = ORIGIN(sram4);
|
|
_eheap2 = ORIGIN(sram4) + LENGTH(sram4);
|
|
} > sram4
|
|
}
|
|
|
|
INCLUDE cortexm.ld
|