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53 lines
2.0 KiB
C
53 lines
2.0 KiB
C
/*
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* Copyright (C) 2017, 2019 Ken Rabold, JP Bonn
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_fe310
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the clock initialization for SiFive FE310
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*
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* @author Ken Rabold
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* @}
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*/
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#include "cpu.h"
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#include "periph_conf.h"
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#include "vendor/encoding.h"
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#include "vendor/platform.h"
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#include "vendor/prci_driver.h"
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void clock_init(void)
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{
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/* In case we are executing from QSPI, (which is quite likely) we need to
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* set the QSPI clock divider appropriately before boosting the clock
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* frequency. PRCI_set_hfrosctrim_for_f_cpu() tries multiple clocks
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* so choose a safe value that should work for all frequencies.
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*/
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SPI0_REG(SPI_REG_SCKDIV) = SCKDIV_SAFE;
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/* Note: The range is limited to ~100MHz and depends on PLL settings */
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PRCI_set_hfrosctrim_for_f_cpu(CPU_DESIRED_FREQ, PRCI_FREQ_UNDERSHOOT);
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/* begin{code-style-ignore} */
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SPI0_REG(SPI_REG_FFMT) = /* setup "Fast Read Dual I/O" */
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SPI_INSN_CMD_EN | /* Enable memory-mapped flash */
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SPI_INSN_ADDR_LEN(3) | /* 25LP03D read commands have 3 address bytes */
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SPI_INSN_PAD_CNT(4) | /* 25LP03D Table 6.11 Read Dummy Cycles = 4 */
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SPI_INSN_CMD_PROTO(SPI_PROTO_S) | /* 25LP03D Table 8.1 "Instruction */
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SPI_INSN_ADDR_PROTO(SPI_PROTO_D) | /* Set" shows mode for cmd, addr, and */
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SPI_INSN_DATA_PROTO(SPI_PROTO_D) | /* data protocol for given instruction */
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SPI_INSN_CMD_CODE(0xBB) | /* Set the instruction to "Fast Read Dual I/O" */
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SPI_INSN_PAD_CODE(0x00); /* Dummy cycle sends 0 value bits */
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/* end{code-style-ignore} */
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SPI0_REG(SPI_REG_SCKDIV) = SCKDIV;
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}
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