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124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Gunar Schorcht
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @defgroup cpu_esp32_conf ESP32 compile configurations
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* @ingroup cpu_esp32
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* @ingroup config
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* @brief Compile-time configuration macros for ESP32x SoCs
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* @{
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*
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* @file
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* @brief Compile compile-time configurations that are common for all ESP32x SoCs
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#if !defined(__ASSEMBLER__)
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# include <stdint.h>
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#endif
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/**
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* @name Stack size configuration
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* @{
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*/
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/** Extra thread stack size required if newlib-nano is not used */
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#ifdef MODULE_NEWLIB_NANO
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# define THREAD_EXTRA_STACKSIZE (0)
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#else
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# define THREAD_EXTRA_STACKSIZE (512)
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#endif
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/** Extra thread stack size if `printf` is used */
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#define THREAD_EXTRA_STACKSIZE_PRINTF (1536)
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#ifndef THREAD_STACKSIZE_DEFAULT
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/** Default thread stack size */
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# define THREAD_STACKSIZE_DEFAULT (2048)
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#endif
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#ifndef THREAD_STACKSIZE_IDLE
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/** Stack size for the idle thread */
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# define THREAD_STACKSIZE_IDLE (2048)
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#endif
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#ifndef ESP_WIFI_STACKSIZE
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/** Stack size for the WiFi thread */
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# define ESP_WIFI_STACKSIZE (THREAD_STACKSIZE_DEFAULT + THREAD_EXTRA_STACKSIZE)
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#endif
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/** @} */
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/** Buffer size used for printf functions (maximum length of formatted output). */
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#define PRINTF_BUFSIZ 256
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/**
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* @brief Attribute for memory sections required by SRAM PUF
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*/
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#define PUF_SRAM_ATTRIBUTES __attribute__((used, section(".noinit")))
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/**
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* @brief Support of unaligned access
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*
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* All ESP32x SoCs allow unaligned read/write access to the RAM as well as
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* unaligned read access to the constant data in the flash, which is accessible
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* via the data bus and mapped by the MMU into the data address space of
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* the CPU.
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*/
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#define CPU_HAS_UNALIGNED_ACCESS 1
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/**
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* @name Flash page configuration
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* @{
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*/
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#if !DOXYGEN && !defined(__ASSEMBLER__)
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/* start address of flash pages in CPU address space as determined by the linker */
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extern uint8_t _fp_mmu_start;
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#endif
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#define FLASHPAGE_SIZE (4096U) /**< Size of pages (flash sectors) in bytes */
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#define FLASHPAGE_WRITE_BLOCK_SIZE (4U) /**< Minimum write block size */
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U) /**< Write block alignment */
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/**
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* @brief Number of pages
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*/
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#define FLASHPAGE_NUMOF (CONFIG_ESP_FLASHPAGE_CAPACITY / FLASHPAGE_SIZE)
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/**
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* @brief CPU base address for flash page access as determined by the linker
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*/
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#define CPU_FLASH_BASE ((uint32_t)&_fp_mmu_start)
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/** @} */
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/* include ESP32x SoC specific compile time configurations */
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#if defined(CPU_FAM_ESP32)
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# include "cpu_conf_esp32.h"
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#elif defined(CPU_FAM_ESP32C3)
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# include "cpu_conf_esp32c3.h"
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#elif defined(CPU_FAM_ESP32C6)
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# include "cpu_conf_esp32c6.h"
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#elif defined(CPU_FAM_ESP32H2)
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# include "cpu_conf_esp32h2.h"
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#elif defined(CPU_FAM_ESP32S2)
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# include "cpu_conf_esp32s2.h"
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#elif defined(CPU_FAM_ESP32S3)
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# include "cpu_conf_esp32s3.h"
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#else
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# error "ESP32x family implementation missing"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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