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The commit defines a new common CPU symbol `CPU_COMMON_ESP32X` in Kconfig that is used by all `CPU_FAM_ESP32x` symbols which selects features, modules and packages that are common for all ESP32x SoC variants. This avoids the selection of features, modules and packages again and again for each ESP32x SoC variant.
99 lines
2.4 KiB
Plaintext
99 lines
2.4 KiB
Plaintext
# Copyright (c) 2020 HAW Hamburg
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# 2022 Gunar Schorcht
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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## Definition of specific features
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config HAS_ARCH_ESP32
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bool
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help
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Indicates that the current architecture is any ESP32x SoC architecture.
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config HAS_CPU_ESP32
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bool
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help
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Indicates that the current CPU belongs to the ESP32x SoC series.
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config HAS_ESP_BLE
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bool
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help
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Indicates that the used ESP32x SoC supports Bluetooth LE.
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config HAS_ESP_BLE_ESP32
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bool
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help
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Indicates that the ESP32x SoC uses the SDK Bluetooth LE library
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for the ESP32 variant.
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config HAS_ESP_BLE_ESP32C3
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bool
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help
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Indicates that the ESP32x SoC uses the SDK Bluetooth LE library
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for the ESP32-C3 or ESP32-S3 variant.
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config HAS_ESP_HW_COUNTER
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bool
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help
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Indicates that the used ESP32x SoC supports HW counters that can be
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used as timers.
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config HAS_ESP_RMT
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bool
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help
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Indicates that the ESP32x SoC has a RMT peripheral.
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config HAS_ESP_RTC_TIMER_32K
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bool
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help
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Indicates that an external 32.768 kHz crystal is connected to the
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ESP32x Soc on the board.
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config HAS_ESP_SPI_RAM
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bool
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help
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Indicates that an external RAM is connected via the SPI interface to
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the ESP32x SoC on the board.
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config HAS_ESP_SPI_OCT
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bool
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help
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Indicates that Octal SPI mode is used for Flash and SPI RAM. In this
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case additional GPIOs are used for the SPI interface and cannot be
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used for other purposes.
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config CPU
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default "esp32" if HAS_CPU_ESP32
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config CPU_CORE_XTENSA_LX6
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bool
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select CPU_ARCH_XTENSA
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help
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CPU core of the ESP32x SoC is a Xtensa LX6.
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config CPU_CORE_XTENSA_LX7
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bool
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select CPU_ARCH_XTENSA
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help
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CPU core of the ESP32x SoC is a Xtensa LX7.
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config CPU_CORE_RV32IMC
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bool
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select CPU_ARCH_RISCV
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help
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CPU core of the ESP32x SoC is a RISC-V core.
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config CPU_CORE
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default "xtensa-lx6" if CPU_CORE_XTENSA_LX6
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default "xtensa-lx7" if CPU_CORE_XTENSA_LX7
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default "rv32imc" if CPU_CORE_RV32IMC
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rsource "Kconfig.esp32x"
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rsource "Kconfig.esp32"
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rsource "Kconfig.esp32c3"
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rsource "Kconfig.esp32s3"
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rsource "Kconfig.esp32s2"
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source "$(RIOTCPU)/esp_common/Kconfig"
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