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78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2015 Kaspar Schleiser <kaspar@schleiser.de>
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* SPDX-FileCopyrightText: 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
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* SPDX-FileCopyrightText: 2018 RWTH Aachen, Josua Arndt <jarndt@ias.rwth-aachen.de>
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* SPDX-FileCopyrightText: 2021 Gerson Fernando Budke <nandojve@gmail.com>
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup cpu_atmega_common
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* @brief Common clock support for ATmega family based micro-controllers
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* @{
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*
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* @file
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* @brief Basic definitions for the ATmega common clock
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*
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* When ever you want to do something hardware related, that is accessing MCUs registers directly,
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* just include this file. It will then make sure that the MCU specific headers are included.
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*
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* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Josua Arndt <jarndt@ias.rwth-aachen.de>
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*
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*/
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief ATmega system clock prescaler settings
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*
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* Some CPUs may not support the highest prescaler settings
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*/
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enum {
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CPU_ATMEGA_CLK_SCALE_DIV1 = 0,
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CPU_ATMEGA_CLK_SCALE_DIV2 = 1,
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CPU_ATMEGA_CLK_SCALE_DIV4 = 2,
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CPU_ATMEGA_CLK_SCALE_DIV8 = 3,
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CPU_ATMEGA_CLK_SCALE_DIV16 = 4,
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CPU_ATMEGA_CLK_SCALE_DIV32 = 5,
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CPU_ATMEGA_CLK_SCALE_DIV64 = 6,
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CPU_ATMEGA_CLK_SCALE_DIV128 = 7,
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CPU_ATMEGA_CLK_SCALE_DIV256 = 8,
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CPU_ATMEGA_CLK_SCALE_DIV512 = 9,
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};
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/**
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* @brief Initializes system clock prescaler
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*/
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static inline void atmega_set_prescaler(uint8_t clk_scale)
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{
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/* Enable clock change */
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#ifdef CLKPR
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/* Must be assignment to set all other bits to zero, see datasheet */
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CLKPR = (1 << CLKPCE);
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/* Write clock within 4 cycles */
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CLKPR = clk_scale;
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#else
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(void) clk_scale;
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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