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https://github.com/RIOT-OS/RIOT.git
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ae0beee99e
The CC2538 does not support "Open Drain" or "Open Drain with Pullup" outputs. However problems can arrise from setting both macros to the same value. This commit sets them to separate values which are both invalid to avoid conflicts with other applications.
391 lines
11 KiB
C
391 lines
11 KiB
C
/*
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* Copyright (C) 2015-2016 Freie Universität Berlin
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* 2017 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc2538
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Sebastian Meiling <s@mlng.net>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include <stdint.h>
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#include <stdio.h>
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#include "vendor/hw_soc_adc.h"
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#include "cpu.h"
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#include "vendor/hw_ssi.h"
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#include "vendor/hw_uart.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Starting offset of CPU_ID
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*/
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#define CPUID_ADDR (&IEEE_ADDR_MSWORD)
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/**
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* @brief Length of the CPU_ID in octets
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*/
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#define CPUID_LEN (8U)
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/**
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* @name Define a custom type for GPIO pins
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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/** @} */
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (5)
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/** @} */
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/**
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* @brief Define custom value to specify undefined or unused GPIOs
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*/
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#define GPIO_UNDEF (0xffffffff)
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/**
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* @brief Custom value to indicate unused parameter in gpio_init_mux
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*/
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#define GPIO_MUX_NONE (0xff)
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/**
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* @brief Define a custom GPIO_PIN macro
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*
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* For the CC2538, we use OR the gpio ports base register address with the
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* actual pin number.
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*/
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#define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_BASE + \
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(port << GPIO_PORTNUM_SHIFT)) | pin)
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/**
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* @brief Configure an alternate function for the given pin
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*
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* @param[in] pin gpio pin
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* @param[in] sel Select pin peripheral function
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* @param[in] over Override pin configuration
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*/
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void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over);
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/**
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* @brief Configure an alternate function for the given pin
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*
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* @param[in] pin gpio pin
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* @param[in] over Override pin configuration
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* @param[in] sel Set peripheral function for pin (output)
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* @param[in] func Set pin for peripheral function (input)
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*/
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void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func);
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/**
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* @name Use shared I2C functions
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* @{
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*/
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#define PERIPH_I2C_NEED_READ_REG
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#define PERIPH_I2C_NEED_READ_REGS
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#define PERIPH_I2C_NEED_WRITE_REG
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#define PERIPH_I2C_NEED_WRITE_REGS
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/** @} */
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#ifndef DOXYGEN
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/**
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* @name Override I2C clock speed values
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = 0x01, /**< not supported */
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I2C_SPEED_NORMAL = 100000U, /**< normal mode: ~100kbit/s */
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I2C_SPEED_FAST = 400000U, /**< fast mode: ~400kbit/s */
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I2C_SPEED_FAST_PLUS = 0x02, /**< not supported */
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I2C_SPEED_HIGH = 0x03, /**< not supported */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C configuration options
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*/
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typedef struct {
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i2c_speed_t speed; /**< baudrate used for the bus */
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gpio_t scl_pin; /**< pin used for SCL */
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gpio_t sda_pin; /**< pin used for SDA */
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} i2c_conf_t;
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/**
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* @name declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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#ifndef DOXYGEN
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/**
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* @name Override the default GPIO mode settings
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* @{
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = ((uint8_t)OVERRIDE_DISABLE), /**< input, no pull */
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GPIO_IN_ANALOG = ((uint8_t)OVERRIDE_ANALOG), /**< input, analog */
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GPIO_IN_PD = ((uint8_t)OVERRIDE_PULLDOWN), /**< input, pull-down */
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GPIO_IN_PU = ((uint8_t)OVERRIDE_PULLUP), /**< input, pull-up */
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GPIO_OUT = ((uint8_t)OVERRIDE_ENABLE), /**< output */
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GPIO_OD = (0xfe), /**< not supported */
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GPIO_OD_PU = (0xff) /**< not supported */
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} gpio_mode_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @name UART device configuration
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* @{
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*/
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typedef struct {
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cc2538_uart_t *dev; /**< pointer to the used UART device */
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gpio_t rx_pin; /**< pin used for RX */
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gpio_t tx_pin; /**< pin used for TX */
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#ifdef MODULE_PERIPH_UART_HW_FC
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gpio_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using */
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gpio_t rts_pin; /**< RTS pin - set to GPIO_UNDEF when not using */
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#endif
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} uart_conf_t;
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Override parity values
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* @{
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*/
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#define HAVE_UART_PARITY_T
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typedef enum {
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UART_PARITY_NONE = 0, /**< no parity */
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UART_PARITY_EVEN = (UART_LCRH_PEN | UART_LCRH_EPS), /**< even parity */
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UART_PARITY_ODD = UART_LCRH_PEN, /**< odd parity */
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UART_PARITY_MARK = (UART_LCRH_PEN | UART_LCRH_SPS), /**< mark */
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UART_PARITY_SPACE = (UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_SPS) /**< space */
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} uart_parity_t;
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/** @} */
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/**
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* @brief Override data bits length values
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* @{
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*/
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#define HAVE_UART_DATA_BITS_T
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typedef enum {
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UART_DATA_BITS_5 = (0 << UART_LCRH_WLEN_S), /**< 5 data bits */
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UART_DATA_BITS_6 = (1 << UART_LCRH_WLEN_S), /**< 6 data bits */
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UART_DATA_BITS_7 = (2 << UART_LCRH_WLEN_S), /**< 7 data bits */
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UART_DATA_BITS_8 = (3 << UART_LCRH_WLEN_S), /**< 8 data bits */
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} uart_data_bits_t;
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/** @} */
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/**
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* @brief Override stop bits length values
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* @{
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*/
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#define HAVE_UART_STOP_BITS_T
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typedef enum {
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UART_STOP_BITS_1 = 0, /**< 1 stop bit */
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UART_STOP_BITS_2 = UART_LCRH_STP2, /**< 2 stop bits */
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} uart_stop_bits_t;
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/** @} */
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/**
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* @brief Size of the UART TX buffer for non-blocking mode.
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*/
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#ifndef UART_TXBUF_SIZE
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#define UART_TXBUF_SIZE (64)
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#endif
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/**
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* @brief Define value for unused CS line
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*/
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#define SPI_CS_UNDEF (GPIO_UNDEF)
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#ifndef DOXYGEN
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/**
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* @brief Overwrite the default spi_cs_t type definition
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* @{
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*/
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#define HAVE_SPI_CS_T
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typedef uint32_t spi_cs_t;
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/** @} */
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#endif
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/**
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* @name Override SPI mode settings
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
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SPI_MODE_1 = (SSI_CR0_SPH), /**< CPOL=0, CPHA=1 */
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SPI_MODE_2 = (SSI_CR0_SPO), /**< CPOL=1, CPHA=0 */
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SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH) /**< CPOL=1, CPHA=1 */
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} spi_mode_t;
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/** @ */
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/**
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* @name Override SPI clock settings
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = 0, /**< drive the SPI bus with 100KHz */
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SPI_CLK_400KHZ = 1, /**< drive the SPI bus with 400KHz */
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SPI_CLK_1MHZ = 2, /**< drive the SPI bus with 1MHz */
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SPI_CLK_5MHZ = 3, /**< drive the SPI bus with 5MHz */
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SPI_CLK_10MHZ = 4 /**< drive the SPI bus with 10MHz */
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} spi_clk_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Datafields for static SPI clock configuration values
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*/
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typedef struct {
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uint8_t cpsr; /**< CPSR clock divider */
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uint8_t scr; /**< SCR clock divider */
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} spi_clk_conf_t;
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#ifndef BOARD_HAS_SPI_CLK_CONF
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/**
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* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
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*
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* SPI bus frequency = CLOCK_CORECLOCK / (CPSR * (SCR + 1)), with
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* CPSR = 2..254 and even,
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* SCR = 0..255
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*/
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static const spi_clk_conf_t spi_clk_config[] = {
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{ .cpsr = 64, .scr = 4 }, /* 100khz */
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{ .cpsr = 16, .scr = 4 }, /* 400khz */
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{ .cpsr = 32, .scr = 0 }, /* 1.0MHz */
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{ .cpsr = 2, .scr = 2 }, /* 5.3MHz */
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{ .cpsr = 2, .scr = 1 } /* 8.0MHz */
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};
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#endif /* BOARD_HAS_SPI_CLK_CONF */
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/**
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* @name SPI configuration data structure
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* @{
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*/
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typedef struct {
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uint8_t num; /**< number of SSI device, i.e. 0 or 1 */
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gpio_t mosi_pin; /**< pin used for MOSI */
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gpio_t miso_pin; /**< pin used for MISO */
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gpio_t sck_pin; /**< pin used for SCK */
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spi_cs_t cs_pin; /**< pin used for CS */
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} spi_conf_t;
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/** @} */
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/**
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* @brief Timer configuration
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*
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* General purpose timers (GPT[0-3]) are configured consecutively and in order
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* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
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*/
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typedef struct {
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uint_fast8_t chn; /**< number of channels */
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uint_fast8_t cfg; /**< timer config word */
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} timer_conf_t;
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#ifndef DOXYGEN
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/**
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* @name Override resolution options
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = (0xa00), /**< not supported by hardware */
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ADC_RES_7BIT = (0 << 4), /**< ADC resolution: 7 bit */
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ADC_RES_8BIT = (0xb00), /**< not supported by hardware */
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ADC_RES_9BIT = (1 << 4), /**< ADC resolution: 9 bit */
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ADC_RES_10BIT = (2 << 4), /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = (3 << 4), /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = (0xc00), /**< not supported by hardware */
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ADC_RES_16BIT = (0xd00), /**< not supported by hardware */
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} adc_res_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief ADC configuration wrapper
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*/
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typedef gpio_t adc_conf_t;
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/**
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* @name SOC_ADC_ADCCON3_EREF registers field values
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* @{
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*/
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#define SOC_ADC_ADCCON3_EREF_INT (0 << SOC_ADC_ADCCON3_EREF_S) /**< Internal reference */
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#define SOC_ADC_ADCCON3_EREF_EXT (1 << SOC_ADC_ADCCON3_EREF_S) /**< External reference on AIN7 pin */
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#define SOC_ADC_ADCCON3_EREF_AVDD5 (2 << SOC_ADC_ADCCON3_EREF_S) /**< AVDD5 pin */
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#define SOC_ADC_ADCCON3_EREF_DIFF (3 << SOC_ADC_ADCCON3_EREF_S) /**< External reference on AIN6-AIN7 differential input */
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/** @} */
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/**
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* @name Bit shift for data per ADC resolution
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* @{
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*/
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#define SOCADC_7_BIT_RSHIFT (9U) /**< Mask for getting data( 7 bits ENOB) */
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#define SOCADC_9_BIT_RSHIFT (7U) /**< Mask for getting data( 9 bits ENOB) */
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#define SOCADC_10_BIT_RSHIFT (6U) /**< Mask for getting data(10 bits ENOB) */
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#define SOCADC_12_BIT_RSHIFT (4U) /**< Mask for getting data(12 bits ENOB) */
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/** @} */
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/**
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* @name RTT configuration
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* @{
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*/
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#define RTT_DEV SMWDTHROSC
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#define RTT_IRQ SM_TIMER_ALT_IRQn
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#define RTT_IRQ_PRIO 1
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#define RTT_ISR isr_sleepmode
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_FREQUENCY (CLOCK_OSC32K)
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/* When setting a new compare value, the value must be at least 5 more
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than the current sleep timer value. Otherwise, the timer compare
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event may be lost. */
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#define RTT_MIN_OFFSET (5U)
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/** @} */
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/**
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* @name WDT upper and lower bound times in ms
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* @{
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*/
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/* Limits are in clock cycles according to data sheet.
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As the WDT is clocked by a 32 kHz clock and supports 4 intervals */
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#define NWDT_TIME_LOWER_LIMIT (2U)
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#define NWDT_TIME_UPPER_LIMIT (1000U)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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