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RIOT/cpu/stm32/include/clk/clk_conf.h
2025-10-02 10:24:48 +02:00

50 lines
1.2 KiB
C

/*
* SPDX-FileCopyrightText: 2020 Inria
* SPDX-License-Identifier: LGPL-2.1-only
*/
#pragma once
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Main header for STM32 clock configuration
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
#include "f0f1f3/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7)
#include "f2f4f7/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4)
#include "g0g4/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32C0)
#include "c0/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#include "l0l1/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
#include "l4l5wx/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32U5)
#include "u5/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32MP1)
#include "mp1/cfg_clock_default.h"
#else
#error "No clock configuration available"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/** @} */