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RIOT/cpu/stm32/include/periph/cpu_qdec.h
2025-10-02 10:24:48 +02:00

66 lines
1.6 KiB
C

/*
* SPDX-FileCopyrightText: 2016 Freie Universität Berlin
* SPDX-FileCopyrightText: 2017 OTA keys S.A.
* SPDX-License-Identifier: LGPL-2.1-only
*/
#pragma once
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief QDEC CPU specific definitions for the STM32 family
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
*/
#include <stdint.h>
#include "cpu.h"
#include "periph/cpu_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief All STM QDEC timers have 2 capture channels
*/
#define QDEC_CHAN (2U)
/**
* @brief QDEC channel
*/
typedef struct {
gpio_t pin; /**< GPIO pin mapped to this channel */
uint8_t cc_chan; /**< capture compare channel used */
} qdec_chan_t;
/**
* @brief QDEC configuration
*/
typedef struct {
TIM_TypeDef *dev; /**< Timer used */
uint32_t max; /**< Maximum counter value */
uint32_t rcc_mask; /**< bit in clock enable register */
qdec_chan_t chan[QDEC_CHAN]; /**< channel mapping, set to {GPIO_UNDEF, 0}
* if not used */
#ifdef CPU_FAM_STM32F1
uint32_t remap; /**< AFIO remap mask to route periph to other
pins (or zero, if not needed) */
#else
gpio_af_t af; /**< alternate function used */
#endif
uint8_t bus; /**< APB bus */
uint8_t irqn; /**< global IRQ channel */
} qdec_conf_t;
#ifdef __cplusplus
}
#endif
/** @} */