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73 lines
1.3 KiB
C
73 lines
1.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2017 Thomas Stilwell <stilwellt@openlabs.co>
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup boards_openlabs-kw41z-mini
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped ADC
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @author Thomas Stilwell <stilwellt@openlabs.co>
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*/
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ADC configuration
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*/
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static const saul_adc_params_t saul_adc_params[] =
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{
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{
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.name = "A0",
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.line = ADC_LINE(0),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "A1",
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.line = ADC_LINE(1),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "A2",
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.line = ADC_LINE(2),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "A3",
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.line = ADC_LINE(3),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "coretemp",
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.line = ADC_LINE(4),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "corebandgap",
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.line = ADC_LINE(5),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "dcdcvbat",
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.line = ADC_LINE(6),
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.res = ADC_RES_16BIT,
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},
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};
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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