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cde8ac6093
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB, Bluetooth Low Energy and in some variants NFC. This patch implements the first steps for having support for this CPU. While the QN908x can be considered the successor of similar chips from NXP like the KW41Z when looking at the feature set, the internal architecture, boot image format and CPU peripherals don't match those in the Kinetis line. Therefore, this patch creates a new directory for just the QN908x chip under cpu/qn908x. The minimal set of peripherals are implemented in this patch to allow the device to boot and enable a GPIO: the gpio and wdt peripheral modules only. The wdt driver is required to boot and disable the wdt. On reset, the wdt is disabled by the chip, however the QN908x bootloader stored in the internal ROM enables the wdt and sets a timer to reboot after 10 seconds, therefore it is needed to disable the wdt in RIOT OS soon after booting. This patch sets it up such that when no periph_wdt module is used the Watchdog is disabled, but if the periph_wdt is used it must be configured (initialized) within the first 10 seconds. Tests performed: Defined a custom board for this CPU and compiled a simple application that blinks some LEDs. Manually tested with periph_wdt and with periph_wdt_cb as well.
149 lines
4.0 KiB
C
149 lines
4.0 KiB
C
/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_qn908x
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author iosabi <iosabi@protonmail.com>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include <stdint.h>
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#include <stdbool.h>
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name CPU specific gpio_t type definition
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint16_t gpio_t;
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/** @} */
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/**
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* @brief Definition of a fitting UNDEF value
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*/
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#define GPIO_UNDEF (0xffff)
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/**
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* @brief Define a CPU specific GPIO pin generator macro.
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*
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* This generates the GPIO port base address with a mask of the GPIO_PIN value
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* to avoid a memory access. The value 12 here is selected as an optimization
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* to be able to derive the GPIO port address with a simple mask of the GPIO_PIN
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* value.
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*/
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#define GPIO_PIN(x, y) (((x) << 12u) | (y))
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/* QN908x has a unique default Bluetooth address in the Flash Information Page
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* descriptor. This value is set in the factory and cannot be modified by
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* users. However, the actual Bluetooth address used by the stack may be
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* different, this is just the default. */
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/**
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* @brief Starting offset of CPU_ID
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*/
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#define CPUID_ADDR (FSL_FEATURE_FLASH_ADDR_OF_VENDOR_BD_ADDR)
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/**
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* @brief Length of the CPU_ID in octets
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*/
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#define CPUID_LEN (6U)
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/**
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* @brief Watchdog clock can be stopped independently of other clocks.
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*/
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#define WDT_HAS_STOP (1)
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/**
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* @name WDT upper and lower bound times in ms
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* @{
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*/
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/** The WDT clock can run up to 16MHz (via CLK_APB) and the WDT counter is
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* 32-bit so the maximum value in ms we can wait is ((1 << 32) - 1) / 16000.
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* TODO: A much larger limit (~1.5 days) can be set if the WDT runs from the
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* 32 KHz clock. However, this is likely decided by the board and depends on the
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* clocks installed on the board. Figure out a way to configure this limit based
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* on the clock used.
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*/
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#define NWDT_TIME_LOWER_LIMIT (0)
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#define NWDT_TIME_UPPER_LIMIT (268435U)
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#define WWDT_TIME_LOWER_LIMIT (0)
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#define WWDT_TIME_UPPER_LIMIT (268435U)
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/** @} */
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/**
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* @brief Generate GPIO mode bitfields
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*
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* The GPIO_MODE has the following structure:
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* - bit 0: open-drain: 1 for enabled (open-drain mode) and 0 for disabled.
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* - bit 1: output-enabled: 1 output mode, 0 input mode.
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* - bit 4-5: pull_mode: 0 for hi-z (no pull-up or down), 1 for pull-down and 2
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* for pull-up. These correspond to the IOCON_MODE macros.
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*/
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#define GPIO_MODE(open_drain, out_enabled, pull_mode) \
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((open_drain) | ((out_enabled) << 1) | ((pull_mode) << 4))
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#ifndef DOXYGEN
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/**
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* @name GPIO pin modes
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* @{
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = GPIO_MODE(0, 0, 0), /**< IN */
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GPIO_IN_PD = GPIO_MODE(0, 0, 1), /**< IN with pull-down */
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GPIO_IN_PU = GPIO_MODE(0, 0, 2), /**< IN with pull-up */
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GPIO_OUT = GPIO_MODE(0, 1, 0), /**< OUT (push-pull) */
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GPIO_OD = GPIO_MODE(1, 1, 0), /**< OD */
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GPIO_OD_PU = GPIO_MODE(1, 1, 2), /**< OD with pull-up */
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} gpio_mode_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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#ifndef DOXYGEN
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/**
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* @name GPIO flank configuration values
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* @{
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*/
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_LOW = 0, /**< emit interrupt when the value is low */
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GPIO_HIGH = 1, /**< emit interrupt when the value is high */
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GPIO_RISING = 2, /**< emit interrupt on rising flank */
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GPIO_FALLING = 3, /**< emit interrupt on falling flank */
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} gpio_flank_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Available ports on the QN908x.
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*/
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enum {
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PORT_A = 0, /**< port A */
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PORT_B = 1, /**< port B */
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GPIO_PORTS_NUMOF /**< overall number of available ports */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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