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46 lines
732 B
C
46 lines
732 B
C
/*
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* SPDX-FileCopyrightText: 2020 Inria
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief STM32L5 CPU specific definitions for internal peripheral handling
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN
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/**
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* @brief Starting address of the ROM bootloader
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* see application note AN2606
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*/
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#define STM32_BOOTLOADER_ADDR (0x0BF90000)
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/**
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* @name Constants for internal VBAT ADC line
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* @{
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*/
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#define VBAT_ADC_RES ADC_RES_12BIT
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#define VBAT_ADC_MAX 4095
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/** @} */
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#endif /* ndef DOXYGEN */
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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