mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-12-26 23:11:19 +01:00
53235dd2e2
The current ATxmega clock_init enable DFLL to improve the accuracy of the 2MHz and 32MHz internal oscillators. In some ATxmega revisions, after started DFLL the clock become unstable. Add another sync point for 32MHz internal oscilator. Note: If clock is not stable, system won't switch from 2MHz to 32MHz as main clock. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>