mirror of
https://github.com/RIOT-OS/RIOT.git
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76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
/*
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* Copyright (C) 2018 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#pragma once
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/**
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* @ingroup cpu_esp32
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* @{
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*
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* @file
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* @brief Implementation of the kernels irq interface
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*
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* @}
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*/
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#include "irq_arch_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name CPU interrupt numbers
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*
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* All interrupts that are used for RIOT-OS are preallocated and fix.
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* The allocated interrupts are all level interrupts, most of them with
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* low priority.
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*
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* @{
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*/
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/* On Xtensa-based ESP32x SoCs, interrupt 0 is reserved for the WiFi interface
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* and interrupt 1 is available. However, since interrupt 0 is not available on
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* RISC-V-based ESP32x SoCs, interrupt 1 is used for the WiFi interface instead.
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* Therefore, we use interrupt 1 for the RMT peripheral on Xtensa-based ESP32x
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* SoCs, but we use interrupt 11 for the RMT peripheral on RISC-V-based ESP32x
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* SoCs. Interrupt 11 is reserved for profiling on Xtensa-based ESP32x SoCs. */
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#if defined(__XTENSA__)
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# define CPU_INUM_RMT 1 /**< Level interrupt with low priority 1 */
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#else
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# define CPU_INUM_RMT 11 /**< Level interrupt with low priority 1 */
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#endif
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#define CPU_INUM_GPIO 2 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_BLE 5 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_RTT 9 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_SERIAL_JTAG 10 /**< Edge interrupt with low priority 1 */
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#define CPU_INUM_I2C 12 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_UART 13 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_CAN 17 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_ETH 18 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_USB 18 /**< Level interrupt with low priority 1 */
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#define CPU_INUM_LCDCAM 19 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_FRC2 20 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_SDMMC 21 /**< Level interrupt with medium priority 2 */
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#define CPU_INUM_TIMER 22 /**< Edge interrupt with medium priority 2 */
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#define CPU_INUM_WDT 23 /**< Level interrupt with medium priority 3 */
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#define CPU_INUM_SOFTWARE 29 /**< Software interrupt with medium priority 3 */
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/** @} */
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/**
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* @brief Initialize architecture specific interrupt handling
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*/
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void esp_irq_init(void);
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#ifdef __cplusplus
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}
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#endif
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