mirror of
https://github.com/RIOT-OS/RIOT.git
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208 lines
6.9 KiB
C
208 lines
6.9 KiB
C
/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#pragma once
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/**
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* @ingroup cpu_esp32
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* @{
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*
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* @file
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* @brief SDK configuration used by the ESP-IDF for ESP32 SoC variant (family)
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*
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* The SDK configuration can be partially overridden by application-specific
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* board configuration.
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef DOXYGEN
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name ESP32 specific clock configuration
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* @{
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*/
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/* Mapping of Kconfig defines to the respective enumeration values */
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#if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_2
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 2
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_5
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 5
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_10
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 10
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_20
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 20
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_40
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 40
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_80
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_160
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_240
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
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#endif
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/**
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* @brief Defines the CPU frequency [values = 2, 5, 10, 20, 40, 80, 160, 240]
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*/
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#ifndef CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
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# define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 80
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#endif
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/** @} */
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/**
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* ESP32 specific RTC clock configuration
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*/
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#define CONFIG_RTC_CLK_CAL_CYCLES 1024
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#ifdef MODULE_ESP_RTC_TIMER_32K
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# define CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_NONE 1
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# define CONFIG_RTC_XTAL_CAL_RETRY 1
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# define CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES 5
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#endif
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/**
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* ESP32 specific EFUSE configuration
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*/
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#define CONFIG_EFUSE_MAX_BLK_LEN 192
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#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
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#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
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#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 99
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/**
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* ESP32 specific MAC configuration
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*/
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
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#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
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#define CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES 4
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/**
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* ESP32 specific system configuration (DO NOT CHANGE)
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*/
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#define CONFIG_ESP32_REV_MIN 0
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#define CONFIG_ESP32_TRACEMEM_RESERVE_DRAM 0x0
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#define CONFIG_ESP_BROWNOUT_DET 1
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#define CONFIG_ESP_BROWNOUT_DET_LVL 0
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#define CONFIG_ESP_CONSOLE_MULTIPLE_UART 1
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#define CONFIG_ESP_DEBUG_OCDAWARE 1
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#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
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#define CONFIG_ULP_COPROC_RESERVE_MEM 0
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/**
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* ESP32 specific sleep configuration (DO NOT CHANGE)
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*/
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#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
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#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
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/**
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* ESP32 specific ADC calibration
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*/
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#define CONFIG_ADC_CALI_EFUSE_TP_ENABLE 1
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#define CONFIG_ADC_CALI_EFUSE_VREF_ENABLE 1
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#define CONFIG_ADC_CALI_LUT_ENABLE 1
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/**
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* ESP32 specific PHY configuration
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*/
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#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1
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/**
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* ESP32 specific XTAL configuration
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*
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* Main clock crystal frequency (MHz). Zero means to auto-configure.
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* This is configured at the board level, defaulting to 40.
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*/
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#ifndef CONFIG_XTAL_FREQ
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# define CONFIG_XTAL_FREQ 0
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#endif
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/**
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* ESP32 specific SPI RAM configuration
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*/
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#ifdef MODULE_ESP_SPI_RAM
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# define CONFIG_D0WD_PSRAM_CLK_IO 17
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# define CONFIG_D0WD_PSRAM_CS_IO 16
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# define CONFIG_D2WD_PSRAM_CLK_IO 9
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# define CONFIG_D2WD_PSRAM_CS_IO 10
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# define CONFIG_PICO_PSRAM_CS_IO 10
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# define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
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# define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
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# define CONFIG_SPIRAM_CACHE_WORKAROUND 1
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# define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
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# define CONFIG_SPIRAM_MODE_QUAD 1
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# define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
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#endif
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/**
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* ESP32 specific ETH configuration
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*/
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#ifdef MODULE_ESP_ETH
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# define CONFIG_ETH_USE_ESP32_EMAC 1
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# define CONFIG_ETH_PHY_INTERFACE_RMII 1
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# define CONFIG_ETH_RMII_CLK_INPUT 1
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# define CONFIG_ETH_RMII_CLK_IN_GPIO 0
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# define CONFIG_ETH_DMA_BUFFER_SIZE 512
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# define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
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# define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
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#endif
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/**
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* ESP32 specific BLE driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_BLE
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# define CONFIG_BT_ALARM_MAX_NUM 50
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# define CONFIG_BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
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# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_NUM 100
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# define CONFIG_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP 1
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# define CONFIG_BTDM_BLE_CHAN_ASS_EN 1
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# define CONFIG_BTDM_BLE_DEFAULT_SCA_250PPM 1
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# define CONFIG_BTDM_BLE_PING_EN 1
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# define CONFIG_BTDM_BLE_SCAN_DUPL 1
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# define CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF 1
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# define CONFIG_BTDM_CTRL_BLE_MAX_CONN 3
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# define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 3
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# define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0
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# define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0
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# define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
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# define CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED 1
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# define CONFIG_BTDM_CTRL_HCI_MODE_VHCI 1
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# define CONFIG_BTDM_CTRL_HLI 0 /* ESP-IDF uses 1 by default */
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# define CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL 1
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# define CONFIG_BTDM_CTRL_MODE_BLE_ONLY 1
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# define CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG 1
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# define CONFIG_BTDM_CTRL_MODEM_SLEEP 1
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# define CONFIG_BTDM_CTRL_PCM_FSYNCSHP_EFF 1
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# define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0
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# define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0
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# define CONFIG_BTDM_CTRL_PINNED_TO_CORE 0
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# define CONFIG_BTDM_CTRL_PINNED_TO_CORE_0 1
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# define CONFIG_BTDM_RESERVE_DRAM 0xe000 /* at least 0xdb5c, we use 56 kB */
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# define CONFIG_BTDM_SCAN_DUPL_CACHE_REFRESH_PERIOD 0
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# define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE 200
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# define CONFIG_BTDM_SCAN_DUPL_TYPE 0
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# define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE 1
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#else
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# define CONFIG_BTDM_RESERVE_DRAM 0
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* DOXYGEN */
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/** @} */
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