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425 lines
16 KiB
C
425 lines
16 KiB
C
/*
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* Copyright (C) 2024 COGIP Robotics association
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#pragma once
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_can
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* @defgroup fdcandev_stm32 STM32 FDCAN controller
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* @brief STM32 FDCAN controller driver
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*
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* The STM32Gx microcontroller can have an integrated FDCAN controller
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*
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* This driver has been tested with a STM32G4 MCU
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* but should work on others.
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*
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* The default bitrates are set to 1 Mbps for headers and 4 Mbps for data.
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* The default sample point is set to 87.5%.
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* @{
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*
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* @file
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* @brief FDCAN specific definitions
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*
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* @author Gilles DOFFE <g.doffe@gmail.com>
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* @}
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "can/candev.h"
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/** Number of channels in the device (up to 3) */
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#if defined(FDCAN3)
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#define FDCANDEV_STM32_CHAN_NUMOF 3
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#elif defined(FDCAN2)
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#define FDCANDEV_STM32_CHAN_NUMOF 2
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#elif defined(FDCAN1) || DOXYGEN
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#define FDCANDEV_STM32_CHAN_NUMOF 1
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#else
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#error "FDCAN STM32: CPU not supported"
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#endif
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/**
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* @name ISR functions
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* @{
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*/
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#define ISR_FDCAN1_IT0 isr_fdcan1_it0 /**< Interrupt line 0 */
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#define ISR_FDCAN1_IT1 isr_fdcan1_it1 /**< Interrupt line 1 */
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/** @} */
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/**
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* @name Filters
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* @{
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*/
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#define FDCAN_STM32_NB_STD_FILTER 28U /**< Number of standard filters */
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#define FDCAN_STM32_NB_EXT_FILTER 8U /**< Number of extended filters */
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#define FDCAN_STM32_NB_FILTER \
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(FDCAN_STM32_NB_STD_FILTER + FDCAN_STM32_NB_EXT_FILTER) /**< Total number of filters */
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/** @} */
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/**
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* @name Birates
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* @{
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*/
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#ifndef FDCANDEV_STM32_DEFAULT_BITRATE
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#define FDCANDEV_STM32_DEFAULT_BITRATE 500000U
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/**< Default bitrate for headers and non-FDCAN messages */
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#endif
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#ifndef FDCANDEV_STM32_DEFAULT_FD_DATA_BITRATE
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#define FDCANDEV_STM32_DEFAULT_FD_DATA_BITRATE 1000000U
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/**< Default FDCAN data bitrate */
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#endif
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/** @} */
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#ifndef FDCANDEV_STM32_DEFAULT_SPT
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/** Default sampling-point */
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#define FDCANDEV_STM32_DEFAULT_SPT 875
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#endif
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/** bxCAN device configuration */
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typedef struct {
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FDCAN_GlobalTypeDef *can; /**< CAN device */
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uint32_t rcc_mask; /**< RCC mask to enable clock */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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gpio_af_t af; /**< Alternate pin function to use */
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bool en_deep_sleep_wake_up; /**< Enable deep-sleep wake-up interrupt */
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uint8_t it0_irqn; /**< Interrupt line 0 IRQ channel */
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uint8_t it1_irqn; /**< Interrupt line 1 IRQ channel */
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uint8_t ttcm : 1; /**< Time triggered communication mode */
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uint8_t abom : 1; /**< Automatic bus-off management */
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uint8_t awum : 1; /**< Automatic wakeup mode */
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uint8_t nart : 1; /**< No automatic retransmission */
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uint8_t rflm : 1; /**< Receive FIFO locked mode */
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uint8_t txfp : 1; /**< Transmit FIFO priority */
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uint8_t lbkm : 1; /**< Loopback mode */
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uint8_t silm : 1; /**< Silent mode */
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} can_conf_t;
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/** can_conf_t is re-defined */
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#define HAVE_CAN_CONF_T
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/**
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* @name STM32 mailboxes
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* @{
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*/
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#define FDCAN_STM32_TX_MAILBOXES 3
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/**< Number of frame the driver can transmit simultaneously */
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#define FDCAN_STM32_RX_MAILBOXES (FDCANDEV_STM32_CHAN_NUMOF * 6)
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/**< Maximum number of frame the driver can receive simultaneously.
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There are 3 buffers per FIFO and 2 FIFO per channel. */
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/** @} */
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/** FDCAN candev descriptor */
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typedef struct can can_t;
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/** can_t is re-defined */
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#define HAVE_CAN_T
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#define FDCAN_SRAM_MESSAGE_RAM_SIZE 0x350 /**< FDCAN SRAM message size */
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/**
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* @name Message RAM addresses - 32 bits aligned
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* @{
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*/
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#define FDCAN_SRAM_FLESA 0x1CU /**< Filter List Extended Start Address */
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#define FDCAN_SRAM_F0SA 0x2CU /**< Rx FIFO0 Start Address */
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#define FDCAN_SRAM_F1SA 0x62U /**< Rx FIFO1 Start Address */
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#define FDCAN_SRAM_EFSA 0x98U /**< Event FIFO Start Address */
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#define FDCAN_SRAM_TBSA 0x9EU /**< Tx Buffer Start Address */
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/** @} */
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/**
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* @name Standard filter bit definition
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* @{
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*/
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#define FDCAN_SRAM_FLS_SFID1_Pos (16U)
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/**< Standard filter ID 1 position */
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#define FDCAN_SRAM_FLS_SFID1_Msk (0x7FFU << FDCAN_SRAM_FLS_SFID1_Pos)
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/**< Standard filter ID 1 mask */
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#define FDCAN_SRAM_FLS_SFID1 FDCAN_SRAM_FLS_SFID1_Msk
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/**< Standard filter ID 1 */
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#define FDCAN_SRAM_FLS_SFID2_Msk (0x7FFU)
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/**< Standard filter ID 2 mask */
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#define FDCAN_SRAM_FLS_SFID2 FDCAN_SRAM_FLS_SFID2_Msk
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/**< Standard filter ID 2 */
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#define FDCAN_SRAM_FLS_SFT_Pos (30U)
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/**< Standard filter type position */
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#define FDCAN_SRAM_FLS_SFT_Msk (0x3U << FDCAN_SRAM_FLS_SFT_Pos)
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/**< Standard filter type mask */
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#define FDCAN_SRAM_FLS_SFT FDCAN_SRAM_FLS_SFT_Msk
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/**< Standard filter type */
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#define FDCAN_SRAM_FLS_SFEC_Pos (27U)
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/**< Standard filter element configuration position */
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#define FDCAN_SRAM_FLS_SFEC_Msk (0x7U << FDCAN_SRAM_FLS_SFEC_Pos)
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/**< Standard filter element configuration mask */
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#define FDCAN_SRAM_FLS_SFEC FDCAN_SRAM_FLS_SFEC_Msk
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/**< Standard filter element configuration */
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/** @} */
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/**
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* @name Standard filter configuration
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* @{
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*/
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#define FDCAN_SRAM_FLS_FILTER_SIZE 1U
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/**< Standard filter size */
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#define FDCAN_SRAM_FLS_SFT_DISABLED (0x3U << FDCAN_SRAM_FLS_SFT_Pos)
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/**< Filter element disabled */
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#define FDCAN_SRAM_FLS_SFT_CLASSIC (0x2U << FDCAN_SRAM_FLS_SFT_Pos)
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/**< Classic filter */
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#define FDCAN_SRAM_FLS_SFEC_DISABLED (0x0U << FDCAN_SRAM_FLS_SFEC_Pos)
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/**< Filter element disabled */
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#define FDCAN_SRAM_FLS_SFEC_FIFO0 (0x1U << FDCAN_SRAM_FLS_SFEC_Pos)
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/**< Use FIFO0 if filter matches */
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#define FDCAN_SRAM_FLS_SFEC_FIFO1 (0x2U << FDCAN_SRAM_FLS_SFEC_Pos)
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/**< Use FIFO1 if filter matches*/
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/** @} */
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/**
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* @name Extended filter bit definition
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* @{
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*/
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#define FDCAN_SRAM_FLE_F0_EFID1_Msk 0x1FFFFFFFU
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/**< Extended filter ID 1 mask */
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#define FDCAN_SRAM_FLE_F0_EFID1 FDCAN_SRAM_FLE_F0_EFID1_Msk
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/**< Extended filter ID 1 */
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#define FDCAN_SRAM_FLE_F1_EFID2_Msk 0x1FFFFFFFU
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/**< Extended filter ID 2 mask */
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#define FDCAN_SRAM_FLE_F1_EFID2 FDCAN_SRAM_FLE_F1_EFID2_Msk
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/**< Extended filter ID 2 */
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#define FDCAN_SRAM_FLE_F1_EFT_Pos 30U
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/**< Extended filter type position */
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#define FDCAN_SRAM_FLE_F1_EFT_Msk (0x3U << FDCAN_SRAM_FLE_F1_EFT_Pos)
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/**< Extended filter type mask */
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#define FDCAN_SRAM_FLE_F1_EFT FDCAN_SRAM_FLE_F1_EFT_Msk
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/**< Extended filter type */
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#define FDCAN_SRAM_FLE_F0_EFEC_Pos 29U
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/**< Extended filter element configuration position */
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#define FDCAN_SRAM_FLE_F0_EFEC_Msk (0x7U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
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/**< Extended filter element configuration mask */
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#define FDCAN_SRAM_FLE_F0_EFEC FDCAN_SRAM_FLE_F0_EFEC_Msk
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/**< Extended filter element configuration */
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/** @} */
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/**
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* @name Extended filter configuration
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* @{
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*/
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#define FDCAN_SRAM_FLE_FILTER_SIZE 2U
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/**< Extended filter size */
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#define FDCAN_SRAM_FLE_F1_EFT_CLASSIC (0x2U << FDCAN_SRAM_FLE_F1_EFT_Pos)
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/**< Classic filter */
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#define FDCAN_SRAM_FLE_F0_EFEC_DISABLED (0x0U)
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/**< Disabled filter */
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#define FDCAN_SRAM_FLE_F0_EFEC_FIFO0 (0x1U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
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/**< Use FIFO0 if filter matches */
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#define FDCAN_SRAM_FLE_F0_EFEC_FIFO1 (0x2U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
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/**< Use FIFI1 if filter matches */
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/** @} */
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/**
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* @name Tx Buffer bits definition
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* @{
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*/
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#define FDCAN_SRAM_TXBUFFER_T0_ESI_Pos 31U
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/**< Error State Indicator position */
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#define FDCAN_SRAM_TXBUFFER_T0_ESI_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
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/**< Error State Indicator mask */
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#define FDCAN_SRAM_TXBUFFER_T0_ESI FDCAN_SRAM_TXBUFFER_T0_ESI_Msk
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/**< Error State Indicator */
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#define FDCAN_SRAM_TXBUFFER_T0_XTD_Pos 30U
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/**< Extended Identifier position */
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#define FDCAN_SRAM_TXBUFFER_T0_XTD_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T0_XTD_Pos)
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/**< Extended Identifier mask */
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#define FDCAN_SRAM_TXBUFFER_T0_XTD FDCAN_SRAM_TXBUFFER_T0_XTD_Msk
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/**< Extended Identifier */
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#define FDCAN_SRAM_TXBUFFER_T0_RTR_Pos 29U
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/**< Remote transmission request position*/
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#define FDCAN_SRAM_TXBUFFER_T0_RTR_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T0_RTR_Pos)
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/**< Remote transmission request mask */
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#define FDCAN_SRAM_TXBUFFER_T0_RTR FDCAN_SRAM_TXBUFFER_T0_RTR_Msk
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/**< Remote transmission request */
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#define FDCAN_SRAM_TXBUFFER_T0_ID_Pos 18U
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/**< Standard Identifier position */
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#define FDCAN_SRAM_TXBUFFER_T1_EFC_Pos 23U
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/**< Event FIFO Control position */
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#define FDCAN_SRAM_TXBUFFER_T1_EFC_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
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/**< Event FIFO Control mask */
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#define FDCAN_SRAM_TXBUFFER_T1_EFC FDCAN_SRAM_TXBUFFER_T1_EFC_Msk
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/**< Event FIFO Control */
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#define FDCAN_SRAM_TXBUFFER_T1_FDF_Pos 21U
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/**< FD Format position */
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#define FDCAN_SRAM_TXBUFFER_T1_FDF_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
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/**< FD Format mask */
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#define FDCAN_SRAM_TXBUFFER_T1_FDF FDCAN_SRAM_TXBUFFER_T1_FDF_Msk
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/**< FD Format */
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#define FDCAN_SRAM_TXBUFFER_T1_BRS_Pos 20U
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/**< Bit Rate Switching position */
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#define FDCAN_SRAM_TXBUFFER_T1_BRS_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
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/**< Bit Rate Switching mask */
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#define FDCAN_SRAM_TXBUFFER_T1_BRS FDCAN_SRAM_TXBUFFER_T1_BRS_Msk
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/**< Bit Rate Switching */
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#define FDCAN_SRAM_TXBUFFER_T1_DLC_Pos 16U
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/**< Data Length Code position */
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#define FDCAN_SRAM_TXBUFFER_T1_DLC_Msk (0xFU << FDCAN_SRAM_TXBUFFER_T1_DLC_Pos)
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/**< Data Length Code mask */
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#define FDCAN_SRAM_TXBUFFER_T1_DLC FDCAN_SRAM_TXBUFFER_T1_DLC_Msk
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/**< Data Length Code */
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/** @} */
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/**
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* @name Tx buffers configuration
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* @{
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*/
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#define FDCAN_SRAM_TXBUFFER_SIZE 18U
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/**< Tx buffer size */
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#define FDCAN_SRAM_TXBUFFER_T0_ESI_PASSIVE_FLAG (0x0U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
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/**< ESI bit in CAN FD format depends only on error passive flag */
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#define FDCAN_SRAM_TXBUFFER_T0_ESI_RECESSIVE (0x1U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
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/**< ESI bit in CAN FD format transmitted recessive */
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#define FDCAN_SRAM_TXBUFFER_T1_EFC_DISABLE (0x0U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
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/**< Do not store Tx events */
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#define FDCAN_SRAM_TXBUFFER_T1_EFC_STORE_EVENTS (0x1U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
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/**< Store Tx events */
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#define FDCAN_SRAM_TXBUFFER_T1_FDF_CLASSIC (0x0U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
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/**< Classic CAN format */
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#define FDCAN_SRAM_TXBUFFER_T1_FDF_FD (0x1U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
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/**< CAN FD format */
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#define FDCAN_SRAM_TXBUFFER_T1_BRS_OFF (0x0U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
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/**< Disable CAN FD bit rate switching */
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#define FDCAN_SRAM_TXBUFFER_T1_BRS_ON (0x1U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
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/**< Enable CAN FD bit rate switching */
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/** @} */
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/**
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* @name Rx Buffer bits definition
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* @{
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*/
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#define FDCAN_SRAM_RXFIFO_R0_ESI_Pos 31U
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/**< Error State Indicator position */
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#define FDCAN_SRAM_RXFIFO_R0_ESI_Msk (0x1U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
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/**< Error State Indicator mask */
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#define FDCAN_SRAM_RXFIFO_R0_ESI FDCAN_SRAM_RXFIFO_R0_ESI_Msk
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/**< Error State Indicator */
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#define FDCAN_SRAM_RXFIFO_R0_XTD_Pos 30U
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/**< Extended Identifier position */
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#define FDCAN_SRAM_RXFIFO_R0_XTD_Msk (0x1U << FDCAN_SRAM_RXFIFO_R0_XTD_Pos)
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/**< Extended Identifier mask */
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#define FDCAN_SRAM_RXFIFO_R0_XTD FDCAN_SRAM_RXFIFO_R0_XTD_Msk
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/**< Extended Identifier */
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#define FDCAN_SRAM_RXFIFO_R0_RTR_Pos 29U
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/**< Remote transmission request position*/
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#define FDCAN_SRAM_RXFIFO_R0_RTR_Msk (0x1U << FDCAN_SRAM_RXFIFO_R0_RTR_Pos)
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/**< Remote transmission request mask */
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#define FDCAN_SRAM_RXFIFO_R0_RTR FDCAN_SRAM_RXFIFO_R0_RTR_Msk
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/**< Remote transmission request */
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#define FDCAN_SRAM_RXFIFO_R0_ID_Pos 18U
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/**< Standard Identifier position */
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#define FDCAN_SRAM_RXFIFO_R0_ID_Msk 0x1FFFFFFFU
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/**< Identifier mask */
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#define FDCAN_SRAM_RXFIFO_R0_ID FDCAN_SRAM_RXFIFO_R0_ID_Msk
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/**< Identifier */
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#define FDCAN_SRAM_RXFIFO_R1_EFC_Pos 23U
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/**< Event FIFO Control position */
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#define FDCAN_SRAM_RXFIFO_R1_EFC_Msk (0x1U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
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/**< Event FIFO Control mask */
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#define FDCAN_SRAM_RXFIFO_R1_EFC FDCAN_SRAM_RXFIFO_R1_EFC_Msk
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/**< Event FIFO Control */
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#define FDCAN_SRAM_RXFIFO_R1_FDF_Pos 21U
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/**< FD Format position */
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#define FDCAN_SRAM_RXFIFO_R1_FDF_Msk (0x1U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
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/**< FD Format mask */
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#define FDCAN_SRAM_RXFIFO_R1_FDF FDCAN_SRAM_RXFIFO_R1_FDF_Msk
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/**< FD Format */
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#define FDCAN_SRAM_RXFIFO_R1_BRS_Pos 20U
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/**< Bit Rate Switching position */
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#define FDCAN_SRAM_RXFIFO_R1_BRS_Msk (0x1U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
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/**< Bit Rate Switching mask */
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#define FDCAN_SRAM_RXFIFO_R1_BRS FDCAN_SRAM_RXFIFO_R1_BRS_Msk
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/**< Bit Rate Switching */
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#define FDCAN_SRAM_RXFIFO_R1_DLC_Pos 16U
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/**< Data Length Code position */
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#define FDCAN_SRAM_RXFIFO_R1_DLC_Msk (0xFU << FDCAN_SRAM_RXFIFO_R1_DLC_Pos)
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/**< Data Length Code mask */
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#define FDCAN_SRAM_RXFIFO_R1_DLC FDCAN_SRAM_RXFIFO_R1_DLC_Msk
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/**< Data Length Code */
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/** @} */
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/**
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* @name Rx buffers configuration
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* @{
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*/
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#define FDCAN_SRAM_RXFIFO_SIZE 54U
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/**< Rx FIFO size */
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#define FDCAN_SRAM_RXFIFO_ELEMENT_SIZE 18U
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/**< Rx FIFO element size */
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#define FDCAN_SRAM_RXFIFO_R0_ESI_PASSIVE_FLAG (0x0U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
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/**< ESI bit in CAN FD format depends only on error passive flag */
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#define FDCAN_SRAM_RXFIFO_R0_ESI_RECESSIVE (0x1U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
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/**< ESI bit in CAN FD format transmitted recessive */
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#define FDCAN_SRAM_RXFIFO_R1_EFC_DISABLE (0x0U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
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/**< Do not store Rx events */
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#define FDCAN_SRAM_RXFIFO_R1_EFC_STORE_EVENTS (0x1U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
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/**< Store Rx events */
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#define FDCAN_SRAM_RXFIFO_R1_FDF_CLASSIC (0x0U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
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/**< Classic CAN format */
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#define FDCAN_SRAM_RXFIFO_R1_FDF_FD (0x1U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
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/**< CAN FD format */
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#define FDCAN_SRAM_RXFIFO_R1_BRS_OFF (0x0U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
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/**< CAN FD bit rate switching enabled */
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#define FDCAN_SRAM_RXFIFO_R1_BRS_ON (0x1U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
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/**< CAN FD bit rate switching disabled */
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/** @} */
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/** This structure holds anything related to the receive part */
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typedef struct candev_stm32_rx_mailbox {
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can_frame_t frame[FDCAN_STM32_RX_MAILBOXES];
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/**< Receive FIFO */
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int write_idx;
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/**< Write index in the receive FIFO */
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int read_idx;
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/**< Read index in the receive FIFO*/
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int is_full;
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/**< Flag set when the FIFO is full */
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} candev_stm32_rx_mailbox_t;
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|
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/** Internal interrupt flags */
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typedef struct candev_stm32_isr {
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int isr_tx : 3; /**< Tx mailboxes interrupt */
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int isr_rx : 2; /**< Rx FIFO interrupt */
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int isr_wkup : 1; /**< Wake up interrupt */
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} candev_stm32_isr_t;
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|
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/** STM32 CAN device descriptor */
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struct can {
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candev_t candev; /**< Common candev struct */
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const can_conf_t *conf; /**< Configuration */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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gpio_af_t af; /**< Alternate pin function to use */
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const can_frame_t
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*tx_mailbox[FDCAN_STM32_TX_MAILBOXES]; /**< Tx mailboxes*/
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candev_stm32_rx_mailbox_t rx_mailbox; /**< Rx mailboxes */
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candev_stm32_isr_t isr_flags; /**< ISR flags */
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};
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|
|
|
/**
|
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* @brief Set the pins of an stm32 CAN device
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|
*
|
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* @param[in,out] dev the device to set pins
|
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* @param[in] tx_pin tx pin
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* @param[in] rx_pin rx pin
|
|
* @param[in] af alternate function
|
|
*/
|
|
void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin,
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|
gpio_af_t af);
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|
#ifdef __cplusplus
|
|
}
|
|
#endif
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