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https://github.com/RIOT-OS/RIOT.git
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eb3f515f55
saml1x and samd5x have dedicated interrupts per GPIO line. Use those instead of iterating over the GPIO status bits to serve IRQs even faster.
389 lines
8.7 KiB
C
389 lines
8.7 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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* 2015 Kaspar Schleiser <kaspar@schleiser.de>
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* 2015 FreshTemp, LLC.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file gpio.c
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* @brief Low-level GPIO driver implementation
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*
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* @author Troels Hoffmeyer <troels.d.hoffmeyer@gmail.com>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "periph/gpio.h"
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#include "periph_conf.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/**
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* @brief Mask to get PINCFG reg value from mode value
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*/
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#define MODE_PINCFG_MASK (0x06)
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#ifdef MODULE_PERIPH_GPIO_IRQ
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/**
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* @brief Number of external interrupt lines
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*/
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#ifdef CPU_SAML1X
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#define NUMOF_IRQS (8U)
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#else
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#define NUMOF_IRQS (16U)
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#endif
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/**
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* @brief External Interrupts Controller selection macros
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*/
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#ifdef CPU_FAM_SAML11
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#define _EIC EIC_SEC
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#else
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#define _EIC EIC
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#endif
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/**
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* @brief Clock source for the External Interrupt Controller
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*/
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typedef enum {
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_EIC_CLOCK_FAST,
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_EIC_CLOCK_SLOW
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} gpio_eic_clock_t;
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static gpio_isr_ctx_t gpio_config[NUMOF_IRQS];
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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static inline PortGroup *_port(gpio_t pin)
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{
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return (PortGroup *)(pin & ~(0x1f));
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}
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static inline int _pin_pos(gpio_t pin)
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{
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return (pin & 0x1f);
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}
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static inline int _pin_mask(gpio_t pin)
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{
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return (1 << _pin_pos(pin));
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}
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void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
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{
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PortGroup* port = _port(pin);
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int pin_pos = _pin_pos(pin);
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port->PINCFG[pin_pos].reg |= PORT_PINCFG_PMUXEN;
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port->PMUX[pin_pos >> 1].reg &= ~(0xf << (4 * (pin_pos & 0x1)));
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port->PMUX[pin_pos >> 1].reg |= (mux << (4 * (pin_pos & 0x1)));
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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PortGroup* port = _port(pin);
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int pin_pos = _pin_pos(pin);
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int pin_mask = _pin_mask(pin);
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/* make sure pin mode is applicable */
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if (mode > 0x7) {
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return -1;
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}
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/* set pin direction */
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if (mode & 0x2) {
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port->DIRCLR.reg = pin_mask;
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}
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else {
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port->DIRSET.reg = pin_mask;
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}
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/* configure the pin cfg */
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port->PINCFG[pin_pos].reg = (mode & MODE_PINCFG_MASK);
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/* and set pull-up/pull-down if applicable */
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if (mode == GPIO_IN_PU) {
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port->OUTSET.reg = pin_mask;
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}
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else if (mode == GPIO_IN_PD) {
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port->OUTCLR.reg = pin_mask;
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}
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return 0;
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}
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int gpio_read(gpio_t pin)
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{
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PortGroup *port = _port(pin);
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int mask = _pin_mask(pin);
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if (port->DIR.reg & mask) {
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return (port->OUT.reg & mask) ? 1 : 0;
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}
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else {
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return (port->IN.reg & mask) ? 1 : 0;
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}
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}
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void gpio_set(gpio_t pin)
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{
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_port(pin)->OUTSET.reg = _pin_mask(pin);
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}
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void gpio_clear(gpio_t pin)
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{
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_port(pin)->OUTCLR.reg = _pin_mask(pin);
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}
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void gpio_toggle(gpio_t pin)
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{
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_port(pin)->OUTTGL.reg = _pin_mask(pin);
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}
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void gpio_write(gpio_t pin, int value)
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{
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if (value) {
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_port(pin)->OUTSET.reg = _pin_mask(pin);
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} else {
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_port(pin)->OUTCLR.reg = _pin_mask(pin);
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}
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}
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#ifdef MODULE_PERIPH_GPIO_IRQ
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#ifdef CPU_FAM_SAMD21
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#define EIC_SYNC() while (_EIC->STATUS.bit.SYNCBUSY)
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#else
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#define EIC_SYNC() while (_EIC->SYNCBUSY.bit.ENABLE)
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#endif
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static int _exti(gpio_t pin)
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{
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unsigned port_num = ((pin >> 7) & 0x03);
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if (port_num >= ARRAY_SIZE(exti_config)) {
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return -1;
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}
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return exti_config[port_num][_pin_pos(pin)];
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}
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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int exti = _exti(pin);
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/* make sure EIC channel is valid */
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if (exti == -1) {
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return -1;
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}
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/* save callback */
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gpio_config[exti].cb = cb;
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gpio_config[exti].arg = arg;
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/* configure pin as input and set MUX to peripheral function A */
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gpio_init(pin, mode);
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gpio_init_mux(pin, GPIO_MUX_A);
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#ifdef CPU_FAM_SAMD21
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/* enable clocks for the EIC module */
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PM->APBAMASK.reg |= PM_APBAMASK_EIC;
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/* SAMD21 used GCLK2 which is supplied by either the ultra low power
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internal or external 32 kHz */
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GCLK->CLKCTRL.reg = EIC_GCLK_ID
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| GCLK_CLKCTRL_CLKEN
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| GCLK_CLKCTRL_GEN(SAM0_GCLK_32KHZ);
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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#else /* CPU_FAM_SAML21 */
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/* enable clocks for the EIC module */
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
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GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(SAM0_GCLK_MAIN);
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/* disable the EIC module*/
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_EIC->CTRLA.reg = 0;
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EIC_SYNC();
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#endif
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/* configure the active flank */
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_EIC->CONFIG[exti >> 3].reg &= ~(0xf << ((exti & 0x7) * 4));
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_EIC->CONFIG[exti >> 3].reg |= (flank << ((exti & 0x7) * 4));
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/* enable the global EIC interrupt */
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#ifdef CPU_SAML1X
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/* EXTI[4..7] are binded to EIC_OTHER_IRQn */
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NVIC_EnableIRQ((exti > 3 )? EIC_OTHER_IRQn : (EIC_0_IRQn + exti));
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#elif defined(CPU_SAMD5X)
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NVIC_EnableIRQ(EIC_0_IRQn + exti);
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#else
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NVIC_EnableIRQ(EIC_IRQn);
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#endif
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/* clear interrupt flag and enable the interrupt line and line wakeup */
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_EIC->INTFLAG.reg = (1 << exti);
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_EIC->INTENSET.reg = (1 << exti);
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#ifdef CPU_FAM_SAMD21
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_EIC->WAKEUP.reg |= (1 << exti);
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/* enable the EIC module*/
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_EIC->CTRL.reg = EIC_CTRL_ENABLE;
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EIC_SYNC();
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#else /* CPU_FAM_SAML21 */
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/* enable the EIC module*/
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_EIC->CTRLA.reg = EIC_CTRLA_ENABLE;
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EIC_SYNC();
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#endif
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return 0;
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}
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inline static void reenable_eic(gpio_eic_clock_t clock) {
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#if defined(CPU_SAMD21)
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if (clock == _EIC_CLOCK_SLOW) {
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GCLK->CLKCTRL.reg = EIC_GCLK_ID
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| GCLK_CLKCTRL_CLKEN
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| GCLK_CLKCTRL_GEN(SAM0_GCLK_32KHZ);
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} else {
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GCLK->CLKCTRL.reg = EIC_GCLK_ID
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| GCLK_CLKCTRL_CLKEN
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| GCLK_CLKCTRL_GEN(SAM0_GCLK_MAIN);
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}
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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#else
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uint32_t ctrla_reg = EIC_CTRLA_ENABLE;
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EIC->CTRLA.reg = 0;
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EIC_SYNC();
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if (clock == _EIC_CLOCK_SLOW) {
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ctrla_reg |= EIC_CTRLA_CKSEL;
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}
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EIC->CTRLA.reg = ctrla_reg;
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EIC_SYNC();
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#endif
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}
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void gpio_pm_cb_enter(int deep)
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{
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#if defined(PM_SLEEPCFG_SLEEPMODE_STANDBY)
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(void) deep;
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if (PM->SLEEPCFG.bit.SLEEPMODE == PM_SLEEPCFG_SLEEPMODE_STANDBY) {
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DEBUG_PUTS("gpio: switching EIC to slow clock");
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reenable_eic(_EIC_CLOCK_SLOW);
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}
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#else
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if (deep) {
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DEBUG_PUTS("gpio: switching EIC to slow clock");
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reenable_eic(_EIC_CLOCK_SLOW);
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}
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#endif
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}
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void gpio_pm_cb_leave(int deep)
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{
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#if defined(PM_SLEEPCFG_SLEEPMODE_STANDBY)
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(void) deep;
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if (PM->SLEEPCFG.bit.SLEEPMODE == PM_SLEEPCFG_SLEEPMODE_STANDBY) {
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DEBUG_PUTS("gpio: switching EIC to fast clock");
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reenable_eic(_EIC_CLOCK_FAST);
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}
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#else
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if (deep) {
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DEBUG_PUTS("gpio: switching EIC to fast clock");
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reenable_eic(_EIC_CLOCK_FAST);
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}
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#endif
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}
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void gpio_irq_enable(gpio_t pin)
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{
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int exti = _exti(pin);
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if (exti == -1) {
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return;
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}
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_EIC->INTENSET.reg = (1 << exti);
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}
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void gpio_irq_disable(gpio_t pin)
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{
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int exti = _exti(pin);
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if (exti == -1) {
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return;
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}
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_EIC->INTENCLR.reg = (1 << exti);
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}
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#if defined(CPU_SAML1X)
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void isr_eic_other(void)
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#else
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void isr_eic(void)
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#endif
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{
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/* read & clear interrupt flags */
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uint32_t state = _EIC->INTFLAG.reg;
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state &= (1 << NUMOF_IRQS) - 1;
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_EIC->INTFLAG.reg = state;
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/* execute interrupt callbacks */
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while (state) {
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unsigned pin = 8 * sizeof(state) - __builtin_clz(state) - 1;
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state &= ~(1 << pin);
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gpio_config[pin].cb(gpio_config[pin].arg);
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}
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cortexm_isr_end();
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}
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#if defined(CPU_SAML1X) || defined(CPU_SAMD5X)
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#define ISR_EICn(n) \
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void isr_eic ## n (void) \
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{ \
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_EIC->INTFLAG.reg = 1 << n; \
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gpio_config[n].cb(gpio_config[n].arg); \
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cortexm_isr_end(); \
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}
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ISR_EICn(0)
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ISR_EICn(1)
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ISR_EICn(2)
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ISR_EICn(3)
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#if defined(CPU_SAMD5X)
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ISR_EICn(4)
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ISR_EICn(5)
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ISR_EICn(6)
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ISR_EICn(7)
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#if (NUMOF_IRQS > 8)
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ISR_EICn(8)
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ISR_EICn(9)
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ISR_EICn(10)
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ISR_EICn(11)
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ISR_EICn(12)
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ISR_EICn(13)
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ISR_EICn(14)
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ISR_EICn(15)
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#endif /* NUMOF_IRQS > 8 */
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#endif /* CPU_SAMD5X */
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#endif /* CPU_SAML1X || CPU_SAMD5X */
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#else /* MODULE_PERIPH_GPIO_IRQ */
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void gpio_pm_cb_enter(int deep)
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{
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(void) deep;
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}
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void gpio_pm_cb_leave(int deep)
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{
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(void) deep;
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}
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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