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f6139ae346
When a previously disabled DFLL gets enabled again, the frequency will be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3 to work around the issue. This fixes wake from standby.
241 lines
6.9 KiB
C
241 lines
6.9 KiB
C
/*
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* Copyright (C) 2019 ML!PA Consulting GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_samd5x
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the CPU initialization for Microchip SAMD5x/SAME5x MCUs
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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* @}
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*/
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#include "cpu.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#include "stdio_base.h"
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#if CLOCK_CORECLOCK == 0
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#error Please select CLOCK_CORECLOCK
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#endif
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/* use DFLL for low frequency operation */
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#if CLOCK_CORECLOCK > SAM0_DFLL_FREQ_HZ
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#define USE_DPLL 1
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#else
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#define USE_DPLL 0
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#if (SAM0_DFLL_FREQ_HZ % CLOCK_CORECLOCK)
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#error For frequencies < 48 MHz, CLOCK_CORECLOCK must be a divider of 48 MHz
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#endif
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#endif
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/* If the CPU clock is lower than the minimal DPLL Freq
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set fDPLL = 2 * CLOCK_CORECLOCK */
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#if USE_DPLL && (CLOCK_CORECLOCK < SAM0_DPLL_FREQ_MIN_HZ)
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#define DPLL_DIV 2
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#else
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#define DPLL_DIV 1
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#endif
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static void xosc32k_init(void)
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{
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OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE
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| OSC32KCTRL_XOSC32K_EN1K
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| OSC32KCTRL_XOSC32K_EN32K
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| OSC32KCTRL_XOSC32K_RUNSTDBY
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| OSC32KCTRL_XOSC32K_XTALEN
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| OSC32KCTRL_XOSC32K_STARTUP(7);
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while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {}
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}
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static void dfll_init(void)
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{
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uint32_t reg = OSCCTRL_DFLLCTRLB_QLDIS
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#ifdef OSCCTRL_DFLLCTRLB_WAITLOCK
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| OSCCTRL_DFLLCTRLB_WAITLOCK
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#endif
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;
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/* workaround for Errata 2.8.3 DFLLVAL.FINE Value When DFLL48M Re-enabled */
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OSCCTRL->DFLLMUL.reg = 0; /* Write new DFLLMULL configuration */
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OSCCTRL->DFLLCTRLB.reg = 0; /* Select Open loop configuration */
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OSCCTRL->DFLLCTRLA.bit.ENABLE = 1; /* Enable DFLL */
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OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg; /* Reload DFLLVAL register */
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OSCCTRL->DFLLCTRLB.reg = reg; /* Write final DFLL configuration */
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OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_ENABLE;
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while (!OSCCTRL->STATUS.bit.DFLLRDY) {}
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}
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#if USE_DPLL
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static void fdpll0_init(uint32_t f_cpu)
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{
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/* We source the DPLL from 32kHz GCLK1 */
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const uint32_t LDR = ((f_cpu << 5) / 32768);
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/* disable the DPLL before changing the configuration */
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OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 0;
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while (OSCCTRL->Dpll[0].DPLLSYNCBUSY.reg) {}
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/* set DPLL clock source */
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = GCLK_PCHCTRL_GEN(1) | GCLK_PCHCTRL_CHEN;
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while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg & GCLK_PCHCTRL_CHEN)) {}
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OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR & 0x1F)
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| OSCCTRL_DPLLRATIO_LDR((LDR >> 5) - 1);
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/* Without LBYPASS, startup takes very long, see errata section 2.13. */
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK
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| OSCCTRL_DPLLCTRLB_WUF
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| OSCCTRL_DPLLCTRLB_LBYPASS;
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
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while (OSCCTRL->Dpll[0].DPLLSYNCBUSY.reg) {}
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while (!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY &&
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OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK)) {}
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}
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#endif
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static void gclk_connect(uint8_t id, uint8_t src, uint32_t flags) {
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GCLK->GENCTRL[id].reg = GCLK_GENCTRL_SRC(src) | GCLK_GENCTRL_GENEN | flags | GCLK_GENCTRL_IDC;
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while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(id)) {}
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}
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void sam0_gclk_enable(uint8_t id)
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{
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/* clocks 0 & 1 are always running */
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switch (id) {
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case SAM0_GCLK_8MHZ:
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/* 8 MHz clock used by xtimer */
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#if USE_DPLL
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gclk_connect(SAM0_GCLK_8MHZ,
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GCLK_SOURCE_DPLL0,
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GCLK_GENCTRL_DIV(DPLL_DIV * CLOCK_CORECLOCK / 8000000));
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#else
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gclk_connect(SAM0_GCLK_8MHZ,
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GCLK_SOURCE_DFLL,
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GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / 8000000));
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#endif
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break;
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case SAM0_GCLK_48MHZ:
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gclk_connect(SAM0_GCLK_48MHZ, GCLK_SOURCE_DFLL, 0);
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break;
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}
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}
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uint32_t sam0_gclk_freq(uint8_t id)
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{
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switch (id) {
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case SAM0_GCLK_MAIN:
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return CLOCK_CORECLOCK;
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case SAM0_GCLK_32KHZ:
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return 32768;
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case SAM0_GCLK_8MHZ:
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return 8000000;
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case SAM0_GCLK_48MHZ:
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return SAM0_DFLL_FREQ_HZ;
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default:
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return 0;
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}
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}
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void cpu_pm_cb_enter(int deep)
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{
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(void) deep;
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/* will be called before entering sleep */
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}
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void cpu_pm_cb_leave(int deep)
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{
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/* will be called after wake-up */
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if (deep) {
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/* DFLL needs to be re-initialized to work around errata 2.8.3 */
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dfll_init();
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}
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}
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/**
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* @brief Initialize the CPU, set IRQ priorities, clocks
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*/
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void cpu_init(void)
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{
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/* Disable the RTC module to prevent synchronization issues during CPU init
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if the RTC was running from a previous boot (e.g wakeup from backup) */
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if (RTC->MODE2.CTRLA.bit.ENABLE) {
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while (RTC->MODE2.SYNCBUSY.reg) {}
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RTC->MODE2.CTRLA.bit.ENABLE = 0;
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while (RTC->MODE2.SYNCBUSY.reg) {}
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}
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/* initialize the Cortex-M core */
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cortexm_init();
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/* turn on only needed APB peripherals */
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MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK
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| MCLK_APBAMASK_OSCCTRL
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| MCLK_APBAMASK_OSC32KCTRL
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| MCLK_APBAMASK_GCLK
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| MCLK_APBAMASK_SUPC
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| MCLK_APBAMASK_PAC
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#ifdef MODULE_PERIPH_PM
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| MCLK_APBAMASK_PM
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#endif
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#ifdef MODULE_PERIPH_GPIO_IRQ
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| MCLK_APBAMASK_EIC
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#endif
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;
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MCLK->APBBMASK.reg = 0
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#ifdef MODULE_PERIPH_FLASHPAGE
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| MCLK_APBBMASK_NVMCTRL
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#endif
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#ifdef MODULE_PERIPH_GPIO
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| MCLK_APBBMASK_PORT
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#endif
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;
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MCLK->APBCMASK.reg = 0;
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MCLK->APBDMASK.reg = 0;
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/* enable the Cortex M Cache Controller */
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CMCC->CTRL.bit.CEN = 1;
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xosc32k_init();
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gclk_connect(SAM0_GCLK_32KHZ, GCLK_SOURCE_XOSC32K, 0);
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/* make sure main clock is not sourced from DPLL */
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dfll_init();
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gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL, 0);
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#if USE_DPLL
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fdpll0_init(CLOCK_CORECLOCK * DPLL_DIV);
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/* source main clock from DPLL */
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gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DPLL0, GCLK_GENCTRL_DIV(DPLL_DIV));
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#else
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gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL, GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / CLOCK_CORECLOCK));
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#endif
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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stdio_init();
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/* trigger static peripheral initialization */
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periph_init();
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/* set ONDEMAND bit after all clocks have been configured */
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/* This is to avoid setting the source for the main clock to ONDEMAND before using it. */
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OSCCTRL->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND;
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OSCCTRL->Dpll[0].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
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}
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