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107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
/*
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* Copyright (C) 2025 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam4s
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* @{
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*
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* @file
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* @brief Startup code and interrupt vector definition
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* Cortex-M common interrupt vectors */
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WEAK_DEFAULT void isr_svc(void);
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WEAK_DEFAULT void isr_pendsv(void);
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WEAK_DEFAULT void isr_systick(void);
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/* SAM4S specific interrupt vector */
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WEAK_DEFAULT void isr_supc(void);
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WEAK_DEFAULT void isr_rstc(void);
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WEAK_DEFAULT void isr_rtc(void);
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WEAK_DEFAULT void isr_rtt(void);
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WEAK_DEFAULT void isr_wdt(void);
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WEAK_DEFAULT void isr_pmc(void);
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WEAK_DEFAULT void isr_eefc0(void);
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WEAK_DEFAULT void isr_eefc1(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_smc(void);
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WEAK_DEFAULT void isr_pioa(void);
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WEAK_DEFAULT void isr_piob(void);
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WEAK_DEFAULT void isr_pioc(void);
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WEAK_DEFAULT void isr_usart0(void);
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WEAK_DEFAULT void isr_usart1(void);
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WEAK_DEFAULT void isr_hsmci(void);
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WEAK_DEFAULT void isr_twi0(void);
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WEAK_DEFAULT void isr_twi1(void);
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WEAK_DEFAULT void isr_spi(void);
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WEAK_DEFAULT void isr_ssc(void);
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WEAK_DEFAULT void isr_tc0(void);
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WEAK_DEFAULT void isr_tc1(void);
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WEAK_DEFAULT void isr_tc2(void);
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WEAK_DEFAULT void isr_tc3(void);
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WEAK_DEFAULT void isr_tc4(void);
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WEAK_DEFAULT void isr_tc5(void);
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WEAK_DEFAULT void isr_adc(void);
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WEAK_DEFAULT void isr_dacc(void);
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WEAK_DEFAULT void isr_pwm(void);
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WEAK_DEFAULT void isr_crccu(void);
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WEAK_DEFAULT void isr_acc(void);
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WEAK_DEFAULT void isr_udp(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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isr_supc, /* 0 Supply Controller */
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isr_rstc, /* 1 Reset Controller */
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isr_rtc, /* 2 Real Time Clock */
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isr_rtt, /* 3 Real Timer Timer */
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isr_wdt, /* 4 Watchdog Timer */
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isr_pmc, /* 5 Power Management Controller */
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isr_eefc0, /* 6 Enhanced Embedded Flash Controller 0 */
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isr_eefc1, /* 7 Enhanced Embedded Flash Controller 1 */
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isr_uart0, /* 8 Universal Asynchronous Receiver Transceiver 0 */
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isr_uart1, /* 9 Universal Asynchronous Receiver Transceiver 1 */
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isr_smc, /* 10 Static Memory Controller */
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isr_pioa, /* 11 GPIO port A */
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isr_piob, /* 12 GPIO port B */
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isr_pioc, /* 13 GPIO port C */
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isr_usart0, /* 14 USART0 */
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isr_usart1, /* 15 USART1 */
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(0UL), /* Reserved */
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(0UL), /* Reserved */
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isr_hsmci, /* 18 Multimedia Card Interface */
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isr_twi0, /* 19 Two-wire Interface 0 */
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isr_twi1, /* 20 Two-wire Interface 1 */
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isr_spi, /* 21 Serial Peripheral Interface */
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isr_ssc, /* 22 Synchronous Serial Controller */
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isr_tc0, /* 23 Timer Counter 0 */
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isr_tc1, /* 24 Timer Counter 1 */
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isr_tc2, /* 25 Timer Counter 2 */
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isr_tc3, /* 26 Timer Counter 3 */
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isr_tc4, /* 27 Timer Counter 4 */
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isr_tc5, /* 28 Timer Counter 5 */
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isr_adc, /* 29 Analog/Digital Converter */
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isr_dacc, /* 30 Digital/Analog Converter Controller */
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isr_pwm, /* 31 Pulse Width Modulation */
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isr_crccu, /* 32 CRC Calculation Unit */
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isr_acc, /* 33 Analog Comparator Controller */
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isr_udp, /* 34 USB Device Port */
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};
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