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RIOT/cpu/stm32/include/fdcandev_stm32.h
Gilles DOFFE 5d48376a21 cpu/stm32: add FDCAN support to STM32G4 family 
Until now, STM32 MCUs classic CAN support is coded in can.c file.
However CAN FD in STM32G4 family is designed in a very different way:
* CAN FD channels are independant
* CAN FD channel configuration is done in a dedicated RAM block called
  message RAM, with one message RAM per channel
* Each message RAM is divided this way:
  - 11-bit filter (28 elements / 28 words)
  - 29-bit filter (8 elements / 16 words)
  - Rx FIFO 0 (3 elements / 54 words)
  - Rx FIFO 1 (3 elements / 54 words)
  - Tx event FIFO (3 elements / 6 words)
  - Tx buffers (3 elements / 54 words)

Due to these design differences with other STM32 MCUs, the choice is
made to split the driver in two files:
* classiccan.c for STM32 MCUs that support classical CAN. This file
  has just been renamed (previously can.c) to avoid build conflicts
  but does not introduce changes
* fdcan.c for STM32 MCUs that support CAN FD

Message RAM definitions is not provided in CMSIS headers of the STM32G4
family, they are defined in fdcandev_stm32.h. Those definitions could be
extracted to a new file for each STM32 families as some differences
exist with other STM32 families that support CAN FD (for instance
STM32H7). This could be done in a futher commit, according to new
families requirements.

CAN hardware parameters stay similar and are kept in can_params.h.

There are 36 filters per channel:
* 28 first filters are standard ID (11 bit) filters
* 8 last filters are extended ID (29 bit) filters

On each Tx frame sent, the STM32G4 can store Tx events in a dedicated
FIFO. This feature is not yet implemented and Tx event FIFO is disabled
by default.
Automatic retransmission on arbitration loss is enabled by default by
the STM32G4.

About Rx, if no filter is configured, all frames are accepted by
default.

Signed-off-by: Gilles DOFFE <gilles.doffe@rtone.fr>
2025-01-29 20:51:23 +01:00

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/*
* Copyright (C) 2024 COGIP Robotics association
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @ingroup drivers_can
* @defgroup fdcandev_stm32 STM32 FDCAN controller
* @brief STM32 FDCAN controller driver
*
* The STM32Gx microcontroller can have an integrated FDCAN controller
*
* This driver has been tested with a STM32G4 MCU
* but should work on others.
*
* The default bitrates are set to 1 Mbps for headers and 4 Mbps for data.
* The default sample point is set to 87.5%.
* @{
*
* @file
* @brief FDCAN specific definitions
*
* @author Gilles DOFFE <g.doffe@gmail.com>
* @}
*/
#ifndef FDCANDEV_STM32_H
#define FDCANDEV_STM32_H
#ifdef __cplusplus
extern "C" {
#endif
#include "can/candev.h"
/** Number of channels in the device (up to 3) */
#if defined(FDCAN3)
#define FDCANDEV_STM32_CHAN_NUMOF 3
#elif defined(FDCAN2)
#define FDCANDEV_STM32_CHAN_NUMOF 2
#elif defined(FDCAN1) || DOXYGEN
#define FDCANDEV_STM32_CHAN_NUMOF 1
#else
#error "FDCAN STM32: CPU not supported"
#endif
/**
* @name ISR functions
* @{
*/
#define ISR_FDCAN1_IT0 isr_fdcan1_it0 /**< Interrupt line 0 */
#define ISR_FDCAN1_IT1 isr_fdcan1_it1 /**< Interrupt line 1 */
/** @} */
/**
* @name Filters
* @{
*/
#define FDCAN_STM32_NB_STD_FILTER 28U /**< Number of standard filters */
#define FDCAN_STM32_NB_EXT_FILTER 8U /**< Number of extended filters */
#define FDCAN_STM32_NB_FILTER \
(FDCAN_STM32_NB_STD_FILTER + FDCAN_STM32_NB_EXT_FILTER) /**< Total number of filters */
/** @} */
/**
* @name Birates
* @{
*/
#ifndef FDCANDEV_STM32_DEFAULT_BITRATE
#define FDCANDEV_STM32_DEFAULT_BITRATE 500000U
/**< Default bitrate for headers and non-FDCAN messages */
#endif
#ifndef FDCANDEV_STM32_DEFAULT_FD_DATA_BITRATE
#define FDCANDEV_STM32_DEFAULT_FD_DATA_BITRATE 1000000U
/**< Default FDCAN data bitrate */
#endif
/** @} */
#ifndef FDCANDEV_STM32_DEFAULT_SPT
/** Default sampling-point */
#define FDCANDEV_STM32_DEFAULT_SPT 875
#endif
/** bxCAN device configuration */
typedef struct {
FDCAN_GlobalTypeDef *can; /**< CAN device */
uint32_t rcc_mask; /**< RCC mask to enable clock */
gpio_t rx_pin; /**< RX pin */
gpio_t tx_pin; /**< TX pin */
gpio_af_t af; /**< Alternate pin function to use */
bool en_deep_sleep_wake_up; /**< Enable deep-sleep wake-up interrupt */
uint8_t it0_irqn; /**< Interrupt line 0 IRQ channel */
uint8_t it1_irqn; /**< Interrupt line 1 IRQ channel */
uint8_t ttcm : 1; /**< Time triggered communication mode */
uint8_t abom : 1; /**< Automatic bus-off management */
uint8_t awum : 1; /**< Automatic wakeup mode */
uint8_t nart : 1; /**< No automatic retransmission */
uint8_t rflm : 1; /**< Receive FIFO locked mode */
uint8_t txfp : 1; /**< Transmit FIFO priority */
uint8_t lbkm : 1; /**< Loopback mode */
uint8_t silm : 1; /**< Silent mode */
} can_conf_t;
/** can_conf_t is re-defined */
#define HAVE_CAN_CONF_T
/**
* @name STM32 mailboxes
* @{
*/
#define FDCAN_STM32_TX_MAILBOXES 3
/**< Number of frame the driver can transmit simultaneously */
#define FDCAN_STM32_RX_MAILBOXES (FDCANDEV_STM32_CHAN_NUMOF * 6)
/**< Maximum number of frame the driver can receive simultaneously.
There are 3 buffers per FIFO and 2 FIFO per channel. */
/** @} */
/** FDCAN candev descriptor */
typedef struct can can_t;
/** can_t is re-defined */
#define HAVE_CAN_T
#define FDCAN_SRAM_MESSAGE_RAM_SIZE 0x350 /**< FDCAN SRAM message size */
/**
* @name Message RAM addresses - 32 bits aligned
* @{
*/
#define FDCAN_SRAM_FLESA 0x1CU /**< Filter List Extended Start Address */
#define FDCAN_SRAM_F0SA 0x2CU /**< Rx FIFO0 Start Address */
#define FDCAN_SRAM_F1SA 0x62U /**< Rx FIFO1 Start Address */
#define FDCAN_SRAM_EFSA 0x98U /**< Event FIFO Start Address */
#define FDCAN_SRAM_TBSA 0x9EU /**< Tx Buffer Start Address */
/** @} */
/**
* @name Standard filter bit definition
* @{
*/
#define FDCAN_SRAM_FLS_SFID1_Pos (16U)
/**< Standard filter ID 1 position */
#define FDCAN_SRAM_FLS_SFID1_Msk (0x7FFU << FDCAN_SRAM_FLS_SFID1_Pos)
/**< Standard filter ID 1 mask */
#define FDCAN_SRAM_FLS_SFID1 FDCAN_SRAM_FLS_SFID1_Msk
/**< Standard filter ID 1 */
#define FDCAN_SRAM_FLS_SFID2_Msk (0x7FFU)
/**< Standard filter ID 2 mask */
#define FDCAN_SRAM_FLS_SFID2 FDCAN_SRAM_FLS_SFID2_Msk
/**< Standard filter ID 2 */
#define FDCAN_SRAM_FLS_SFT_Pos (30U)
/**< Standard filter type position */
#define FDCAN_SRAM_FLS_SFT_Msk (0x3U << FDCAN_SRAM_FLS_SFT_Pos)
/**< Standard filter type mask */
#define FDCAN_SRAM_FLS_SFT FDCAN_SRAM_FLS_SFT_Msk
/**< Standard filter type */
#define FDCAN_SRAM_FLS_SFEC_Pos (27U)
/**< Standard filter element configuration position */
#define FDCAN_SRAM_FLS_SFEC_Msk (0x7U << FDCAN_SRAM_FLS_SFEC_Pos)
/**< Standard filter element configuration mask */
#define FDCAN_SRAM_FLS_SFEC FDCAN_SRAM_FLS_SFEC_Msk
/**< Standard filter element configuration */
/** @} */
/**
* @name Standard filter configuration
* @{
*/
#define FDCAN_SRAM_FLS_FILTER_SIZE 1U
/**< Standard filter size */
#define FDCAN_SRAM_FLS_SFT_DISABLED (0x3U << FDCAN_SRAM_FLS_SFT_Pos)
/**< Filter element disabled */
#define FDCAN_SRAM_FLS_SFT_CLASSIC (0x2U << FDCAN_SRAM_FLS_SFT_Pos)
/**< Classic filter */
#define FDCAN_SRAM_FLS_SFEC_DISABLED (0x0U << FDCAN_SRAM_FLS_SFEC_Pos)
/**< Filter element disabled */
#define FDCAN_SRAM_FLS_SFEC_FIFO0 (0x1U << FDCAN_SRAM_FLS_SFEC_Pos)
/**< Use FIFO0 if filter matches */
#define FDCAN_SRAM_FLS_SFEC_FIFO1 (0x2U << FDCAN_SRAM_FLS_SFEC_Pos)
/**< Use FIFO1 if filter matches*/
/** @} */
/**
* @name Extended filter bit definition
* @{
*/
#define FDCAN_SRAM_FLE_F0_EFID1_Msk 0x1FFFFFFFU
/**< Extended filter ID 1 mask */
#define FDCAN_SRAM_FLE_F0_EFID1 FDCAN_SRAM_FLE_F0_EFID1_Msk
/**< Extended filter ID 1 */
#define FDCAN_SRAM_FLE_F1_EFID2_Msk 0x1FFFFFFFU
/**< Extended filter ID 2 mask */
#define FDCAN_SRAM_FLE_F1_EFID2 FDCAN_SRAM_FLE_F1_EFID2_Msk
/**< Extended filter ID 2 */
#define FDCAN_SRAM_FLE_F1_EFT_Pos 30U
/**< Extended filter type position */
#define FDCAN_SRAM_FLE_F1_EFT_Msk (0x3U << FDCAN_SRAM_FLE_F1_EFT_Pos)
/**< Extended filter type mask */
#define FDCAN_SRAM_FLE_F1_EFT FDCAN_SRAM_FLE_F1_EFT_Msk
/**< Extended filter type */
#define FDCAN_SRAM_FLE_F0_EFEC_Pos 29U
/**< Extended filter element configuration position */
#define FDCAN_SRAM_FLE_F0_EFEC_Msk (0x7U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
/**< Extended filter element configuration mask */
#define FDCAN_SRAM_FLE_F0_EFEC FDCAN_SRAM_FLE_F0_EFEC_Msk
/**< Extended filter element configuration */
/** @} */
/**
* @name Extended filter configuration
* @{
*/
#define FDCAN_SRAM_FLE_FILTER_SIZE 2U
/**< Extended filter size */
#define FDCAN_SRAM_FLE_F1_EFT_CLASSIC (0x2U << FDCAN_SRAM_FLE_F1_EFT_Pos)
/**< Classic filter */
#define FDCAN_SRAM_FLE_F0_EFEC_DISABLED (0x0U)
/**< Disabled filter */
#define FDCAN_SRAM_FLE_F0_EFEC_FIFO0 (0x1U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
/**< Use FIFO0 if filter matches */
#define FDCAN_SRAM_FLE_F0_EFEC_FIFO1 (0x2U << FDCAN_SRAM_FLE_F0_EFEC_Pos)
/**< Use FIFI1 if filter matches */
/** @} */
/**
* @name Tx Buffer bits definition
* @{
*/
#define FDCAN_SRAM_TXBUFFER_T0_ESI_Pos 31U
/**< Error State Indicator position */
#define FDCAN_SRAM_TXBUFFER_T0_ESI_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
/**< Error State Indicator mask */
#define FDCAN_SRAM_TXBUFFER_T0_ESI FDCAN_SRAM_TXBUFFER_T0_ESI_Msk
/**< Error State Indicator */
#define FDCAN_SRAM_TXBUFFER_T0_XTD_Pos 30U
/**< Extended Identifier position */
#define FDCAN_SRAM_TXBUFFER_T0_XTD_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T0_XTD_Pos)
/**< Extended Identifier mask */
#define FDCAN_SRAM_TXBUFFER_T0_XTD FDCAN_SRAM_TXBUFFER_T0_XTD_Msk
/**< Extended Identifier */
#define FDCAN_SRAM_TXBUFFER_T0_RTR_Pos 29U
/**< Remote transmission request position*/
#define FDCAN_SRAM_TXBUFFER_T0_RTR_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T0_RTR_Pos)
/**< Remote transmission request mask */
#define FDCAN_SRAM_TXBUFFER_T0_RTR FDCAN_SRAM_TXBUFFER_T0_RTR_Msk
/**< Remote transmission request */
#define FDCAN_SRAM_TXBUFFER_T0_ID_Pos 18U
/**< Standard Identifier position */
#define FDCAN_SRAM_TXBUFFER_T1_EFC_Pos 23U
/**< Event FIFO Control position */
#define FDCAN_SRAM_TXBUFFER_T1_EFC_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
/**< Event FIFO Control mask */
#define FDCAN_SRAM_TXBUFFER_T1_EFC FDCAN_SRAM_TXBUFFER_T1_EFC_Msk
/**< Event FIFO Control */
#define FDCAN_SRAM_TXBUFFER_T1_FDF_Pos 21U
/**< FD Format position */
#define FDCAN_SRAM_TXBUFFER_T1_FDF_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
/**< FD Format mask */
#define FDCAN_SRAM_TXBUFFER_T1_FDF FDCAN_SRAM_TXBUFFER_T1_FDF_Msk
/**< FD Format */
#define FDCAN_SRAM_TXBUFFER_T1_BRS_Pos 20U
/**< Bit Rate Switching position */
#define FDCAN_SRAM_TXBUFFER_T1_BRS_Msk (0x1U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
/**< Bit Rate Switching mask */
#define FDCAN_SRAM_TXBUFFER_T1_BRS FDCAN_SRAM_TXBUFFER_T1_BRS_Msk
/**< Bit Rate Switching */
#define FDCAN_SRAM_TXBUFFER_T1_DLC_Pos 16U
/**< Data Length Code position */
#define FDCAN_SRAM_TXBUFFER_T1_DLC_Msk (0xFU << FDCAN_SRAM_TXBUFFER_T1_DLC_Pos)
/**< Data Length Code mask */
#define FDCAN_SRAM_TXBUFFER_T1_DLC FDCAN_SRAM_TXBUFFER_T1_DLC_Msk
/**< Data Length Code */
/** @} */
/**
* @name Tx buffers configuration
* @{
*/
#define FDCAN_SRAM_TXBUFFER_SIZE 18U
/**< Tx buffer size */
#define FDCAN_SRAM_TXBUFFER_T0_ESI_PASSIVE_FLAG (0x0U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
/**< ESI bit in CAN FD format depends only on error passive flag */
#define FDCAN_SRAM_TXBUFFER_T0_ESI_RECESSIVE (0x1U << FDCAN_SRAM_TXBUFFER_T0_ESI_Pos)
/**< ESI bit in CAN FD format transmitted recessive */
#define FDCAN_SRAM_TXBUFFER_T1_EFC_DISABLE (0x0U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
/**< Do not store Tx events */
#define FDCAN_SRAM_TXBUFFER_T1_EFC_STORE_EVENTS (0x1U << FDCAN_SRAM_TXBUFFER_T1_EFC_Pos)
/**< Store Tx events */
#define FDCAN_SRAM_TXBUFFER_T1_FDF_CLASSIC (0x0U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
/**< Classic CAN format */
#define FDCAN_SRAM_TXBUFFER_T1_FDF_FD (0x1U << FDCAN_SRAM_TXBUFFER_T1_FDF_Pos)
/**< CAN FD format */
#define FDCAN_SRAM_TXBUFFER_T1_BRS_OFF (0x0U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
/**< Disable CAN FD bit rate switching */
#define FDCAN_SRAM_TXBUFFER_T1_BRS_ON (0x1U << FDCAN_SRAM_TXBUFFER_T1_BRS_Pos)
/**< Enable CAN FD bit rate switching */
/** @} */
/**
* @name Rx Buffer bits definition
* @{
*/
#define FDCAN_SRAM_RXFIFO_R0_ESI_Pos 31U
/**< Error State Indicator position */
#define FDCAN_SRAM_RXFIFO_R0_ESI_Msk (0x1U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
/**< Error State Indicator mask */
#define FDCAN_SRAM_RXFIFO_R0_ESI FDCAN_SRAM_RXFIFO_R0_ESI_Msk
/**< Error State Indicator */
#define FDCAN_SRAM_RXFIFO_R0_XTD_Pos 30U
/**< Extended Identifier position */
#define FDCAN_SRAM_RXFIFO_R0_XTD_Msk (0x1U << FDCAN_SRAM_RXFIFO_R0_XTD_Pos)
/**< Extended Identifier mask */
#define FDCAN_SRAM_RXFIFO_R0_XTD FDCAN_SRAM_RXFIFO_R0_XTD_Msk
/**< Extended Identifier */
#define FDCAN_SRAM_RXFIFO_R0_RTR_Pos 29U
/**< Remote transmission request position*/
#define FDCAN_SRAM_RXFIFO_R0_RTR_Msk (0x1U << FDCAN_SRAM_RXFIFO_R0_RTR_Pos)
/**< Remote transmission request mask */
#define FDCAN_SRAM_RXFIFO_R0_RTR FDCAN_SRAM_RXFIFO_R0_RTR_Msk
/**< Remote transmission request */
#define FDCAN_SRAM_RXFIFO_R0_ID_Pos 18U
/**< Standard Identifier position */
#define FDCAN_SRAM_RXFIFO_R0_ID_Msk 0x1FFFFFFFU
/**< Identifier mask */
#define FDCAN_SRAM_RXFIFO_R0_ID FDCAN_SRAM_RXFIFO_R0_ID_Msk
/**< Identifier */
#define FDCAN_SRAM_RXFIFO_R1_EFC_Pos 23U
/**< Event FIFO Control position */
#define FDCAN_SRAM_RXFIFO_R1_EFC_Msk (0x1U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
/**< Event FIFO Control mask */
#define FDCAN_SRAM_RXFIFO_R1_EFC FDCAN_SRAM_RXFIFO_R1_EFC_Msk
/**< Event FIFO Control */
#define FDCAN_SRAM_RXFIFO_R1_FDF_Pos 21U
/**< FD Format position */
#define FDCAN_SRAM_RXFIFO_R1_FDF_Msk (0x1U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
/**< FD Format mask */
#define FDCAN_SRAM_RXFIFO_R1_FDF FDCAN_SRAM_RXFIFO_R1_FDF_Msk
/**< FD Format */
#define FDCAN_SRAM_RXFIFO_R1_BRS_Pos 20U
/**< Bit Rate Switching position */
#define FDCAN_SRAM_RXFIFO_R1_BRS_Msk (0x1U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
/**< Bit Rate Switching mask */
#define FDCAN_SRAM_RXFIFO_R1_BRS FDCAN_SRAM_RXFIFO_R1_BRS_Msk
/**< Bit Rate Switching */
#define FDCAN_SRAM_RXFIFO_R1_DLC_Pos 16U
/**< Data Length Code position */
#define FDCAN_SRAM_RXFIFO_R1_DLC_Msk (0xFU << FDCAN_SRAM_RXFIFO_R1_DLC_Pos)
/**< Data Length Code mask */
#define FDCAN_SRAM_RXFIFO_R1_DLC FDCAN_SRAM_RXFIFO_R1_DLC_Msk
/**< Data Length Code */
/** @} */
/**
* @name Rx buffers configuration
* @{
*/
#define FDCAN_SRAM_RXFIFO_SIZE 54U
/**< Rx FIFO size */
#define FDCAN_SRAM_RXFIFO_ELEMENT_SIZE 18U
/**< Rx FIFO element size */
#define FDCAN_SRAM_RXFIFO_R0_ESI_PASSIVE_FLAG (0x0U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
/**< ESI bit in CAN FD format depends only on error passive flag */
#define FDCAN_SRAM_RXFIFO_R0_ESI_RECESSIVE (0x1U << FDCAN_SRAM_RXFIFO_R0_ESI_Pos)
/**< ESI bit in CAN FD format transmitted recessive */
#define FDCAN_SRAM_RXFIFO_R1_EFC_DISABLE (0x0U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
/**< Do not store Rx events */
#define FDCAN_SRAM_RXFIFO_R1_EFC_STORE_EVENTS (0x1U << FDCAN_SRAM_RXFIFO_R1_EFC_Pos)
/**< Store Rx events */
#define FDCAN_SRAM_RXFIFO_R1_FDF_CLASSIC (0x0U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
/**< Classic CAN format */
#define FDCAN_SRAM_RXFIFO_R1_FDF_FD (0x1U << FDCAN_SRAM_RXFIFO_R1_FDF_Pos)
/**< CAN FD format */
#define FDCAN_SRAM_RXFIFO_R1_BRS_OFF (0x0U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
/**< CAN FD bit rate switching enabled */
#define FDCAN_SRAM_RXFIFO_R1_BRS_ON (0x1U << FDCAN_SRAM_RXFIFO_R1_BRS_Pos)
/**< CAN FD bit rate switching disabled */
/** @} */
/** This structure holds anything related to the receive part */
typedef struct candev_stm32_rx_mailbox {
can_frame_t frame[FDCAN_STM32_RX_MAILBOXES];
/**< Receive FIFO */
int write_idx;
/**< Write index in the receive FIFO */
int read_idx;
/**< Read index in the receive FIFO*/
int is_full;
/**< Flag set when the FIFO is full */
} candev_stm32_rx_mailbox_t;
/** Internal interrupt flags */
typedef struct candev_stm32_isr {
int isr_tx : 3; /**< Tx mailboxes interrupt */
int isr_rx : 2; /**< Rx FIFO interrupt */
int isr_wkup : 1; /**< Wake up interrupt */
} candev_stm32_isr_t;
/** STM32 CAN device descriptor */
struct can {
candev_t candev; /**< Common candev struct */
const can_conf_t *conf; /**< Configuration */
gpio_t rx_pin; /**< RX pin */
gpio_t tx_pin; /**< TX pin */
gpio_af_t af; /**< Alternate pin function to use */
const can_frame_t
*tx_mailbox[FDCAN_STM32_TX_MAILBOXES]; /**< Tx mailboxes*/
candev_stm32_rx_mailbox_t rx_mailbox; /**< Rx mailboxes */
candev_stm32_isr_t isr_flags; /**< ISR flags */
};
/**
* @brief Set the pins of an stm32 CAN device
*
* @param[in,out] dev the device to set pins
* @param[in] tx_pin tx pin
* @param[in] rx_pin rx pin
* @param[in] af alternate function
*/
void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin,
gpio_af_t af);
#ifdef __cplusplus
}
#endif
#endif /* FDCANDEV_STM32_H */
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