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https://github.com/RIOT-OS/RIOT.git
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fd105b7e77
This patch removes a largely redundant block of conditional includes. The removed includes are moved into the family specific headers so that the more specific headers may override defaults defined in the shared headers.
188 lines
6.3 KiB
C
188 lines
6.3 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Default STM32L4 clock configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CLK_L4L5WX_CFG_CLOCK_DEFAULT_H
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#define CLK_L4L5WX_CFG_CLOCK_DEFAULT_H
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#include "cfg_clock_common_lx_u5_wx.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name L4/L5/WB clock system configuration
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* @{
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*/
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
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#error "HSE clock frequency must be between 4MHz and 48MHz"
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#endif
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/* The following parameters configure a 80MHz system clock with PLL as input clock */
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#ifndef CONFIG_CLOCK_PLL_SRC_MSI
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
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IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CONFIG_CLOCK_PLL_SRC_MSI 0
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#else
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#define CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI as input clock by default */
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#endif
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#endif /* CONFIG_CLOCK_PLL_SRC_MSI */
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#ifndef CONFIG_CLOCK_PLL_SRC_HSE
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && \
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!IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
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#define CONFIG_CLOCK_PLL_SRC_HSE 1
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#else
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#define CONFIG_CLOCK_PLL_SRC_HSE 0
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_SRC_HSI
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#define CONFIG_CLOCK_PLL_SRC_HSI 0
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
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#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
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#else /* CONFIG_CLOCK_PLL_SRC_ */
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
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#endif
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#ifndef CONFIG_CLOCK_PLL_M
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
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#define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */
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#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
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#define CONFIG_CLOCK_PLL_M (1) /* HSE at 8MHz */
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#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32))
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#define CONFIG_CLOCK_PLL_M (4) /* HSE at 32MHz */
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#else
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#define CONFIG_CLOCK_PLL_M (2) /* HSI at 16MHz */
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32))
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/* For STM32WL, VCO output frequency ((PLL input clock frequency / PLLM ) x PLLN )
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must be between 96 and 344 MHz. PLLN can have values <=127 & >=6 */
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#if IS_ACTIVE(CPU_FAM_STM32WL)
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#define CONFIG_CLOCK_PLL_N (12)
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#else
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#define CONFIG_CLOCK_PLL_N (16)
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#endif /* CPU_FAM_STM32WL */
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#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
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(IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(16)))
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#define CONFIG_CLOCK_PLL_N (32)
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#else
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#if defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
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defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
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defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
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defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
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defined(CPU_LINE_STM32L4S9xx)
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#define CONFIG_CLOCK_PLL_N (30)
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#elif defined(CPU_FAM_STM32L5)
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#define CONFIG_CLOCK_PLL_N (27)
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#else
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#define CONFIG_CLOCK_PLL_N (20)
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#endif
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (2)
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#endif
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2:8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 64MHz, 80MHZ or 120MHz MAX!
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*/
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#define CLOCK_CORECLOCK \
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((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
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/* Set max allowed sysclk */
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#if defined(CPU_FAM_STM32WL)
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#define CLOCK_CORECLOCK_MAX MHZ(48)
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#elif defined(CPU_FAM_STM32WB)
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#define CLOCK_CORECLOCK_MAX MHZ(64)
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#elif defined(CPU_FAM_STM32L5)
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#define CLOCK_CORECLOCK_MAX MHZ(110)
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#elif defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
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defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
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defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
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defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
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defined(CPU_LINE_STM32L4S9xx)
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#define CLOCK_CORECLOCK_MAX MHZ(120)
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#else /* all the other L4 */
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#define CLOCK_CORECLOCK_MAX MHZ(80)
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#endif
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#if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
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#if CLOCK_CORECLOCK_MAX == MHZ(48)
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#error "SYSCLK cannot exceed 48MHz"
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#elif CLOCK_CORECLOCK_MAX == MHZ(64)
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#error "SYSCLK cannot exceed 64MHz"
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#elif CLOCK_CORECLOCK_MAX == MHZ(80)
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#error "SYSCLK cannot exceed 80MHz"
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#elif CLOCK_CORECLOCK_MAX == MHZ(110)
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#error "SYSCLK cannot exceed 110MHz"
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#elif CLOCK_CORECLOCK_MAX == MHZ(120)
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#error "SYSCLK cannot exceed 120MHz"
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#else
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#error "invalid SYSCLK"
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#endif
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#endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48/64/80/120MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (4)
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#endif
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#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48/64/80/120MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2)
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#endif
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#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 48/64/80/120MHz */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CLK_L4L5WX_CFG_CLOCK_DEFAULT_H */
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/** @} */
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