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https://github.com/RIOT-OS/RIOT.git
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fd105b7e77
This patch removes a largely redundant block of conditional includes. The removed includes are moved into the family specific headers so that the more specific headers may override defaults defined in the shared headers.
118 lines
3.0 KiB
C
118 lines
3.0 KiB
C
/*
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* Copyright (C) 2020 Savoir-faire Linux
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Main header for STM32MP1 clock configuration
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*
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* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
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*/
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#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_H
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#define CLK_MP1_CFG_CLOCK_DEFAULT_H
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#include "cfg_clock_common_fx_gx_mp1_c0.h"
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/**
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* @name MP1 clock PLL settings (208MHz)
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* @{
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*/
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/* The following parameters configure a 208MHz system clock with HSE (24MHz)
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* or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (2)
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#endif
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(24))
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (52)
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#endif
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#else /* HSI */
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (78)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (3)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (13)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (3)
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#endif
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/** @} */
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/**
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* @name MP1 clock bus settings (MCU, APB1, APB2 and APB3)
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* @{
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*/
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#ifndef CONFIG_CLOCK_MCU_DIV
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#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB3_DIV
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#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */
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#endif
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/** @} */
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#if CLOCK_CORECLOCK > MHZ(208)
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#error "SYSCLK cannot exceed 208MHz"
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#endif
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/**
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* @name MP1 clock values
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* @{
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*/
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
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#else /* CONFIG_CLOCK_HSI */
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
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#endif
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
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#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
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#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
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* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \
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* CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
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#define CLOCK_APB1 (CLOCK_CORECLOCK \
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/ CONFIG_CLOCK_APB1_DIV)
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#define CLOCK_APB2 (CLOCK_CORECLOCK \
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/ CONFIG_CLOCK_APB2_DIV)
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/** @} */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_H */
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/** @} */
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