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RIOT supports two distinct families of the MSP430: The [MSP430 x1xx]
MCU family and the [MSP430 F2xx/G2xx] MCU family. For both incompatible
MCU families the code was located in the msp430fxyz folder, resulting
in case of the UART driver in particularly bizarre code looking roughly
like this:
#ifndef UART_USE_USCI
/* implementation of x1xx peripheral ... */
#else
/* implementation of F2xx/G2xx peripheral ... */
#endif
/* zero shared code between both variants */
This splits the peripheral drivers for USCI and USART serial IP blocks
into separate files and relocates everything in cpu/msp430, similar to
how cpu/stm32 is organized.
[MSP430 x1xx]: https://www.ti.com/lit/ug/slau049f/slau049f.pdf
[MSP430 F2xx/G2xx]: https://www.ti.com/lit/ug/slau144k/slau144k.pdf
239 lines
7.0 KiB
C
239 lines
7.0 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430
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* @{
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*
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* @file
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* @brief Cortex CMSIS style definition of MSP430 registers
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*
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* @todo This file is incomplete, not all registers are listed. Further
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* There are probably some inconsistencies throughout the MSP430
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* family which need to be addressed.
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef MSP430_REGS_COMMON_H
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#define MSP430_REGS_COMMON_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Shortcut to specify 8-bit wide registers
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*/
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#define REG8 volatile uint8_t
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/**
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* @brief Shortcut to specify 16-bit wide registers
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*/
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#define REG16 volatile uint16_t
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/**
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* @brief Special function registers
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*/
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typedef struct {
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REG8 IE1; /**< interrupt enable 1 */
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REG8 IE2; /**< interrupt enable 2 */
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REG8 IFG1; /**< interrupt flag 1 */
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REG8 IFG2; /**< interrupt flag 2 */
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REG8 ME1; /**< module enable 1 */
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REG8 ME2; /**< module enable 2 */
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} msp_sfr_t;
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/**
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* @brief Digital I/O Port w/o interrupt functionality (P3-P6)
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*/
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typedef struct {
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REG8 IN; /**< input data */
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REG8 OD; /**< output data */
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REG8 DIR; /**< pin direction */
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REG8 SEL; /**< alternative function select */
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} msp_port_t;
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/**
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* @brief Digital I/O Port with interrupt functionality (P1 & P2)
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*/
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typedef struct {
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REG8 IN; /**< input data */
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REG8 OD; /**< output data */
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REG8 DIR; /**< pin direction */
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REG8 IFG; /**< interrupt flag */
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REG8 IES; /**< interrupt edge select */
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REG8 IE; /**< interrupt enable */
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REG8 SEL; /**< alternative function select */
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} msp_port_isr_t;
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/**
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* @brief Timer interrupt status registers
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*/
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typedef struct {
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REG16 TBIV; /**< TIMER_A interrupt status */
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REG16 reserved[7]; /**< reserved */
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REG16 TAIV; /**< TIMER_B interrupt status */
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} msp_timer_ivec_t;
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/**
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* @brief Timer module registers
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*/
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typedef struct {
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REG16 CTL; /**< timer control */
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REG16 CCTL[7]; /**< capture compare channel control */
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REG16 R; /**< current counter value */
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REG16 CCR[7]; /**< capture compare channel values */
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} msp_timer_t;
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/**
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* @name SFR interrupt enable 1 register bitmap
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* @{
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*/
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#define SFR_IE1_OFIE (0x02)
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#define SFR_IE1_URXIE0 (0x40)
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#define SFR_IE1_UTXIE0 (0x80)
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/** @} */
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/**
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* @name SFR interrupt enable 2 register bitmap
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* @{
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*/
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#define SFR_IE2_UCA0RXIE (0x01)
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#define SFR_IE2_UCA0TXIE (0x02)
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#define SFR_IE2_URXIE2 (0x10)
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#define SFR_IE2_UTXIE2 (0x20)
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/** @} */
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/**
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* @name SFR interrupt flag 1 register bitmap
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* @{
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*/
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#define SFR_IFG1_OFIFG (0x02)
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#define SFR_IFG1_URXIFG0 (0x40)
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#define SFR_IFG1_UTXIFG0 (0x80)
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/** @} */
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/**
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* @name SFR interrupt flag 2 register bitmap
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* @{
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*/
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#define SFR_IFG2_UCA0RXIFG (0x01)
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#define SFR_IFG2_UCA0TXIFG (0x02)
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#define SFR_IFG2_URXIFG1 (0x10)
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#define SFR_IFG2_UTXIFG1 (0x20)
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/** @} */
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/**
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* @name SFR module enable register 1
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* @{
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*/
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#define SFR_ME1_USPIE0 (0x40)
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/** @} */
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/**
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* @name SFR module enable register 2
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* @{
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*/
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#define SFR_ME2_USPIE1 (0x10)
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/** @} */
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/**
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* @name Timer Control register bitmap
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* @{
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*/
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#define TIMER_CTL_IFG (0x0001)
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#define TIMER_CTL_IE (0x0002)
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#define TIMER_CTL_CLR (0x0004)
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#define TIMER_CTL_MC_MASK (0x0030)
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#define TIMER_CTL_MC_STOP (0x0000)
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#define TIMER_CTL_MC_UP (0x0010)
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#define TIMER_CTL_MC_CONT (0x0020)
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#define TIMER_CTL_MC_UPDOWN (0x0030)
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#define TIMER_CTL_ID_MASK (0x00c0)
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#define TIMER_CTL_ID_DIV1 (0x0000)
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#define TIMER_CTL_ID_DIV2 (0x0040)
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#define TIMER_CTL_ID_DIV4 (0x0080)
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#define TIMER_CTL_ID_DIV8 (0x00c0)
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#define TIMER_CTL_TASSEL_MASK (0x0300)
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#define TIMER_CTL_TASSEL_TCLK (0x0000)
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#define TIMER_CTL_TASSEL_ACLK (0x0100)
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#define TIMER_CTL_TASSEL_SMCLK (0x0200)
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#define TIMER_CTL_TASSEL_INV_TCLK (0x0300)
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/** @} */
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/**
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* @name Timer Channel Control register bitmap
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* @{
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*/
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#define TIMER_CCTL_CCIFG (0x0001)
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#define TIMER_CCTL_COV (0x0002)
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#define TIMER_CCTL_OUT (0x0004)
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#define TIMER_CCTL_CCI (0x0008)
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#define TIMER_CCTL_CCIE (0x0010)
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#define TIMER_CCTL_OUTMOD_MASK (0x00e0)
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#define TIMER_CCTL_OUTMOD_OUTVAL (0x0000)
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#define TIMER_CCTL_OUTMOD_SET (0x0020)
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#define TIMER_CCTL_OUTMOD_TOG_RESET (0x0040)
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#define TIMER_CCTL_OUTMOD_SET_RESET (0x0060)
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#define TIMER_CCTL_OUTMOD_TOGGLE (0x0080)
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#define TIMER_CCTL_OUTMOD_RESET (0x00a0)
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#define TIMER_CCTL_OUTMOD_TOG_SET (0x00c0)
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#define TIMER_CCTL_OUTMOD_RESET_SET (0x00e0)
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#define TIMER_CCTL_CAP (0x0100)
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#define TIMER_CCTL_CLLD_MASK (0x0600)
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#define TIMER_CCTL_SCS (0x0800)
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#define TIMER_CCTL_CCIS_MASK (0x3000)
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#define TIMER_CCTL_CM_MASK (0xc000)
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/** @} */
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/**
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* @name Base register address definitions
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* @{
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*/
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#define SFR_BASE ((uint16_t)0x0000)
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#define PORT_1_BASE ((uint16_t)0x0020)
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#define PORT_2_BASE ((uint16_t)0x0028)
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#define PORT_3_BASE ((uint16_t)0x0018)
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#define PORT_4_BASE ((uint16_t)0x001c)
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#define PORT_5_BASE ((uint16_t)0x0030)
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#define PORT_6_BASE ((uint16_t)0x0034)
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#define CLK_BASE ((uint16_t)0x0053)
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#define TIMER_IVEC_BASE ((uint16_t)0x011e)
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#define TIMER_A_BASE ((uint16_t)0x0160)
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#define TIMER_B_BASE ((uint16_t)0x0180)
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#define WD_BASE ((uint16_t)0x0120)
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/** @} */
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/**
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* @name Typing of base register objects
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* @{
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*/
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#define SFR ((msp_sfr_t *)SFR_BASE)
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#define PORT_1 ((msp_port_t *)PORT_1_BASE)
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#define PORT_2 ((msp_port_t *)PORT_2_BASE)
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#define PORT_3 ((msp_port_t *)PORT_3_BASE)
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#define PORT_4 ((msp_port_t *)PORT_4_BASE)
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#define PORT_5 ((msp_port_t *)PORT_5_BASE)
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#define PORT_6 ((msp_port_t *)PORT_6_BASE)
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#define CLK ((msp_clk_t *)CLK_BASE)
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#define TIMER_IVEC ((msp_timer_ivec_t *)TIMER_IVEC_BASE)
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#define TIMER_A ((msp_timer_t *)TIMER_A_BASE)
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#define TIMER_B ((msp_timer_t *)TIMER_B_BASE)
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#define WD ((msp_wd_t *)WD_BASE)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* MSP430_REGS_COMMON_H */
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/** @} */
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