/*
 * @note     Generated by SVDConv V3.3.35 on Tuesday, 01.09.2020 17:58:39
 *           from File 'GD32VF103.svd',
 */

#ifndef GD32VF103_PERIPH_H
#define GD32VF103_PERIPH_H

#include "stdint.h"

#ifdef __cplusplus
extern "C" {
#endif

/* =========================================================================================================================== */
/* ================                                           ADC0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog to digital converter (ADC0)
  */

typedef struct {                                /*!< (@ 0x40012400) ADC0 Structure                                             */

  union {
    __IO uint32_t STAT;                        /*!< (@ 0x00000000) status register                                            */

    struct {
      __IO uint32_t WDE        : 1;            /*!< [0..0] Analog watchdog event flag                                         */
      __IO uint32_t EOC        : 1;            /*!< [1..1] End of group conversion flag                                       */
      __IO uint32_t EOIC       : 1;            /*!< [2..2] End of inserted group conversion flag                              */
      __IO uint32_t STIC       : 1;            /*!< [3..3] Start flag of inserted channel group                               */
      __IO uint32_t STRC       : 1;            /*!< [4..4] Start flag of regular channel group                                */
            uint32_t            : 27;
    } STAT_b;
  } ;

  union {
    __IO uint32_t CTL0;                        /*!< (@ 0x00000004) control register 0                                         */

    struct {
      __IO uint32_t WDCHSEL    : 5;            /*!< [4..0] Analog watchdog channel select                                     */
      __IO uint32_t EOCIE      : 1;            /*!< [5..5] Interrupt enable for EOC                                           */
      __IO uint32_t WDEIE      : 1;            /*!< [6..6] Interrupt enable for WDE                                           */
      __IO uint32_t EOICIE     : 1;            /*!< [7..7] Interrupt enable for EOIC                                          */
      __IO uint32_t SM         : 1;            /*!< [8..8] Scan mode                                                          */
      __IO uint32_t WDSC       : 1;            /*!< [9..9] When in scan mode, analog watchdog is effective on a
                                                     single channel                                                            */
      __IO uint32_t ICA        : 1;            /*!< [10..10] Inserted channel group convert  automatically                    */
      __IO uint32_t DISRC      : 1;            /*!< [11..11] Discontinuous mode on regular channels                           */
      __IO uint32_t DISIC      : 1;            /*!< [12..12] Discontinuous mode on  inserted channels                         */
      __IO uint32_t DISNUM     : 3;            /*!< [15..13] Number of conversions in  discontinuous mode                     */
      __IO uint32_t SYNCM      : 4;            /*!< [19..16] sync mode selection                                              */
            uint32_t            : 2;
      __IO uint32_t IWDEN      : 1;            /*!< [22..22] Inserted channel analog watchdog  enable                         */
      __IO uint32_t RWDEN      : 1;            /*!< [23..23] Regular channel analog watchdog enable                           */
            uint32_t            : 8;
    } CTL0_b;
  } ;

  union {
    __IO uint32_t CTL1;                        /*!< (@ 0x00000008) control register 1                                         */

    struct {
      __IO uint32_t ADCON      : 1;            /*!< [0..0] ADC on                                                             */
      __IO uint32_t CTN        : 1;            /*!< [1..1] Continuous mode                                                    */
      __IO uint32_t CLB        : 1;            /*!< [2..2] ADC calibration                                                    */
      __IO uint32_t RSTCLB     : 1;            /*!< [3..3] Reset calibration                                                  */
            uint32_t            : 4;
      __IO uint32_t DMA        : 1;            /*!< [8..8] DMA request enable                                                 */
            uint32_t            : 2;
      __IO uint32_t DAL        : 1;            /*!< [11..11] Data alignment                                                   */
      __IO uint32_t ETSIC      : 3;            /*!< [14..12] External trigger select for inserted channel                     */
      __IO uint32_t ETEIC      : 1;            /*!< [15..15] External trigger select for inserted channel                     */
            uint32_t            : 1;
      __IO uint32_t ETSRC      : 3;            /*!< [19..17] External trigger select for regular channel                      */
      __IO uint32_t ETERC      : 1;            /*!< [20..20] External trigger enable for regular channel                      */
      __IO uint32_t SWICST     : 1;            /*!< [21..21] Start on inserted channel                                        */
      __IO uint32_t SWRCST     : 1;            /*!< [22..22] Start on regular channel                                         */
      __IO uint32_t TSVREN     : 1;            /*!< [23..23] Channel 16 and 17 enable of ADC0                                 */
            uint32_t            : 8;
    } CTL1_b;
  } ;

  union {
    __IO uint32_t SAMPT0;                      /*!< (@ 0x0000000C) Sample time register 0                                     */

    struct {
      __IO uint32_t SPT10      : 3;            /*!< [2..0] Channel 10 sample time selection                                   */
      __IO uint32_t SPT11      : 3;            /*!< [5..3] Channel 11 sample time selection                                   */
      __IO uint32_t SPT12      : 3;            /*!< [8..6] Channel 12 sample time selection                                   */
      __IO uint32_t SPT13      : 3;            /*!< [11..9] Channel 13 sample time selection                                  */
      __IO uint32_t SPT14      : 3;            /*!< [14..12] Channel 14 sample time selection                                 */
      __IO uint32_t SPT15      : 3;            /*!< [17..15] Channel 15 sample time selection                                 */
      __IO uint32_t SPT16      : 3;            /*!< [20..18] Channel 16 sample time selection                                 */
      __IO uint32_t SPT17      : 3;            /*!< [23..21] Channel 17 sample time selection                                 */
            uint32_t            : 8;
    } SAMPT0_b;
  } ;

  union {
    __IO uint32_t SAMPT1;                      /*!< (@ 0x00000010) Sample time register 1                                     */

    struct {
      __IO uint32_t SPT0       : 3;            /*!< [2..0] Channel 0 sample time selection                                    */
      __IO uint32_t SPT1       : 3;            /*!< [5..3] Channel 1 sample time selection                                    */
      __IO uint32_t SPT2       : 3;            /*!< [8..6] Channel 2 sample time selection                                    */
      __IO uint32_t SPT3       : 3;            /*!< [11..9] Channel 3 sample time selection                                   */
      __IO uint32_t SPT4       : 3;            /*!< [14..12] Channel 4 sample time selection                                  */
      __IO uint32_t SPT5       : 3;            /*!< [17..15] Channel 5 sample time selection                                  */
      __IO uint32_t SPT6       : 3;            /*!< [20..18] Channel 6 sample time selection                                  */
      __IO uint32_t SPT7       : 3;            /*!< [23..21] Channel 7 sample time selection                                  */
      __IO uint32_t SPT8       : 3;            /*!< [26..24] Channel 8 sample time selection                                  */
      __IO uint32_t SPT9       : 3;            /*!< [29..27] Channel 9 sample time selection                                  */
            uint32_t            : 2;
    } SAMPT1_b;
  } ;

  union {
    __IO uint32_t IOFF0;                       /*!< (@ 0x00000014) Inserted channel data offset register 0                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 0                                */
            uint32_t            : 20;
    } IOFF0_b;
  } ;

  union {
    __IO uint32_t IOFF1;                       /*!< (@ 0x00000018) Inserted channel data offset register 1                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 1                                */
            uint32_t            : 20;
    } IOFF1_b;
  } ;

  union {
    __IO uint32_t IOFF2;                       /*!< (@ 0x0000001C) Inserted channel data offset register 2                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 2                                */
            uint32_t            : 20;
    } IOFF2_b;
  } ;

  union {
    __IO uint32_t IOFF3;                       /*!< (@ 0x00000020) Inserted channel data offset register 3                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 3                                */
            uint32_t            : 20;
    } IOFF3_b;
  } ;

  union {
    __IO uint32_t WDHT;                        /*!< (@ 0x00000024) watchdog higher threshold register                         */

    struct {
      __IO uint32_t WDHT       : 12;           /*!< [11..0] Analog watchdog higher threshold                                  */
            uint32_t            : 20;
    } WDHT_b;
  } ;

  union {
    __IO uint32_t WDLT;                        /*!< (@ 0x00000028) watchdog lower threshold register                          */

    struct {
      __IO uint32_t WDLT       : 12;           /*!< [11..0] Analog watchdog lower threshold                                   */
            uint32_t            : 20;
    } WDLT_b;
  } ;

  union {
    __IO uint32_t RSQ0;                        /*!< (@ 0x0000002C) regular sequence register 0                                */

    struct {
      __IO uint32_t RSQ12      : 5;            /*!< [4..0] 13th conversion in regular sequence                                */
      __IO uint32_t RSQ13      : 5;            /*!< [9..5] 14th conversion in regular sequence                                */
      __IO uint32_t RSQ14      : 5;            /*!< [14..10] 15th conversion in regular sequence                              */
      __IO uint32_t RSQ15      : 5;            /*!< [19..15] 16th conversion in regular sequence                              */
      __IO uint32_t RL         : 4;            /*!< [23..20] Regular channel group length                                     */
            uint32_t            : 8;
    } RSQ0_b;
  } ;

  union {
    __IO uint32_t RSQ1;                        /*!< (@ 0x00000030) regular sequence register 1                                */

    struct {
      __IO uint32_t RSQ6       : 5;            /*!< [4..0] 7th conversion in regular sequence                                 */
      __IO uint32_t RSQ7       : 5;            /*!< [9..5] 8th conversion in regular sequence                                 */
      __IO uint32_t RSQ8       : 5;            /*!< [14..10] 9th conversion in regular sequence                               */
      __IO uint32_t RSQ9       : 5;            /*!< [19..15] 10th conversion in regular sequence                              */
      __IO uint32_t RSQ10      : 5;            /*!< [24..20] 11th conversion in regular sequence                              */
      __IO uint32_t RSQ11      : 5;            /*!< [29..25] 12th conversion in regular sequence                              */
            uint32_t            : 2;
    } RSQ1_b;
  } ;

  union {
    __IO uint32_t RSQ2;                        /*!< (@ 0x00000034) regular sequence register 2                                */

    struct {
      __IO uint32_t RSQ0       : 5;            /*!< [4..0] 1st conversion in regular sequence                                 */
      __IO uint32_t RSQ1       : 5;            /*!< [9..5] 2nd conversion in regular sequence                                 */
      __IO uint32_t RSQ2       : 5;            /*!< [14..10] 3rd conversion in regular sequence                               */
      __IO uint32_t RSQ3       : 5;            /*!< [19..15] 4th conversion in regular sequence                               */
      __IO uint32_t RSQ4       : 5;            /*!< [24..20] 5th conversion in regular sequence                               */
      __IO uint32_t RSQ5       : 5;            /*!< [29..25] 6th conversion in regular sequence                               */
            uint32_t            : 2;
    } RSQ2_b;
  } ;

  union {
    __IO uint32_t ISQ;                         /*!< (@ 0x00000038) Inserted sequence register                                 */

    struct {
      __IO uint32_t ISQ0       : 5;            /*!< [4..0] 1st conversion in inserted sequence                                */
      __IO uint32_t ISQ1       : 5;            /*!< [9..5] 2nd conversion in inserted sequence                                */
      __IO uint32_t ISQ2       : 5;            /*!< [14..10] 3rd conversion in inserted sequence                              */
      __IO uint32_t ISQ3       : 5;            /*!< [19..15] 4th conversion in inserted sequence                              */
      __IO uint32_t IL         : 2;            /*!< [21..20] Inserted channel group length                                    */
            uint32_t            : 10;
    } ISQ_b;
  } ;

  union {
    __I  uint32_t IDATA0;                      /*!< (@ 0x0000003C) Inserted data register 0                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA0_b;
  } ;

  union {
    __I  uint32_t IDATA1;                      /*!< (@ 0x00000040) Inserted data register 1                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA1_b;
  } ;

  union {
    __I  uint32_t IDATA2;                      /*!< (@ 0x00000044) Inserted data register 2                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA2_b;
  } ;

  union {
    __I  uint32_t IDATA3;                      /*!< (@ 0x00000048) Inserted data register 3                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA3_b;
  } ;

  union {
    __I  uint32_t RDATA;                       /*!< (@ 0x0000004C) regular data register                                      */

    struct {
      __I  uint32_t RDATA      : 16;           /*!< [15..0] Regular channel data                                              */
      __I  uint32_t ADC1RDTR   : 16;           /*!< [31..16] ADC regular channel data                                         */
    } RDATA_b;
  } ;
  __I  uint32_t  RESERVED[12];

  union {
    __IO uint32_t OVSAMPCTL;                   /*!< (@ 0x00000080) Oversample control register                                */

    struct {
      __IO uint32_t OVSEN      : 1;            /*!< [0..0] Oversampler Enable                                                 */
            uint32_t            : 1;
      __IO uint32_t OVSR       : 3;            /*!< [4..2] Oversampling ratio                                                 */
      __IO uint32_t OVSS       : 4;            /*!< [8..5] Oversampling shift                                                 */
      __IO uint32_t TOVS       : 1;            /*!< [9..9] Triggered Oversampling                                             */
            uint32_t            : 2;
      __IO uint32_t DRES       : 2;            /*!< [13..12] ADC resolution                                                   */
            uint32_t            : 18;
    } OVSAMPCTL_b;
  } ;
} ADC0_Type;                                    /*!< Size = 132 (0x84)                                                         */



/* =========================================================================================================================== */
/* ================                                           ADC1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog to digital converter (ADC1)
  */

typedef struct {                                /*!< (@ 0x40012800) ADC1 Structure                                             */

  union {
    __IO uint32_t STAT;                        /*!< (@ 0x00000000) status register                                            */

    struct {
      __IO uint32_t WDE        : 1;            /*!< [0..0] Analog watchdog event flag                                         */
      __IO uint32_t EOC        : 1;            /*!< [1..1] End of group conversion flag                                       */
      __IO uint32_t EOIC       : 1;            /*!< [2..2] End of inserted group conversion flag                              */
      __IO uint32_t STIC       : 1;            /*!< [3..3] Start flag of inserted channel group                               */
      __IO uint32_t STRC       : 1;            /*!< [4..4] Start flag of regular channel group                                */
            uint32_t            : 27;
    } STAT_b;
  } ;

  union {
    __IO uint32_t CTL0;                        /*!< (@ 0x00000004) control register 0                                         */

    struct {
      __IO uint32_t WDCHSEL    : 5;            /*!< [4..0] Analog watchdog channel select                                     */
      __IO uint32_t EOCIE      : 1;            /*!< [5..5] Interrupt enable for EOC                                           */
      __IO uint32_t WDEIE      : 1;            /*!< [6..6] Interrupt enable for WDE                                           */
      __IO uint32_t EOICIE     : 1;            /*!< [7..7] Interrupt enable for EOIC                                          */
      __IO uint32_t SM         : 1;            /*!< [8..8] Scan mode                                                          */
      __IO uint32_t WDSC       : 1;            /*!< [9..9] When in scan mode, analog watchdog is effective on a
                                                     single channel                                                            */
      __IO uint32_t ICA        : 1;            /*!< [10..10] Inserted channel group convert  automatically                    */
      __IO uint32_t DISRC      : 1;            /*!< [11..11] Discontinuous mode on regular channels                           */
      __IO uint32_t DISIC      : 1;            /*!< [12..12] Discontinuous mode on  inserted channels                         */
      __IO uint32_t DISNUM     : 3;            /*!< [15..13] Number of conversions in  discontinuous mode                     */
            uint32_t            : 6;
      __IO uint32_t IWDEN      : 1;            /*!< [22..22] Inserted channel analog watchdog  enable                         */
      __IO uint32_t RWDEN      : 1;            /*!< [23..23] Regular channel analog watchdog  enable                          */
            uint32_t            : 8;
    } CTL0_b;
  } ;

  union {
    __IO uint32_t CTL1;                        /*!< (@ 0x00000008) control register 1                                         */

    struct {
      __IO uint32_t ADCON      : 1;            /*!< [0..0] ADC on                                                             */
      __IO uint32_t CTN        : 1;            /*!< [1..1] Continuous mode                                                    */
      __IO uint32_t CLB        : 1;            /*!< [2..2] ADC calibration                                                    */
      __IO uint32_t RSTCLB     : 1;            /*!< [3..3] Reset calibration                                                  */
            uint32_t            : 4;
      __IO uint32_t DMA        : 1;            /*!< [8..8] DMA request enable                                                 */
            uint32_t            : 2;
      __IO uint32_t DAL        : 1;            /*!< [11..11] Data alignment                                                   */
      __IO uint32_t ETSIC      : 3;            /*!< [14..12] External trigger select for inserted channel                     */
      __IO uint32_t ETEIC      : 1;            /*!< [15..15] External trigger enable for inserted channel                     */
            uint32_t            : 1;
      __IO uint32_t ETSRC      : 3;            /*!< [19..17] External trigger select for regular channel                      */
      __IO uint32_t ETERC      : 1;            /*!< [20..20] External trigger enable for regular channel                      */
      __IO uint32_t SWICST     : 1;            /*!< [21..21] Start on inserted channel                                        */
      __IO uint32_t SWRCST     : 1;            /*!< [22..22] Start on regular channel                                         */
            uint32_t            : 9;
    } CTL1_b;
  } ;

  union {
    __IO uint32_t SAMPT0;                      /*!< (@ 0x0000000C) Sample time register 0                                     */

    struct {
      __IO uint32_t SPT10      : 3;            /*!< [2..0] Channel 10 sample time selection                                   */
      __IO uint32_t SPT11      : 3;            /*!< [5..3] Channel 11 sample time selection                                   */
      __IO uint32_t SPT12      : 3;            /*!< [8..6] Channel 12 sample time selection                                   */
      __IO uint32_t SPT13      : 3;            /*!< [11..9] Channel 13 sample time selection                                  */
      __IO uint32_t SPT14      : 3;            /*!< [14..12] Channel 14 sample time selection                                 */
      __IO uint32_t SPT15      : 3;            /*!< [17..15] Channel 15 sample time selection                                 */
      __IO uint32_t SPT16      : 3;            /*!< [20..18] Channel 16 sample time selection                                 */
      __IO uint32_t SPT17      : 3;            /*!< [23..21] Channel 17 sample time selection                                 */
            uint32_t            : 8;
    } SAMPT0_b;
  } ;

  union {
    __IO uint32_t SAMPT1;                      /*!< (@ 0x00000010) Sample time register 1                                     */

    struct {
      __IO uint32_t SPT0       : 3;            /*!< [2..0] Channel 0 sample time selection                                    */
      __IO uint32_t SPT1       : 3;            /*!< [5..3] Channel 1 sample time selection                                    */
      __IO uint32_t SPT2       : 3;            /*!< [8..6] Channel 2 sample time selection                                    */
      __IO uint32_t SPT3       : 3;            /*!< [11..9] Channel 3 sample time selection                                   */
      __IO uint32_t SPT4       : 3;            /*!< [14..12] Channel 4 sample time selection                                  */
      __IO uint32_t SPT5       : 3;            /*!< [17..15] Channel 5 sample time selection                                  */
      __IO uint32_t SPT6       : 3;            /*!< [20..18] Channel 6 sample time selection                                  */
      __IO uint32_t SPT7       : 3;            /*!< [23..21] Channel 7 sample time selection                                  */
      __IO uint32_t SPT8       : 3;            /*!< [26..24] Channel 8 sample time selection                                  */
      __IO uint32_t SPT9       : 3;            /*!< [29..27] Channel 9 sample time selection                                  */
            uint32_t            : 2;
    } SAMPT1_b;
  } ;

  union {
    __IO uint32_t IOFF0;                       /*!< (@ 0x00000014) Inserted channel data offset register 0                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 0                                */
            uint32_t            : 20;
    } IOFF0_b;
  } ;

  union {
    __IO uint32_t IOFF1;                       /*!< (@ 0x00000018) Inserted channel data offset register 1                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 1                                */
            uint32_t            : 20;
    } IOFF1_b;
  } ;

  union {
    __IO uint32_t IOFF2;                       /*!< (@ 0x0000001C) Inserted channel data offset register 2                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 2                                */
            uint32_t            : 20;
    } IOFF2_b;
  } ;

  union {
    __IO uint32_t IOFF3;                       /*!< (@ 0x00000020) Inserted channel data offset register 3                    */

    struct {
      __IO uint32_t IOFF       : 12;           /*!< [11..0] Data offset for inserted channel 3                                */
            uint32_t            : 20;
    } IOFF3_b;
  } ;

  union {
    __IO uint32_t WDHT;                        /*!< (@ 0x00000024) watchdog higher threshold register                         */

    struct {
      __IO uint32_t WDHT       : 12;           /*!< [11..0] Analog watchdog higher threshold                                  */
            uint32_t            : 20;
    } WDHT_b;
  } ;

  union {
    __IO uint32_t WDLT;                        /*!< (@ 0x00000028) watchdog lower threshold register                          */

    struct {
      __IO uint32_t WDLT       : 12;           /*!< [11..0] Analog watchdog lower threshold                                   */
            uint32_t            : 20;
    } WDLT_b;
  } ;

  union {
    __IO uint32_t RSQ0;                        /*!< (@ 0x0000002C) regular sequence register 0                                */

    struct {
      __IO uint32_t RSQ12      : 5;            /*!< [4..0] 13th conversion in regular sequence                                */
      __IO uint32_t RSQ13      : 5;            /*!< [9..5] 14th conversion in regular sequence                                */
      __IO uint32_t RSQ14      : 5;            /*!< [14..10] 15th conversion in regular sequence                              */
      __IO uint32_t RSQ15      : 5;            /*!< [19..15] 16th conversion in regular sequence                              */
      __IO uint32_t RL         : 4;            /*!< [23..20] Regular channel group length                                     */
            uint32_t            : 8;
    } RSQ0_b;
  } ;

  union {
    __IO uint32_t RSQ1;                        /*!< (@ 0x00000030) regular sequence register 1                                */

    struct {
      __IO uint32_t RSQ6       : 5;            /*!< [4..0] 7th conversion in regular sequence                                 */
      __IO uint32_t RSQ7       : 5;            /*!< [9..5] 8th conversion in regular sequence                                 */
      __IO uint32_t RSQ8       : 5;            /*!< [14..10] 9th conversion in regular sequence                               */
      __IO uint32_t RSQ9       : 5;            /*!< [19..15] 10th conversion in regular sequence                              */
      __IO uint32_t RSQ10      : 5;            /*!< [24..20] 11th conversion in regular sequence                              */
      __IO uint32_t RSQ11      : 5;            /*!< [29..25] 12th conversion in regular sequence                              */
            uint32_t            : 2;
    } RSQ1_b;
  } ;

  union {
    __IO uint32_t RSQ2;                        /*!< (@ 0x00000034) regular sequence register 2                                */

    struct {
      __IO uint32_t RSQ0       : 5;            /*!< [4..0] 1st conversion in regular sequence                                 */
      __IO uint32_t RSQ1       : 5;            /*!< [9..5] 2nd conversion in regular sequence                                 */
      __IO uint32_t RSQ2       : 5;            /*!< [14..10] 3rd conversion in regular sequence                               */
      __IO uint32_t RSQ3       : 5;            /*!< [19..15] 4th conversion in regular sequence                               */
      __IO uint32_t RSQ4       : 5;            /*!< [24..20] 5th conversion in regular sequence                               */
      __IO uint32_t RSQ5       : 5;            /*!< [29..25] 6th conversion in regular sequence                               */
            uint32_t            : 2;
    } RSQ2_b;
  } ;

  union {
    __IO uint32_t ISQ;                         /*!< (@ 0x00000038) Inserted sequence register                                 */

    struct {
      __IO uint32_t ISQ0       : 5;            /*!< [4..0] 1st conversion in inserted sequence                                */
      __IO uint32_t ISQ1       : 5;            /*!< [9..5] 2nd conversion in inserted sequence                                */
      __IO uint32_t ISQ2       : 5;            /*!< [14..10] 3rd conversion in inserted sequence                              */
      __IO uint32_t ISQ3       : 5;            /*!< [19..15] 4th conversion in inserted sequence                              */
      __IO uint32_t IL         : 2;            /*!< [21..20] Inserted channel group length                                    */
            uint32_t            : 10;
    } ISQ_b;
  } ;

  union {
    __I  uint32_t IDATA0;                      /*!< (@ 0x0000003C) Inserted data register 0                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA0_b;
  } ;

  union {
    __I  uint32_t IDATA1;                      /*!< (@ 0x00000040) Inserted data register 1                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA1_b;
  } ;

  union {
    __I  uint32_t IDATA2;                      /*!< (@ 0x00000044) Inserted data register 2                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA2_b;
  } ;

  union {
    __I  uint32_t IDATA3;                      /*!< (@ 0x00000048) Inserted data register 3                                   */

    struct {
      __I  uint32_t IDATAn     : 16;           /*!< [15..0] Inserted number n conversion data                                 */
            uint32_t            : 16;
    } IDATA3_b;
  } ;

  union {
    __I  uint32_t RDATA;                       /*!< (@ 0x0000004C) regular data register                                      */

    struct {
      __I  uint32_t RDATA      : 16;           /*!< [15..0] Regular channel data                                              */
            uint32_t            : 16;
    } RDATA_b;
  } ;
} ADC1_Type;                                    /*!< Size = 80 (0x50)                                                          */



/* =========================================================================================================================== */
/* ================                                           AFIO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Alternate-function I/Os (AFIO)
  */

typedef struct {                                /*!< (@ 0x40010000) AFIO Structure                                             */

  union {
    __IO uint32_t EC;                          /*!< (@ 0x00000000) Event control register                                     */

    struct {
      __IO uint32_t PIN        : 4;            /*!< [3..0] Event output pin selection                                         */
      __IO uint32_t PORT       : 3;            /*!< [6..4] Event output port selection                                        */
      __IO uint32_t EOE        : 1;            /*!< [7..7] Event output enable                                                */
            uint32_t            : 24;
    } EC_b;
  } ;

  union {
    __IO uint32_t PCF0;                        /*!< (@ 0x00000004) AFIO port configuration register 0                         */

    struct {
      __IO uint32_t SPI0_REMAP : 1;            /*!< [0..0] SPI0 remapping                                                     */
      __IO uint32_t I2C0_REMAP : 1;            /*!< [1..1] I2C0 remapping                                                     */
      __IO uint32_t USART0_REMAP : 1;          /*!< [2..2] USART0 remapping                                                   */
      __IO uint32_t USART1_REMAP : 1;          /*!< [3..3] USART1 remapping                                                   */
      __IO uint32_t USART2_REMAP : 2;          /*!< [5..4] USART2 remapping                                                   */
      __IO uint32_t TIMER0_REMAP : 2;          /*!< [7..6] TIMER0 remapping                                                   */
      __IO uint32_t TIMER1_REMAP : 2;          /*!< [9..8] TIMER1 remapping                                                   */
      __IO uint32_t TIMER2_REMAP : 2;          /*!< [11..10] TIMER2 remapping                                                 */
      __IO uint32_t TIMER3_REMAP : 1;          /*!< [12..12] TIMER3 remapping                                                 */
      __IO uint32_t CAN0_REMAP : 2;            /*!< [14..13] CAN0 alternate interface remapping                               */
      __IO uint32_t PD01_REMAP : 1;            /*!< [15..15] Port D0/Port D1 mapping on OSC_IN/OSC_OUT                        */
      __IO uint32_t TIMER4CH3_IREMAP : 1;      /*!< [16..16] TIMER4 channel3 internal remapping                               */
            uint32_t            : 5;
      __IO uint32_t CAN1_REMAP : 1;            /*!< [22..22] CAN1 I/O remapping                                               */
            uint32_t            : 1;
      __IO uint32_t SWJ_CFG    : 3;            /*!< [26..24] Serial wire JTAG configuration                                   */
            uint32_t            : 1;
      __IO uint32_t SPI2_REMAP : 1;            /*!< [28..28] SPI2/I2S2 remapping                                              */
      __IO uint32_t TIMER1ITI1_REMAP : 1;      /*!< [29..29] TIMER1 internal trigger 1 remapping                              */
            uint32_t            : 2;
    } PCF0_b;
  } ;

  union {
    __IO uint32_t EXTISS0;                     /*!< (@ 0x00000008) EXTI sources selection register 0                          */

    struct {
      __IO uint32_t EXTI0_SS   : 4;            /*!< [3..0] EXTI 0 sources selection                                           */
      __IO uint32_t EXTI1_SS   : 4;            /*!< [7..4] EXTI 1 sources selection                                           */
      __IO uint32_t EXTI2_SS   : 4;            /*!< [11..8] EXTI 2 sources selection                                          */
      __IO uint32_t EXTI3_SS   : 4;            /*!< [15..12] EXTI 3 sources selection                                         */
            uint32_t            : 16;
    } EXTISS0_b;
  } ;

  union {
    __IO uint32_t EXTISS1;                     /*!< (@ 0x0000000C) EXTI sources selection register 1                          */

    struct {
      __IO uint32_t EXTI4_SS   : 4;            /*!< [3..0] EXTI 4 sources selection                                           */
      __IO uint32_t EXTI5_SS   : 4;            /*!< [7..4] EXTI 5 sources selection                                           */
      __IO uint32_t EXTI6_SS   : 4;            /*!< [11..8] EXTI 6 sources selection                                          */
      __IO uint32_t EXTI7_SS   : 4;            /*!< [15..12] EXTI 7 sources selection                                         */
            uint32_t            : 16;
    } EXTISS1_b;
  } ;

  union {
    __IO uint32_t EXTISS2;                     /*!< (@ 0x00000010) EXTI sources selection register 2                          */

    struct {
      __IO uint32_t EXTI8_SS   : 4;            /*!< [3..0] EXTI 8 sources selection                                           */
      __IO uint32_t EXTI9_SS   : 4;            /*!< [7..4] EXTI 9 sources selection                                           */
      __IO uint32_t EXTI10_SS  : 4;            /*!< [11..8] EXTI 10 sources selection                                         */
      __IO uint32_t EXTI11_SS  : 4;            /*!< [15..12] EXTI 11 sources selection                                        */
            uint32_t            : 16;
    } EXTISS2_b;
  } ;

  union {
    __IO uint32_t EXTISS3;                     /*!< (@ 0x00000014) EXTI sources selection register 3                          */

    struct {
      __IO uint32_t EXTI12_SS  : 4;            /*!< [3..0] EXTI 12 sources selection                                          */
      __IO uint32_t EXTI13_SS  : 4;            /*!< [7..4] EXTI 13 sources selection                                          */
      __IO uint32_t EXTI14_SS  : 4;            /*!< [11..8] EXTI 14 sources selection                                         */
      __IO uint32_t EXTI15_SS  : 4;            /*!< [15..12] EXTI 15 sources selection                                        */
            uint32_t            : 16;
    } EXTISS3_b;
  } ;
  __I  uint32_t  RESERVED;

  union {
    __IO uint32_t PCF1;                        /*!< (@ 0x0000001C) AFIO port configuration register 1                         */

    struct {
            uint32_t            : 10;
      __IO uint32_t EXMC_NADV  : 1;            /*!< [10..10] EXMC_NADV connect/disconnect                                     */
            uint32_t            : 21;
    } PCF1_b;
  } ;
} AFIO_Type;                                    /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                            BKP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Backup registers (BKP)
  */

typedef struct {                                /*!< (@ 0x40006C00) BKP Structure                                              */
  __I  uint16_t  RESERVED[2];

  union {
    __IO uint16_t DATA0;                       /*!< (@ 0x00000004) Backup data register 0                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA0_b;
  } ;
  __I  uint16_t  RESERVED1;

  union {
    __IO uint16_t DATA1;                       /*!< (@ 0x00000008) Backup data register 1                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA1_b;
  } ;
  __I  uint16_t  RESERVED2;

  union {
    __IO uint16_t DATA2;                       /*!< (@ 0x0000000C) Backup data register 2                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA2_b;
  } ;
  __I  uint16_t  RESERVED3;

  union {
    __IO uint16_t DATA3;                       /*!< (@ 0x00000010) Backup data register 3                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA3_b;
  } ;
  __I  uint16_t  RESERVED4;

  union {
    __IO uint16_t DATA4;                       /*!< (@ 0x00000014) Backup data register 4                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA4_b;
  } ;
  __I  uint16_t  RESERVED5;

  union {
    __IO uint16_t DATA5;                       /*!< (@ 0x00000018) Backup data register 5                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA5_b;
  } ;
  __I  uint16_t  RESERVED6;

  union {
    __IO uint16_t DATA6;                       /*!< (@ 0x0000001C) Backup data register 6                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA6_b;
  } ;
  __I  uint16_t  RESERVED7;

  union {
    __IO uint16_t DATA7;                       /*!< (@ 0x00000020) Backup data register 7                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA7_b;
  } ;
  __I  uint16_t  RESERVED8;

  union {
    __IO uint16_t DATA8;                       /*!< (@ 0x00000024) Backup data register 8                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA8_b;
  } ;
  __I  uint16_t  RESERVED9;

  union {
    __IO uint16_t DATA9;                       /*!< (@ 0x00000028) Backup data register 9                                     */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA9_b;
  } ;
  __I  uint16_t  RESERVED10;

  union {
    __IO uint16_t OCTL;                        /*!< (@ 0x0000002C) RTC signal output control register                         */

    struct {
      __IO uint16_t RCCV       : 7;            /*!< [6..0] RTC clock calibration value                                        */
      __IO uint16_t COEN       : 1;            /*!< [7..7] RTC clock calibration output enable                                */
      __IO uint16_t ASOEN      : 1;            /*!< [8..8] RTC alarm or second signal output enable                           */
      __IO uint16_t ROSEL      : 1;            /*!< [9..9] RTC output selection                                               */
            uint16_t            : 6;
    } OCTL_b;
  } ;
  __I  uint16_t  RESERVED11;

  union {
    __IO uint16_t TPCTL;                       /*!< (@ 0x00000030) Tamper pin control register                                */

    struct {
      __IO uint16_t TPEN       : 1;            /*!< [0..0] TAMPER detection enable                                            */
      __IO uint16_t TPAL       : 1;            /*!< [1..1] TAMPER pin active level                                            */
            uint16_t            : 14;
    } TPCTL_b;
  } ;
  __I  uint16_t  RESERVED12;

  union {
    __IO uint16_t TPCS;                        /*!< (@ 0x00000034) Tamper control and status register                         */

    struct {
      __IO uint16_t TER        : 1;            /*!< [0..0] Tamper event reset                                                 */
      __IO uint16_t TIR        : 1;            /*!< [1..1] Tamper interrupt reset                                             */
      __IO uint16_t TPIE       : 1;            /*!< [2..2] Tamper interrupt enable                                            */
            uint16_t            : 5;
      __IO uint16_t TEF        : 1;            /*!< [8..8] Tamper event flag                                                  */
      __IO uint16_t TIF        : 1;            /*!< [9..9] Tamper interrupt flag                                              */
            uint16_t            : 6;
    } TPCS_b;
  } ;
  __I  uint16_t  RESERVED13[5];

  union {
    __IO uint16_t DATA10;                      /*!< (@ 0x00000040) Backup data register 10                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA10_b;
  } ;
  __I  uint16_t  RESERVED14;

  union {
    __IO uint16_t DATA11;                      /*!< (@ 0x00000044) Backup data register 11                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA11_b;
  } ;
  __I  uint16_t  RESERVED15;

  union {
    __IO uint16_t DATA12;                      /*!< (@ 0x00000048) Backup data register 12                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA12_b;
  } ;
  __I  uint16_t  RESERVED16;

  union {
    __IO uint16_t DATA13;                      /*!< (@ 0x0000004C) Backup data register 13                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA13_b;
  } ;
  __I  uint16_t  RESERVED17;

  union {
    __IO uint16_t DATA14;                      /*!< (@ 0x00000050) Backup data register 14                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA14_b;
  } ;
  __I  uint16_t  RESERVED18;

  union {
    __IO uint16_t DATA15;                      /*!< (@ 0x00000054) Backup data register 15                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA15_b;
  } ;
  __I  uint16_t  RESERVED19;

  union {
    __IO uint16_t DATA16;                      /*!< (@ 0x00000058) Backup data register 16                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA16_b;
  } ;
  __I  uint16_t  RESERVED20;

  union {
    __IO uint16_t DATA17;                      /*!< (@ 0x0000005C) Backup data register 17                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA17_b;
  } ;
  __I  uint16_t  RESERVED21;

  union {
    __IO uint16_t DATA18;                      /*!< (@ 0x00000060) Backup data register 18                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA18_b;
  } ;
  __I  uint16_t  RESERVED22;

  union {
    __IO uint16_t DATA19;                      /*!< (@ 0x00000064) Backup data register 19                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA19_b;
  } ;
  __I  uint16_t  RESERVED23;

  union {
    __IO uint16_t DATA20;                      /*!< (@ 0x00000068) Backup data register 20                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA20_b;
  } ;
  __I  uint16_t  RESERVED24;

  union {
    __IO uint16_t DATA21;                      /*!< (@ 0x0000006C) Backup data register 21                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA21_b;
  } ;
  __I  uint16_t  RESERVED25;

  union {
    __IO uint16_t DATA22;                      /*!< (@ 0x00000070) Backup data register 22                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA22_b;
  } ;
  __I  uint16_t  RESERVED26;

  union {
    __IO uint16_t DATA23;                      /*!< (@ 0x00000074) Backup data register 23                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA23_b;
  } ;
  __I  uint16_t  RESERVED27;

  union {
    __IO uint16_t DATA24;                      /*!< (@ 0x00000078) Backup data register 24                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA24_b;
  } ;
  __I  uint16_t  RESERVED28;

  union {
    __IO uint16_t DATA25;                      /*!< (@ 0x0000007C) Backup data register 25                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA25_b;
  } ;
  __I  uint16_t  RESERVED29;

  union {
    __IO uint16_t DATA26;                      /*!< (@ 0x00000080) Backup data register 26                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA26_b;
  } ;
  __I  uint16_t  RESERVED30;

  union {
    __IO uint16_t DATA27;                      /*!< (@ 0x00000084) Backup data register 27                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA27_b;
  } ;
  __I  uint16_t  RESERVED31;

  union {
    __IO uint16_t DATA28;                      /*!< (@ 0x00000088) Backup data register 28                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA28_b;
  } ;
  __I  uint16_t  RESERVED32;

  union {
    __IO uint16_t DATA29;                      /*!< (@ 0x0000008C) Backup data register 29                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA29_b;
  } ;
  __I  uint16_t  RESERVED33;

  union {
    __IO uint16_t DATA30;                      /*!< (@ 0x00000090) Backup data register 30                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA30_b;
  } ;
  __I  uint16_t  RESERVED34;

  union {
    __IO uint16_t DATA31;                      /*!< (@ 0x00000094) Backup data register 31                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA31_b;
  } ;
  __I  uint16_t  RESERVED35;

  union {
    __IO uint16_t DATA32;                      /*!< (@ 0x00000098) Backup data register 32                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA32_b;
  } ;
  __I  uint16_t  RESERVED36;

  union {
    __IO uint16_t DATA33;                      /*!< (@ 0x0000009C) Backup data register 33                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA33_b;
  } ;
  __I  uint16_t  RESERVED37;

  union {
    __IO uint16_t DATA34;                      /*!< (@ 0x000000A0) Backup data register 34                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA34_b;
  } ;
  __I  uint16_t  RESERVED38;

  union {
    __IO uint16_t DATA35;                      /*!< (@ 0x000000A4) Backup data register 35                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA35_b;
  } ;
  __I  uint16_t  RESERVED39;

  union {
    __IO uint16_t DATA36;                      /*!< (@ 0x000000A8) Backup data register 36                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA36_b;
  } ;
  __I  uint16_t  RESERVED40;

  union {
    __IO uint16_t DATA37;                      /*!< (@ 0x000000AC) Backup data register 37                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA37_b;
  } ;
  __I  uint16_t  RESERVED41;

  union {
    __IO uint16_t DATA38;                      /*!< (@ 0x000000B0) Backup data register 38                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA38_b;
  } ;
  __I  uint16_t  RESERVED42;

  union {
    __IO uint16_t DATA39;                      /*!< (@ 0x000000B4) Backup data register 39                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA39_b;
  } ;
  __I  uint16_t  RESERVED43;

  union {
    __IO uint16_t DATA40;                      /*!< (@ 0x000000B8) Backup data register 40                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA40_b;
  } ;
  __I  uint16_t  RESERVED44;

  union {
    __IO uint16_t DATA41;                      /*!< (@ 0x000000BC) Backup data register 41                                    */

    struct {
      __IO uint16_t DATA       : 16;           /*!< [15..0] Backup data                                                       */
    } DATA41_b;
  } ;
} BKP_Type;                                     /*!< Size = 190 (0xbe)                                                         */



/* =========================================================================================================================== */
/* ================                                           CAN0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Controller area network (CAN0)
  */

typedef struct {                                /*!< (@ 0x40006400) CAN0 Structure                                             */

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000000) Control register                                           */

    struct {
      __IO uint32_t IWMOD      : 1;            /*!< [0..0] Initial working mode                                               */
      __IO uint32_t SLPWMOD    : 1;            /*!< [1..1] Sleep working mode                                                 */
      __IO uint32_t TFO        : 1;            /*!< [2..2] Transmit FIFO order                                                */
      __IO uint32_t RFOD       : 1;            /*!< [3..3] Receive FIFO overwrite disable                                     */
      __IO uint32_t ARD        : 1;            /*!< [4..4] Automatic retransmission disable                                   */
      __IO uint32_t AWU        : 1;            /*!< [5..5] Automatic wakeup                                                   */
      __IO uint32_t ABOR       : 1;            /*!< [6..6] Automatic bus-off recovery                                         */
      __IO uint32_t TTC        : 1;            /*!< [7..7] Time-triggered communication                                       */
            uint32_t            : 7;
      __IO uint32_t SWRST      : 1;            /*!< [15..15] Software reset                                                   */
      __IO uint32_t DFZ        : 1;            /*!< [16..16] Debug freeze                                                     */
            uint32_t            : 15;
    } CTL_b;
  } ;

  union {
    __IO uint32_t STAT;                        /*!< (@ 0x00000004) Status register                                            */

    struct {
      __I  uint32_t IWS        : 1;            /*!< [0..0] Initial working state                                              */
      __I  uint32_t SLPWS      : 1;            /*!< [1..1] Sleep working state                                                */
      __IO uint32_t ERRIF      : 1;            /*!< [2..2] Error interrupt flag                                               */
      __IO uint32_t WUIF       : 1;            /*!< [3..3] Status change interrupt flag of wakeup  from sleep working
                                                     mode                                                                      */
      __IO uint32_t SLPIF      : 1;            /*!< [4..4] Status change interrupt flag of sleep  working mode entering       */
            uint32_t            : 3;
      __I  uint32_t TS         : 1;            /*!< [8..8] Transmitting state                                                 */
      __I  uint32_t RS         : 1;            /*!< [9..9] Receiving state                                                    */
      __I  uint32_t LASTRX     : 1;            /*!< [10..10] Last sample value of RX pin                                      */
      __I  uint32_t RXL        : 1;            /*!< [11..11] RX level                                                         */
            uint32_t            : 20;
    } STAT_b;
  } ;

  union {
    __IO uint32_t TSTAT;                       /*!< (@ 0x00000008) Transmit status register                                   */

    struct {
      __IO uint32_t MTF0       : 1;            /*!< [0..0] Mailbox 0 transmit finished                                        */
      __IO uint32_t MTFNERR0   : 1;            /*!< [1..1] Mailbox 0 transmit finished and no error                           */
      __IO uint32_t MAL0       : 1;            /*!< [2..2] Mailbox 0 arbitration lost                                         */
      __IO uint32_t MTE0       : 1;            /*!< [3..3] Mailbox 0 transmit error                                           */
            uint32_t            : 3;
      __IO uint32_t MST0       : 1;            /*!< [7..7] Mailbox 0 stop transmitting                                        */
      __IO uint32_t MTF1       : 1;            /*!< [8..8] Mailbox 1 transmit finished                                        */
      __IO uint32_t MTFNERR1   : 1;            /*!< [9..9] Mailbox 1 transmit finished and no error                           */
      __IO uint32_t MAL1       : 1;            /*!< [10..10] Mailbox 1 arbitration lost                                       */
      __IO uint32_t MTE1       : 1;            /*!< [11..11] Mailbox 1 transmit error                                         */
            uint32_t            : 3;
      __IO uint32_t MST1       : 1;            /*!< [15..15] Mailbox 1 stop transmitting                                      */
      __IO uint32_t MTF2       : 1;            /*!< [16..16] Mailbox 2 transmit finished                                      */
      __IO uint32_t MTFNERR2   : 1;            /*!< [17..17] Mailbox 2 transmit finished and no error                         */
      __IO uint32_t MAL2       : 1;            /*!< [18..18] Mailbox 2 arbitration lost                                       */
      __IO uint32_t MTE2       : 1;            /*!< [19..19] Mailbox 2 transmit error                                         */
            uint32_t            : 3;
      __IO uint32_t MST2       : 1;            /*!< [23..23] Mailbox 2 stop transmitting                                      */
      __I  uint32_t NUM        : 2;            /*!< [25..24] number of the transmit FIFO mailbox in  which the frame
                                                     will be transmitted if at least one mailbox is empty                      */
      __I  uint32_t TME0       : 1;            /*!< [26..26] Transmit mailbox 0 empty                                         */
      __I  uint32_t TME1       : 1;            /*!< [27..27] Transmit mailbox 1 empty                                         */
      __I  uint32_t TME2       : 1;            /*!< [28..28] Transmit mailbox 2 empty                                         */
      __I  uint32_t TMLS0      : 1;            /*!< [29..29] Transmit mailbox 0 last sending  in transmit FIFO                */
      __I  uint32_t TMLS1      : 1;            /*!< [30..30] Transmit mailbox 1 last sending  in transmit FIFO                */
      __I  uint32_t TMLS2      : 1;            /*!< [31..31] Transmit mailbox 2 last sending  in transmit FIFO                */
    } TSTAT_b;
  } ;

  union {
    __IO uint32_t RFIFO0;                      /*!< (@ 0x0000000C) Receive message FIFO0 register                             */

    struct {
      __I  uint32_t RFL0       : 2;            /*!< [1..0] Receive FIFO0 length                                               */
            uint32_t            : 1;
      __IO uint32_t RFF0       : 1;            /*!< [3..3] Receive FIFO0 full                                                 */
      __IO uint32_t RFO0       : 1;            /*!< [4..4] Receive FIFO0 overfull                                             */
      __IO uint32_t RFD0       : 1;            /*!< [5..5] Receive FIFO0 dequeue                                              */
            uint32_t            : 26;
    } RFIFO0_b;
  } ;

  union {
    __IO uint32_t RFIFO1;                      /*!< (@ 0x00000010) Receive message FIFO1 register                             */

    struct {
      __I  uint32_t RFL1       : 2;            /*!< [1..0] Receive FIFO1 length                                               */
            uint32_t            : 1;
      __IO uint32_t RFF1       : 1;            /*!< [3..3] Receive FIFO1 full                                                 */
      __IO uint32_t RFO1       : 1;            /*!< [4..4] Receive FIFO1 overfull                                             */
      __IO uint32_t RFD1       : 1;            /*!< [5..5] Receive FIFO1 dequeue                                              */
            uint32_t            : 26;
    } RFIFO1_b;
  } ;

  union {
    __IO uint32_t INTEN;                       /*!< (@ 0x00000014) Interrupt enable register                                  */

    struct {
      __IO uint32_t TMEIE      : 1;            /*!< [0..0] Transmit mailbox empty interrupt enable                            */
      __IO uint32_t RFNEIE0    : 1;            /*!< [1..1] Receive FIFO0 not empty interrupt enable                           */
      __IO uint32_t RFFIE0     : 1;            /*!< [2..2] Receive FIFO0 full interrupt enable                                */
      __IO uint32_t RFOIE0     : 1;            /*!< [3..3] Receive FIFO0 overfull interrupt enable                            */
      __IO uint32_t RFNEIE1    : 1;            /*!< [4..4] Receive FIFO1 not empty interrupt enable                           */
      __IO uint32_t RFFIE1     : 1;            /*!< [5..5] Receive FIFO1 full interrupt enable                                */
      __IO uint32_t RFOIE1     : 1;            /*!< [6..6] Receive FIFO1 overfull interrupt enable                            */
            uint32_t            : 1;
      __IO uint32_t WERRIE     : 1;            /*!< [8..8] Warning error interrupt enable                                     */
      __IO uint32_t PERRIE     : 1;            /*!< [9..9] Passive error interrupt enable                                     */
      __IO uint32_t BOIE       : 1;            /*!< [10..10] Bus-off interrupt enable                                         */
      __IO uint32_t ERRNIE     : 1;            /*!< [11..11] Error number interrupt enable                                    */
            uint32_t            : 3;
      __IO uint32_t ERRIE      : 1;            /*!< [15..15] Error interrupt enable                                           */
      __IO uint32_t WIE        : 1;            /*!< [16..16] Wakeup interrupt enable                                          */
      __IO uint32_t SLPWIE     : 1;            /*!< [17..17] Sleep working interrupt enable                                   */
            uint32_t            : 14;
    } INTEN_b;
  } ;

  union {
    __IO uint32_t ERR;                         /*!< (@ 0x00000018) Error register                                             */

    struct {
      __I  uint32_t WERR       : 1;            /*!< [0..0] Warning error                                                      */
      __I  uint32_t PERR       : 1;            /*!< [1..1] Passive error                                                      */
      __I  uint32_t BOERR      : 1;            /*!< [2..2] Bus-off error                                                      */
            uint32_t            : 1;
      __IO uint32_t ERRN       : 3;            /*!< [6..4] Error number                                                       */
            uint32_t            : 9;
      __I  uint32_t TECNT      : 8;            /*!< [23..16] Transmit Error Count defined  by the CAN standard                */
      __I  uint32_t RECNT      : 8;            /*!< [31..24] Receive Error Count defined  by the CAN standard                 */
    } ERR_b;
  } ;

  union {
    __IO uint32_t BT;                          /*!< (@ 0x0000001C) Bit timing register                                        */

    struct {
      __IO uint32_t BAUDPSC    : 10;           /*!< [9..0] Baud rate prescaler                                                */
            uint32_t            : 6;
      __IO uint32_t BS1        : 4;            /*!< [19..16] Bit segment 1                                                    */
      __IO uint32_t BS2        : 3;            /*!< [22..20] Bit segment 2                                                    */
            uint32_t            : 1;
      __IO uint32_t SJW        : 2;            /*!< [25..24] Resynchronization jump width                                     */
            uint32_t            : 4;
      __IO uint32_t LCMOD      : 1;            /*!< [30..30] Loopback communication mode                                      */
      __IO uint32_t SCMOD      : 1;            /*!< [31..31] Silent communication mode                                        */
    } BT_b;
  } ;
  __I  uint32_t  RESERVED[88];

  union {
    __IO uint32_t TMI0;                        /*!< (@ 0x00000180) Transmit mailbox identifier register 0                     */

    struct {
      __IO uint32_t TEN        : 1;            /*!< [0..0] Transmit enable                                                    */
      __IO uint32_t FT         : 1;            /*!< [1..1] Frame type                                                         */
      __IO uint32_t FF         : 1;            /*!< [2..2] Frame format                                                       */
      __IO uint32_t EFID       : 18;           /*!< [20..3] The frame identifier                                              */
      __IO uint32_t SFID_EFID  : 11;           /*!< [31..21] The frame identifier                                             */
    } TMI0_b;
  } ;

  union {
    __IO uint32_t TMP0;                        /*!< (@ 0x00000184) Transmit mailbox property register 0                       */

    struct {
      __IO uint32_t DLENC      : 4;            /*!< [3..0] Data length code                                                   */
            uint32_t            : 4;
      __IO uint32_t TSEN       : 1;            /*!< [8..8] Time stamp enable                                                  */
            uint32_t            : 7;
      __IO uint32_t TS         : 16;           /*!< [31..16] Time stamp                                                       */
    } TMP0_b;
  } ;

  union {
    __IO uint32_t TMDATA00;                    /*!< (@ 0x00000188) Transmit mailbox data0 register                            */

    struct {
      __IO uint32_t DB0        : 8;            /*!< [7..0] Data byte 0                                                        */
      __IO uint32_t DB1        : 8;            /*!< [15..8] Data byte 1                                                       */
      __IO uint32_t DB2        : 8;            /*!< [23..16] Data byte 2                                                      */
      __IO uint32_t DB3        : 8;            /*!< [31..24] Data byte 3                                                      */
    } TMDATA00_b;
  } ;

  union {
    __IO uint32_t TMDATA10;                    /*!< (@ 0x0000018C) Transmit mailbox data1 register                            */

    struct {
      __IO uint32_t DB4        : 8;            /*!< [7..0] Data byte 4                                                        */
      __IO uint32_t DB5        : 8;            /*!< [15..8] Data byte 5                                                       */
      __IO uint32_t DB6        : 8;            /*!< [23..16] Data byte 6                                                      */
      __IO uint32_t DB7        : 8;            /*!< [31..24] Data byte 7                                                      */
    } TMDATA10_b;
  } ;

  union {
    __IO uint32_t TMI1;                        /*!< (@ 0x00000190) Transmit mailbox identifier register 1                     */

    struct {
      __IO uint32_t TEN        : 1;            /*!< [0..0] Transmit enable                                                    */
      __IO uint32_t FT         : 1;            /*!< [1..1] Frame type                                                         */
      __IO uint32_t FF         : 1;            /*!< [2..2] Frame format                                                       */
      __IO uint32_t EFID       : 18;           /*!< [20..3] The frame identifier                                              */
      __IO uint32_t SFID_EFID  : 11;           /*!< [31..21] The frame identifier                                             */
    } TMI1_b;
  } ;

  union {
    __IO uint32_t TMP1;                        /*!< (@ 0x00000194) Transmit mailbox property register 1                       */

    struct {
      __IO uint32_t DLENC      : 4;            /*!< [3..0] Data length code                                                   */
            uint32_t            : 4;
      __IO uint32_t TSEN       : 1;            /*!< [8..8] Time stamp enable                                                  */
            uint32_t            : 7;
      __IO uint32_t TS         : 16;           /*!< [31..16] Time stamp                                                       */
    } TMP1_b;
  } ;

  union {
    __IO uint32_t TMDATA01;                    /*!< (@ 0x00000198) Transmit mailbox data0 register                            */

    struct {
      __IO uint32_t DB0        : 8;            /*!< [7..0] Data byte 0                                                        */
      __IO uint32_t DB1        : 8;            /*!< [15..8] Data byte 1                                                       */
      __IO uint32_t DB2        : 8;            /*!< [23..16] Data byte 2                                                      */
      __IO uint32_t DB3        : 8;            /*!< [31..24] Data byte 3                                                      */
    } TMDATA01_b;
  } ;

  union {
    __IO uint32_t TMDATA11;                    /*!< (@ 0x0000019C) Transmit mailbox data1 register                            */

    struct {
      __IO uint32_t DB4        : 8;            /*!< [7..0] Data byte 4                                                        */
      __IO uint32_t DB5        : 8;            /*!< [15..8] Data byte 5                                                       */
      __IO uint32_t DB6        : 8;            /*!< [23..16] Data byte 6                                                      */
      __IO uint32_t DB7        : 8;            /*!< [31..24] Data byte 7                                                      */
    } TMDATA11_b;
  } ;

  union {
    __IO uint32_t TMI2;                        /*!< (@ 0x000001A0) Transmit mailbox identifier register 2                     */

    struct {
      __IO uint32_t TEN        : 1;            /*!< [0..0] Transmit enable                                                    */
      __IO uint32_t FT         : 1;            /*!< [1..1] Frame type                                                         */
      __IO uint32_t FF         : 1;            /*!< [2..2] Frame format                                                       */
      __IO uint32_t EFID       : 18;           /*!< [20..3] The frame identifier                                              */
      __IO uint32_t SFID_EFID  : 11;           /*!< [31..21] The frame identifier                                             */
    } TMI2_b;
  } ;

  union {
    __IO uint32_t TMP2;                        /*!< (@ 0x000001A4) Transmit mailbox property register 2                       */

    struct {
      __IO uint32_t DLENC      : 4;            /*!< [3..0] Data length code                                                   */
            uint32_t            : 4;
      __IO uint32_t TSEN       : 1;            /*!< [8..8] Time stamp enable                                                  */
            uint32_t            : 7;
      __IO uint32_t TS         : 16;           /*!< [31..16] Time stamp                                                       */
    } TMP2_b;
  } ;

  union {
    __IO uint32_t TMDATA02;                    /*!< (@ 0x000001A8) Transmit mailbox data0 register                            */

    struct {
      __IO uint32_t DB0        : 8;            /*!< [7..0] Data byte 0                                                        */
      __IO uint32_t DB1        : 8;            /*!< [15..8] Data byte 1                                                       */
      __IO uint32_t DB2        : 8;            /*!< [23..16] Data byte 2                                                      */
      __IO uint32_t DB3        : 8;            /*!< [31..24] Data byte 3                                                      */
    } TMDATA02_b;
  } ;

  union {
    __IO uint32_t TMDATA12;                    /*!< (@ 0x000001AC) Transmit mailbox data1 register                            */

    struct {
      __IO uint32_t DB4        : 8;            /*!< [7..0] Data byte 4                                                        */
      __IO uint32_t DB5        : 8;            /*!< [15..8] Data byte 5                                                       */
      __IO uint32_t DB6        : 8;            /*!< [23..16] Data byte 6                                                      */
      __IO uint32_t DB7        : 8;            /*!< [31..24] Data byte 7                                                      */
    } TMDATA12_b;
  } ;

  union {
    __I  uint32_t RFIFOMI0;                    /*!< (@ 0x000001B0) Receive FIFO mailbox identifier register                   */

    struct {
            uint32_t            : 1;
      __I  uint32_t FT         : 1;            /*!< [1..1] Frame type                                                         */
      __I  uint32_t FF         : 1;            /*!< [2..2] Frame format                                                       */
      __I  uint32_t EFID       : 18;           /*!< [20..3] The frame identifier                                              */
      __I  uint32_t SFID_EFID  : 11;           /*!< [31..21] The frame identifier                                             */
    } RFIFOMI0_b;
  } ;

  union {
    __I  uint32_t RFIFOMP0;                    /*!< (@ 0x000001B4) Receive FIFO0 mailbox property register                    */

    struct {
      __I  uint32_t DLENC      : 4;            /*!< [3..0] Data length code                                                   */
            uint32_t            : 4;
      __I  uint32_t FI         : 8;            /*!< [15..8] Filtering index                                                   */
      __I  uint32_t TS         : 16;           /*!< [31..16] Time stamp                                                       */
    } RFIFOMP0_b;
  } ;

  union {
    __I  uint32_t RFIFOMDATA00;                /*!< (@ 0x000001B8) Receive FIFO0 mailbox data0 register                       */

    struct {
      __I  uint32_t DB0        : 8;            /*!< [7..0] Data byte 0                                                        */
      __I  uint32_t DB1        : 8;            /*!< [15..8] Data byte 1                                                       */
      __I  uint32_t DB2        : 8;            /*!< [23..16] Data byte 2                                                      */
      __I  uint32_t DB3        : 8;            /*!< [31..24] Data byte 3                                                      */
    } RFIFOMDATA00_b;
  } ;

  union {
    __I  uint32_t RFIFOMDATA10;                /*!< (@ 0x000001BC) Receive FIFO0 mailbox data1 register                       */

    struct {
      __I  uint32_t DB4        : 8;            /*!< [7..0] Data byte 4                                                        */
      __I  uint32_t DB5        : 8;            /*!< [15..8] Data byte 5                                                       */
      __I  uint32_t DB6        : 8;            /*!< [23..16] Data byte 6                                                      */
      __I  uint32_t DB7        : 8;            /*!< [31..24] Data byte 7                                                      */
    } RFIFOMDATA10_b;
  } ;

  union {
    __I  uint32_t RFIFOMI1;                    /*!< (@ 0x000001C0) Receive FIFO1 mailbox identifier register                  */

    struct {
            uint32_t            : 1;
      __I  uint32_t FT         : 1;            /*!< [1..1] Frame type                                                         */
      __I  uint32_t FF         : 1;            /*!< [2..2] Frame format                                                       */
      __I  uint32_t EFID       : 18;           /*!< [20..3] The frame identifier                                              */
      __I  uint32_t SFID_EFID  : 11;           /*!< [31..21] The frame identifier                                             */
    } RFIFOMI1_b;
  } ;

  union {
    __I  uint32_t RFIFOMP1;                    /*!< (@ 0x000001C4) Receive FIFO1 mailbox property register                    */

    struct {
      __I  uint32_t DLENC      : 4;            /*!< [3..0] Data length code                                                   */
            uint32_t            : 4;
      __I  uint32_t FI         : 8;            /*!< [15..8] Filtering index                                                   */
      __I  uint32_t TS         : 16;           /*!< [31..16] Time stamp                                                       */
    } RFIFOMP1_b;
  } ;

  union {
    __I  uint32_t RFIFOMDATA01;                /*!< (@ 0x000001C8) Receive FIFO1 mailbox data0 register                       */

    struct {
      __I  uint32_t DB0        : 8;            /*!< [7..0] Data byte 0                                                        */
      __I  uint32_t DB1        : 8;            /*!< [15..8] Data byte 1                                                       */
      __I  uint32_t DB2        : 8;            /*!< [23..16] Data byte 2                                                      */
      __I  uint32_t DB3        : 8;            /*!< [31..24] Data byte 3                                                      */
    } RFIFOMDATA01_b;
  } ;

  union {
    __I  uint32_t RFIFOMDATA11;                /*!< (@ 0x000001CC) Receive FIFO1 mailbox data1 register                       */

    struct {
      __I  uint32_t DB4        : 8;            /*!< [7..0] Data byte 4                                                        */
      __I  uint32_t DB5        : 8;            /*!< [15..8] Data byte 5                                                       */
      __I  uint32_t DB6        : 8;            /*!< [23..16] Data byte 6                                                      */
      __I  uint32_t DB7        : 8;            /*!< [31..24] Data byte 7                                                      */
    } RFIFOMDATA11_b;
  } ;
  __I  uint32_t  RESERVED1[12];

  union {
    __IO uint32_t FCTL;                        /*!< (@ 0x00000200) Filter control register                                    */

    struct {
      __IO uint32_t FLD        : 1;            /*!< [0..0] Filter lock disable                                                */
            uint32_t            : 7;
      __IO uint32_t HBC1F      : 6;            /*!< [13..8] Header bank of CAN1 filter                                        */
            uint32_t            : 18;
    } FCTL_b;
  } ;

  union {
    __IO uint32_t FMCFG;                       /*!< (@ 0x00000204) Filter mode configuration register                         */

    struct {
      __IO uint32_t FMOD0      : 1;            /*!< [0..0] Filter mode                                                        */
      __IO uint32_t FMOD1      : 1;            /*!< [1..1] Filter mode                                                        */
      __IO uint32_t FMOD2      : 1;            /*!< [2..2] Filter mode                                                        */
      __IO uint32_t FMOD3      : 1;            /*!< [3..3] Filter mode                                                        */
      __IO uint32_t FMOD4      : 1;            /*!< [4..4] Filter mode                                                        */
      __IO uint32_t FMOD5      : 1;            /*!< [5..5] Filter mode                                                        */
      __IO uint32_t FMOD6      : 1;            /*!< [6..6] Filter mode                                                        */
      __IO uint32_t FMOD7      : 1;            /*!< [7..7] Filter mode                                                        */
      __IO uint32_t FMOD8      : 1;            /*!< [8..8] Filter mode                                                        */
      __IO uint32_t FMOD9      : 1;            /*!< [9..9] Filter mode                                                        */
      __IO uint32_t FMOD10     : 1;            /*!< [10..10] Filter mode                                                      */
      __IO uint32_t FMOD11     : 1;            /*!< [11..11] Filter mode                                                      */
      __IO uint32_t FMOD12     : 1;            /*!< [12..12] Filter mode                                                      */
      __IO uint32_t FMOD13     : 1;            /*!< [13..13] Filter mode                                                      */
      __IO uint32_t FMOD14     : 1;            /*!< [14..14] Filter mode                                                      */
      __IO uint32_t FMOD15     : 1;            /*!< [15..15] Filter mode                                                      */
      __IO uint32_t FMOD16     : 1;            /*!< [16..16] Filter mode                                                      */
      __IO uint32_t FMOD17     : 1;            /*!< [17..17] Filter mode                                                      */
      __IO uint32_t FMOD18     : 1;            /*!< [18..18] Filter mode                                                      */
      __IO uint32_t FMOD19     : 1;            /*!< [19..19] Filter mode                                                      */
      __IO uint32_t FMOD20     : 1;            /*!< [20..20] Filter mode                                                      */
      __IO uint32_t FMOD21     : 1;            /*!< [21..21] Filter mode                                                      */
      __IO uint32_t FMOD22     : 1;            /*!< [22..22] Filter mode                                                      */
      __IO uint32_t FMOD23     : 1;            /*!< [23..23] Filter mode                                                      */
      __IO uint32_t FMOD24     : 1;            /*!< [24..24] Filter mode                                                      */
      __IO uint32_t FMOD25     : 1;            /*!< [25..25] Filter mode                                                      */
      __IO uint32_t FMOD26     : 1;            /*!< [26..26] Filter mode                                                      */
      __IO uint32_t FMOD27     : 1;            /*!< [27..27] Filter mode                                                      */
            uint32_t            : 4;
    } FMCFG_b;
  } ;
  __I  uint32_t  RESERVED2;

  union {
    __IO uint32_t FSCFG;                       /*!< (@ 0x0000020C) Filter scale configuration register                        */

    struct {
      __IO uint32_t FS0        : 1;            /*!< [0..0] Filter scale configuration                                         */
      __IO uint32_t FS1        : 1;            /*!< [1..1] Filter scale configuration                                         */
      __IO uint32_t FS2        : 1;            /*!< [2..2] Filter scale configuration                                         */
      __IO uint32_t FS3        : 1;            /*!< [3..3] Filter scale configuration                                         */
      __IO uint32_t FS4        : 1;            /*!< [4..4] Filter scale configuration                                         */
      __IO uint32_t FS5        : 1;            /*!< [5..5] Filter scale configuration                                         */
      __IO uint32_t FS6        : 1;            /*!< [6..6] Filter scale configuration                                         */
      __IO uint32_t FS7        : 1;            /*!< [7..7] Filter scale configuration                                         */
      __IO uint32_t FS8        : 1;            /*!< [8..8] Filter scale configuration                                         */
      __IO uint32_t FS9        : 1;            /*!< [9..9] Filter scale configuration                                         */
      __IO uint32_t FS10       : 1;            /*!< [10..10] Filter scale configuration                                       */
      __IO uint32_t FS11       : 1;            /*!< [11..11] Filter scale configuration                                       */
      __IO uint32_t FS12       : 1;            /*!< [12..12] Filter scale configuration                                       */
      __IO uint32_t FS13       : 1;            /*!< [13..13] Filter scale configuration                                       */
      __IO uint32_t FS14       : 1;            /*!< [14..14] Filter scale configuration                                       */
      __IO uint32_t FS15       : 1;            /*!< [15..15] Filter scale configuration                                       */
      __IO uint32_t FS16       : 1;            /*!< [16..16] Filter scale configuration                                       */
      __IO uint32_t FS17       : 1;            /*!< [17..17] Filter scale configuration                                       */
      __IO uint32_t FS18       : 1;            /*!< [18..18] Filter scale configuration                                       */
      __IO uint32_t FS19       : 1;            /*!< [19..19] Filter scale configuration                                       */
      __IO uint32_t FS20       : 1;            /*!< [20..20] Filter scale configuration                                       */
      __IO uint32_t FS21       : 1;            /*!< [21..21] Filter scale configuration                                       */
      __IO uint32_t FS22       : 1;            /*!< [22..22] Filter scale configuration                                       */
      __IO uint32_t FS23       : 1;            /*!< [23..23] Filter scale configuration                                       */
      __IO uint32_t FS24       : 1;            /*!< [24..24] Filter scale configuration                                       */
      __IO uint32_t FS25       : 1;            /*!< [25..25] Filter scale configuration                                       */
      __IO uint32_t FS26       : 1;            /*!< [26..26] Filter scale configuration                                       */
      __IO uint32_t FS27       : 1;            /*!< [27..27] Filter scale configuration                                       */
            uint32_t            : 4;
    } FSCFG_b;
  } ;
  __I  uint32_t  RESERVED3;

  union {
    __IO uint32_t FAFIFO;                      /*!< (@ 0x00000214) Filter associated FIFO register                            */

    struct {
      __IO uint32_t FAF0       : 1;            /*!< [0..0] Filter 0 associated with FIFO                                      */
      __IO uint32_t FAF1       : 1;            /*!< [1..1] Filter 1 associated with FIFO                                      */
      __IO uint32_t FAF2       : 1;            /*!< [2..2] Filter 2 associated with FIFO                                      */
      __IO uint32_t FAF3       : 1;            /*!< [3..3] Filter 3 associated with FIFO                                      */
      __IO uint32_t FAF4       : 1;            /*!< [4..4] Filter 4 associated with FIFO                                      */
      __IO uint32_t FAF5       : 1;            /*!< [5..5] Filter 5 associated with FIFO                                      */
      __IO uint32_t FAF6       : 1;            /*!< [6..6] Filter 6 associated with FIFO                                      */
      __IO uint32_t FAF7       : 1;            /*!< [7..7] Filter 7 associated with FIFO                                      */
      __IO uint32_t FAF8       : 1;            /*!< [8..8] Filter 8 associated with FIFO                                      */
      __IO uint32_t FAF9       : 1;            /*!< [9..9] Filter 9 associated with FIFO                                      */
      __IO uint32_t FAF10      : 1;            /*!< [10..10] Filter 10 associated with FIFO                                   */
      __IO uint32_t FAF11      : 1;            /*!< [11..11] Filter 11 associated with FIFO                                   */
      __IO uint32_t FAF12      : 1;            /*!< [12..12] Filter 12 associated with FIFO                                   */
      __IO uint32_t FAF13      : 1;            /*!< [13..13] Filter 13 associated with FIFO                                   */
      __IO uint32_t FAF14      : 1;            /*!< [14..14] Filter 14 associated with FIFO                                   */
      __IO uint32_t FAF15      : 1;            /*!< [15..15] Filter 15 associated with FIFO                                   */
      __IO uint32_t FAF16      : 1;            /*!< [16..16] Filter 16 associated with FIFO                                   */
      __IO uint32_t FAF17      : 1;            /*!< [17..17] Filter 17 associated with FIFO                                   */
      __IO uint32_t FAF18      : 1;            /*!< [18..18] Filter 18 associated with FIFO                                   */
      __IO uint32_t FAF19      : 1;            /*!< [19..19] Filter 19 associated with FIFO                                   */
      __IO uint32_t FAF20      : 1;            /*!< [20..20] Filter 20 associated with FIFO                                   */
      __IO uint32_t FAF21      : 1;            /*!< [21..21] Filter 21 associated with FIFO                                   */
      __IO uint32_t FAF22      : 1;            /*!< [22..22] Filter 22 associated with FIFO                                   */
      __IO uint32_t FAF23      : 1;            /*!< [23..23] Filter 23 associated with FIFO                                   */
      __IO uint32_t FAF24      : 1;            /*!< [24..24] Filter 24 associated with FIFO                                   */
      __IO uint32_t FAF25      : 1;            /*!< [25..25] Filter 25 associated with FIFO                                   */
      __IO uint32_t FAF26      : 1;            /*!< [26..26] Filter 26 associated with FIFO                                   */
      __IO uint32_t FAF27      : 1;            /*!< [27..27] Filter 27 associated with FIFO                                   */
            uint32_t            : 4;
    } FAFIFO_b;
  } ;
  __I  uint32_t  RESERVED4;

  union {
    __IO uint32_t FW;                          /*!< (@ 0x0000021C) Filter working register                                    */

    struct {
      __IO uint32_t FW0        : 1;            /*!< [0..0] Filter working                                                     */
      __IO uint32_t FW1        : 1;            /*!< [1..1] Filter working                                                     */
      __IO uint32_t FW2        : 1;            /*!< [2..2] Filter working                                                     */
      __IO uint32_t FW3        : 1;            /*!< [3..3] Filter working                                                     */
      __IO uint32_t FW4        : 1;            /*!< [4..4] Filter working                                                     */
      __IO uint32_t FW5        : 1;            /*!< [5..5] Filter working                                                     */
      __IO uint32_t FW6        : 1;            /*!< [6..6] Filter working                                                     */
      __IO uint32_t FW7        : 1;            /*!< [7..7] Filter working                                                     */
      __IO uint32_t FW8        : 1;            /*!< [8..8] Filter working                                                     */
      __IO uint32_t FW9        : 1;            /*!< [9..9] Filter working                                                     */
      __IO uint32_t FW10       : 1;            /*!< [10..10] Filter working                                                   */
      __IO uint32_t FW11       : 1;            /*!< [11..11] Filter working                                                   */
      __IO uint32_t FW12       : 1;            /*!< [12..12] Filter working                                                   */
      __IO uint32_t FW13       : 1;            /*!< [13..13] Filter working                                                   */
      __IO uint32_t FW14       : 1;            /*!< [14..14] Filter working                                                   */
      __IO uint32_t FW15       : 1;            /*!< [15..15] Filter working                                                   */
      __IO uint32_t FW16       : 1;            /*!< [16..16] Filter working                                                   */
      __IO uint32_t FW17       : 1;            /*!< [17..17] Filter working                                                   */
      __IO uint32_t FW18       : 1;            /*!< [18..18] Filter working                                                   */
      __IO uint32_t FW19       : 1;            /*!< [19..19] Filter working                                                   */
      __IO uint32_t FW20       : 1;            /*!< [20..20] Filter working                                                   */
      __IO uint32_t FW21       : 1;            /*!< [21..21] Filter working                                                   */
      __IO uint32_t FW22       : 1;            /*!< [22..22] Filter working                                                   */
      __IO uint32_t FW23       : 1;            /*!< [23..23] Filter working                                                   */
      __IO uint32_t FW24       : 1;            /*!< [24..24] Filter working                                                   */
      __IO uint32_t FW25       : 1;            /*!< [25..25] Filter working                                                   */
      __IO uint32_t FW26       : 1;            /*!< [26..26] Filter working                                                   */
      __IO uint32_t FW27       : 1;            /*!< [27..27] Filter working                                                   */
            uint32_t            : 4;
    } FW_b;
  } ;
  __I  uint32_t  RESERVED5[8];

  union {
    __IO uint32_t F0DATA0;                     /*!< (@ 0x00000240) Filter 0 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F0DATA0_b;
  } ;

  union {
    __IO uint32_t F0DATA1;                     /*!< (@ 0x00000244) Filter 0 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F0DATA1_b;
  } ;

  union {
    __IO uint32_t F1DATA0;                     /*!< (@ 0x00000248) Filter 1 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F1DATA0_b;
  } ;

  union {
    __IO uint32_t F1DATA1;                     /*!< (@ 0x0000024C) Filter 1 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F1DATA1_b;
  } ;

  union {
    __IO uint32_t F2DATA0;                     /*!< (@ 0x00000250) Filter 2 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F2DATA0_b;
  } ;

  union {
    __IO uint32_t F2DATA1;                     /*!< (@ 0x00000254) Filter 2 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F2DATA1_b;
  } ;

  union {
    __IO uint32_t F3DATA0;                     /*!< (@ 0x00000258) Filter 3 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F3DATA0_b;
  } ;

  union {
    __IO uint32_t F3DATA1;                     /*!< (@ 0x0000025C) Filter 3 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F3DATA1_b;
  } ;

  union {
    __IO uint32_t F4DATA0;                     /*!< (@ 0x00000260) Filter 4 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F4DATA0_b;
  } ;

  union {
    __IO uint32_t F4DATA1;                     /*!< (@ 0x00000264) Filter 4 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F4DATA1_b;
  } ;

  union {
    __IO uint32_t F5DATA0;                     /*!< (@ 0x00000268) Filter 5 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F5DATA0_b;
  } ;

  union {
    __IO uint32_t F5DATA1;                     /*!< (@ 0x0000026C) Filter 5 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F5DATA1_b;
  } ;

  union {
    __IO uint32_t F6DATA0;                     /*!< (@ 0x00000270) Filter 6 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F6DATA0_b;
  } ;

  union {
    __IO uint32_t F6DATA1;                     /*!< (@ 0x00000274) Filter 6 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F6DATA1_b;
  } ;

  union {
    __IO uint32_t F7DATA0;                     /*!< (@ 0x00000278) Filter 7 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F7DATA0_b;
  } ;

  union {
    __IO uint32_t F7DATA1;                     /*!< (@ 0x0000027C) Filter 7 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F7DATA1_b;
  } ;

  union {
    __IO uint32_t F8DATA0;                     /*!< (@ 0x00000280) Filter 8 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F8DATA0_b;
  } ;

  union {
    __IO uint32_t F8DATA1;                     /*!< (@ 0x00000284) Filter 8 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F8DATA1_b;
  } ;

  union {
    __IO uint32_t F9DATA0;                     /*!< (@ 0x00000288) Filter 9 data 0 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F9DATA0_b;
  } ;

  union {
    __IO uint32_t F9DATA1;                     /*!< (@ 0x0000028C) Filter 9 data 1 register                                   */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F9DATA1_b;
  } ;

  union {
    __IO uint32_t F10DATA0;                    /*!< (@ 0x00000290) Filter 10 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F10DATA0_b;
  } ;

  union {
    __IO uint32_t F10DATA1;                    /*!< (@ 0x00000294) Filter 10 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F10DATA1_b;
  } ;

  union {
    __IO uint32_t F11DATA0;                    /*!< (@ 0x00000298) Filter 11 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F11DATA0_b;
  } ;

  union {
    __IO uint32_t F11DATA1;                    /*!< (@ 0x0000029C) Filter 11 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F11DATA1_b;
  } ;

  union {
    __IO uint32_t F12DATA0;                    /*!< (@ 0x000002A0) Filter 12 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F12DATA0_b;
  } ;

  union {
    __IO uint32_t F12DATA1;                    /*!< (@ 0x000002A4) Filter 12 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F12DATA1_b;
  } ;

  union {
    __IO uint32_t F13DATA0;                    /*!< (@ 0x000002A8) Filter 13 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F13DATA0_b;
  } ;

  union {
    __IO uint32_t F13DATA1;                    /*!< (@ 0x000002AC) Filter 13 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F13DATA1_b;
  } ;

  union {
    __IO uint32_t F14DATA0;                    /*!< (@ 0x000002B0) Filter 14 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F14DATA0_b;
  } ;

  union {
    __IO uint32_t F14DATA1;                    /*!< (@ 0x000002B4) Filter 14 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F14DATA1_b;
  } ;

  union {
    __IO uint32_t F15DATA0;                    /*!< (@ 0x000002B8) Filter 15 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F15DATA0_b;
  } ;

  union {
    __IO uint32_t F15DATA1;                    /*!< (@ 0x000002BC) Filter 15 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F15DATA1_b;
  } ;

  union {
    __IO uint32_t F16DATA0;                    /*!< (@ 0x000002C0) Filter 16 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F16DATA0_b;
  } ;

  union {
    __IO uint32_t F16DATA1;                    /*!< (@ 0x000002C4) Filter 16 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F16DATA1_b;
  } ;

  union {
    __IO uint32_t F17DATA0;                    /*!< (@ 0x000002C8) Filter 17 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F17DATA0_b;
  } ;

  union {
    __IO uint32_t F17DATA1;                    /*!< (@ 0x000002CC) Filter 17 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F17DATA1_b;
  } ;

  union {
    __IO uint32_t F18DATA0;                    /*!< (@ 0x000002D0) Filter 18 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F18DATA0_b;
  } ;

  union {
    __IO uint32_t F18DATA1;                    /*!< (@ 0x000002D4) Filter 18 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F18DATA1_b;
  } ;

  union {
    __IO uint32_t F19DATA0;                    /*!< (@ 0x000002D8) Filter 19 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F19DATA0_b;
  } ;

  union {
    __IO uint32_t F19DATA1;                    /*!< (@ 0x000002DC) Filter 19 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F19DATA1_b;
  } ;

  union {
    __IO uint32_t F20DATA0;                    /*!< (@ 0x000002E0) Filter 20 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F20DATA0_b;
  } ;

  union {
    __IO uint32_t F20DATA1;                    /*!< (@ 0x000002E4) Filter 20 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F20DATA1_b;
  } ;

  union {
    __IO uint32_t F21DATA0;                    /*!< (@ 0x000002E8) Filter 21 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F21DATA0_b;
  } ;

  union {
    __IO uint32_t F21DATA1;                    /*!< (@ 0x000002EC) Filter 21 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F21DATA1_b;
  } ;

  union {
    __IO uint32_t F22DATA0;                    /*!< (@ 0x000002F0) Filter 22 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F22DATA0_b;
  } ;

  union {
    __IO uint32_t F22DATA1;                    /*!< (@ 0x000002F4) Filter 22 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F22DATA1_b;
  } ;

  union {
    __IO uint32_t F23DATA0;                    /*!< (@ 0x000002F8) Filter 23 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F23DATA0_b;
  } ;

  union {
    __IO uint32_t F23DATA1;                    /*!< (@ 0x000002FC) Filter 23 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F23DATA1_b;
  } ;

  union {
    __IO uint32_t F24DATA0;                    /*!< (@ 0x00000300) Filter 24 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F24DATA0_b;
  } ;

  union {
    __IO uint32_t F24DATA1;                    /*!< (@ 0x00000304) Filter 24 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F24DATA1_b;
  } ;

  union {
    __IO uint32_t F25DATA0;                    /*!< (@ 0x00000308) Filter 25 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F25DATA0_b;
  } ;

  union {
    __IO uint32_t F25DATA1;                    /*!< (@ 0x0000030C) Filter 25 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F25DATA1_b;
  } ;

  union {
    __IO uint32_t F26DATA0;                    /*!< (@ 0x00000310) Filter 26 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F26DATA0_b;
  } ;

  union {
    __IO uint32_t F26DATA1;                    /*!< (@ 0x00000314) Filter 26 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F26DATA1_b;
  } ;

  union {
    __IO uint32_t F27DATA0;                    /*!< (@ 0x00000318) Filter 27 data 0 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F27DATA0_b;
  } ;

  union {
    __IO uint32_t F27DATA1;                    /*!< (@ 0x0000031C) Filter 27 data 1 register                                  */

    struct {
      __IO uint32_t FD0        : 1;            /*!< [0..0] Filter bits                                                        */
      __IO uint32_t FD1        : 1;            /*!< [1..1] Filter bits                                                        */
      __IO uint32_t FD2        : 1;            /*!< [2..2] Filter bits                                                        */
      __IO uint32_t FD3        : 1;            /*!< [3..3] Filter bits                                                        */
      __IO uint32_t FD4        : 1;            /*!< [4..4] Filter bits                                                        */
      __IO uint32_t FD5        : 1;            /*!< [5..5] Filter bits                                                        */
      __IO uint32_t FD6        : 1;            /*!< [6..6] Filter bits                                                        */
      __IO uint32_t FD7        : 1;            /*!< [7..7] Filter bits                                                        */
      __IO uint32_t FD8        : 1;            /*!< [8..8] Filter bits                                                        */
      __IO uint32_t FD9        : 1;            /*!< [9..9] Filter bits                                                        */
      __IO uint32_t FD10       : 1;            /*!< [10..10] Filter bits                                                      */
      __IO uint32_t FD11       : 1;            /*!< [11..11] Filter bits                                                      */
      __IO uint32_t FD12       : 1;            /*!< [12..12] Filter bits                                                      */
      __IO uint32_t FD13       : 1;            /*!< [13..13] Filter bits                                                      */
      __IO uint32_t FD14       : 1;            /*!< [14..14] Filter bits                                                      */
      __IO uint32_t FD15       : 1;            /*!< [15..15] Filter bits                                                      */
      __IO uint32_t FD16       : 1;            /*!< [16..16] Filter bits                                                      */
      __IO uint32_t FD17       : 1;            /*!< [17..17] Filter bits                                                      */
      __IO uint32_t FD18       : 1;            /*!< [18..18] Filter bits                                                      */
      __IO uint32_t FD19       : 1;            /*!< [19..19] Filter bits                                                      */
      __IO uint32_t FD20       : 1;            /*!< [20..20] Filter bits                                                      */
      __IO uint32_t FD21       : 1;            /*!< [21..21] Filter bits                                                      */
      __IO uint32_t FD22       : 1;            /*!< [22..22] Filter bits                                                      */
      __IO uint32_t FD23       : 1;            /*!< [23..23] Filter bits                                                      */
      __IO uint32_t FD24       : 1;            /*!< [24..24] Filter bits                                                      */
      __IO uint32_t FD25       : 1;            /*!< [25..25] Filter bits                                                      */
      __IO uint32_t FD26       : 1;            /*!< [26..26] Filter bits                                                      */
      __IO uint32_t FD27       : 1;            /*!< [27..27] Filter bits                                                      */
      __IO uint32_t FD28       : 1;            /*!< [28..28] Filter bits                                                      */
      __IO uint32_t FD29       : 1;            /*!< [29..29] Filter bits                                                      */
      __IO uint32_t FD30       : 1;            /*!< [30..30] Filter bits                                                      */
      __IO uint32_t FD31       : 1;            /*!< [31..31] Filter bits                                                      */
    } F27DATA1_b;
  } ;
} CAN0_Type;                                    /*!< Size = 800 (0x320)                                                        */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief cyclic redundancy check calculation unit (CRC)
  */

typedef struct {                                /*!< (@ 0x40023000) CRC Structure                                              */

  union {
    __IO uint32_t DATA;                        /*!< (@ 0x00000000) Data register                                              */

    struct {
      __IO uint32_t DATA       : 32;           /*!< [31..0] CRC calculation result bits                                       */
    } DATA_b;
  } ;

  union {
    __IO uint32_t FDATA;                       /*!< (@ 0x00000004) Free data register                                         */

    struct {
      __IO uint32_t FDATA      : 8;            /*!< [7..0] Free Data Register bits                                            */
            uint32_t            : 24;
    } FDATA_b;
  } ;

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000008) Control register                                           */

    struct {
      __IO uint32_t RST        : 1;            /*!< [0..0] reset bit                                                          */
            uint32_t            : 31;
    } CTL_b;
  } ;
} CRC_Type;                                     /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                            DAC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Digital-to-analog converter (DAC)
  */

typedef struct {                                /*!< (@ 0x40007400) DAC Structure                                              */

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000000) control register                                           */

    struct {
      __IO uint32_t DEN0       : 1;            /*!< [0..0] DAC0 enable                                                        */
      __IO uint32_t DBOFF0     : 1;            /*!< [1..1] DAC0 output buffer turn off                                        */
      __IO uint32_t DTEN0      : 1;            /*!< [2..2] DAC0 trigger enable                                                */
      __IO uint32_t DTSEL0     : 3;            /*!< [5..3] DAC0 trigger selection                                             */
      __IO uint32_t DWM0       : 2;            /*!< [7..6] DAC0 noise wave mode                                               */
      __IO uint32_t DWBW0      : 4;            /*!< [11..8] DAC0 noise wave bit width                                         */
      __IO uint32_t DDMAEN0    : 1;            /*!< [12..12] DAC0 DMA enable                                                  */
            uint32_t            : 3;
      __IO uint32_t DEN1       : 1;            /*!< [16..16] DAC1 enable                                                      */
      __IO uint32_t DBOFF1     : 1;            /*!< [17..17] DAC1 output buffer turn off                                      */
      __IO uint32_t DTEN1      : 1;            /*!< [18..18] DAC1 trigger enable                                              */
      __IO uint32_t DTSEL1     : 3;            /*!< [21..19] DAC1 trigger selection                                           */
      __IO uint32_t DWM1       : 2;            /*!< [23..22] DAC1 noise wave mode                                             */
      __IO uint32_t DWBW1      : 4;            /*!< [27..24] DAC1 noise wave bit width                                        */
      __IO uint32_t DDMAEN1    : 1;            /*!< [28..28] DAC1 DMA enable                                                  */
            uint32_t            : 3;
    } CTL_b;
  } ;

  union {
    __O  uint32_t SWT;                         /*!< (@ 0x00000004) software trigger register                                  */

    struct {
      __O  uint32_t SWTR0      : 1;            /*!< [0..0] DAC0 software trigger                                              */
      __O  uint32_t SWTR1      : 1;            /*!< [1..1] DAC1 software trigger                                              */
            uint32_t            : 30;
    } SWT_b;
  } ;

  union {
    __IO uint32_t DAC0_R12DH;                  /*!< (@ 0x00000008) DAC0 12-bit right-aligned data holding register            */

    struct {
      __IO uint32_t DAC0_DH    : 12;           /*!< [11..0] DAC0 12-bit right-aligned data                                    */
            uint32_t            : 20;
    } DAC0_R12DH_b;
  } ;

  union {
    __IO uint32_t DAC0_L12DH;                  /*!< (@ 0x0000000C) DAC0 12-bit left-aligned data holding register             */

    struct {
            uint32_t            : 4;
      __IO uint32_t DAC0_DH    : 12;           /*!< [15..4] DAC0 12-bit left-aligned data                                     */
            uint32_t            : 16;
    } DAC0_L12DH_b;
  } ;

  union {
    __IO uint32_t DAC0_R8DH;                   /*!< (@ 0x00000010) DAC0 8-bit right aligned data holding register             */

    struct {
      __IO uint32_t DAC0_DH    : 8;            /*!< [7..0] DAC0 8-bit right-aligned data                                      */
            uint32_t            : 24;
    } DAC0_R8DH_b;
  } ;

  union {
    __IO uint32_t DAC1_R12DH;                  /*!< (@ 0x00000014) DAC1 12-bit right-aligned data holding register            */

    struct {
      __IO uint32_t DAC1_DH    : 12;           /*!< [11..0] DAC1 12-bit right-aligned data                                    */
            uint32_t            : 20;
    } DAC1_R12DH_b;
  } ;

  union {
    __IO uint32_t DAC1_L12DH;                  /*!< (@ 0x00000018) DAC1 12-bit left aligned data holding register             */

    struct {
            uint32_t            : 4;
      __IO uint32_t DAC1_DH    : 12;           /*!< [15..4] DAC1 12-bit left-aligned data                                     */
            uint32_t            : 16;
    } DAC1_L12DH_b;
  } ;

  union {
    __IO uint32_t DAC1_R8DH;                   /*!< (@ 0x0000001C) DAC1 8-bit right aligned data holding register             */

    struct {
      __IO uint32_t DAC1_DH    : 8;            /*!< [7..0] DAC1 8-bit right-aligned data                                      */
            uint32_t            : 24;
    } DAC1_R8DH_b;
  } ;

  union {
    __IO uint32_t DACC_R12DH;                  /*!< (@ 0x00000020) DAC concurrent mode 12-bit right-aligned data
                                                                    holding register                                           */

    struct {
      __IO uint32_t DAC0_DH    : 12;           /*!< [11..0] DAC0 12-bit right-aligned data                                    */
            uint32_t            : 4;
      __IO uint32_t DAC1_DH    : 12;           /*!< [27..16] DAC1 12-bit right-aligned data                                   */
            uint32_t            : 4;
    } DACC_R12DH_b;
  } ;

  union {
    __IO uint32_t DACC_L12DH;                  /*!< (@ 0x00000024) DAC concurrent mode 12-bit left aligned data
                                                                    holding register                                           */

    struct {
            uint32_t            : 4;
      __IO uint32_t DAC0_DH    : 12;           /*!< [15..4] DAC0 12-bit left-aligned data                                     */
            uint32_t            : 4;
      __IO uint32_t DAC1_DH    : 12;           /*!< [31..20] DAC1 12-bit left-aligned data                                    */
    } DACC_L12DH_b;
  } ;

  union {
    __IO uint32_t DACC_R8DH;                   /*!< (@ 0x00000028) DAC concurrent mode 8-bit right aligned data
                                                                    holding register                                           */

    struct {
      __IO uint32_t DAC0_DH    : 8;            /*!< [7..0] DAC0 8-bit right-aligned data                                      */
      __IO uint32_t DAC1_DH    : 8;            /*!< [15..8] DAC1 8-bit right-aligned data                                     */
            uint32_t            : 16;
    } DACC_R8DH_b;
  } ;

  union {
    __I  uint32_t DAC0_DO;                     /*!< (@ 0x0000002C) DAC0 data output register                                  */

    struct {
      __I  uint32_t DAC0_DO    : 12;           /*!< [11..0] DAC0 data output                                                  */
            uint32_t            : 20;
    } DAC0_DO_b;
  } ;

  union {
    __I  uint32_t DAC1_DO;                     /*!< (@ 0x00000030) DAC1 data output register                                  */

    struct {
      __I  uint32_t DAC1_DO    : 12;           /*!< [11..0] DAC1 data output                                                  */
            uint32_t            : 20;
    } DAC1_DO_b;
  } ;
} DAC_Type;                                     /*!< Size = 52 (0x34)                                                          */



/* =========================================================================================================================== */
/* ================                                            DBG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Debug support (DBG)
  */

typedef struct {                                /*!< (@ 0xE0042000) DBG Structure                                              */

  union {
    __I  uint32_t ID;                          /*!< (@ 0x00000000) ID code register                                           */

    struct {
      __I  uint32_t ID_CODE    : 32;           /*!< [31..0] DBG ID code register                                              */
    } ID_b;
  } ;

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000004) Control register 0                                         */

    struct {
      __IO uint32_t SLP_HOLD   : 1;            /*!< [0..0] Sleep mode hold register                                           */
      __IO uint32_t DSLP_HOLD  : 1;            /*!< [1..1] Deep-sleep mode hold register                                      */
      __IO uint32_t STB_HOLD   : 1;            /*!< [2..2] Standby mode hold register                                         */
            uint32_t            : 5;
      __IO uint32_t FWDGT_HOLD : 1;            /*!< [8..8] FWDGT hold bit                                                     */
      __IO uint32_t WWDGT_HOLD : 1;            /*!< [9..9] WWDGT hold bit                                                     */
      __IO uint32_t TIMER0_HOLD : 1;           /*!< [10..10] TIMER 0 hold bit                                                 */
      __IO uint32_t TIMER1_HOLD : 1;           /*!< [11..11] TIMER 1 hold bit                                                 */
      __IO uint32_t TIMER2_HOLD : 1;           /*!< [12..12] TIMER 2 hold bit                                                 */
      __IO uint32_t TIMER3_HOLD : 1;           /*!< [13..13] TIMER 23 hold bit                                                */
      __IO uint32_t CAN0_HOLD  : 1;            /*!< [14..14] CAN0 hold bit                                                    */
      __IO uint32_t I2C0_HOLD  : 1;            /*!< [15..15] I2C0 hold bit                                                    */
      __IO uint32_t I2C1_HOLD  : 1;            /*!< [16..16] I2C1 hold bit                                                    */
            uint32_t            : 1;
      __IO uint32_t TIMER4_HOLD : 1;           /*!< [18..18] TIMER4_HOLD                                                      */
      __IO uint32_t TIMER5_HOLD : 1;           /*!< [19..19] TIMER 5 hold bit                                                 */
      __IO uint32_t TIMER6_HOLD : 1;           /*!< [20..20] TIMER 6 hold bit                                                 */
      __IO uint32_t CAN1_HOLD  : 1;            /*!< [21..21] CAN1 hold bit                                                    */
            uint32_t            : 10;
    } CTL_b;
  } ;
} DBG_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                           DMA0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA controller (DMA0)
  */

typedef struct {                                /*!< (@ 0x40020000) DMA0 Structure                                             */

  union {
    __I  uint32_t INTF;                        /*!< (@ 0x00000000) Interrupt flag register                                    */

    struct {
      __I  uint32_t GIF0       : 1;            /*!< [0..0] Global interrupt flag of channel 0                                 */
      __I  uint32_t FTFIF0     : 1;            /*!< [1..1] Full Transfer finish flag of channe 0                              */
      __I  uint32_t HTFIF0     : 1;            /*!< [2..2] Half transfer finish flag of channel 0                             */
      __I  uint32_t ERRIF0     : 1;            /*!< [3..3] Error flag of channel 0                                            */
      __I  uint32_t GIF1       : 1;            /*!< [4..4] Global interrupt flag of channel 1                                 */
      __I  uint32_t FTFIF1     : 1;            /*!< [5..5] Full Transfer finish flag of channe 1                              */
      __I  uint32_t HTFIF1     : 1;            /*!< [6..6] Half transfer finish flag of channel 1                             */
      __I  uint32_t ERRIF1     : 1;            /*!< [7..7] Error flag of channel 1                                            */
      __I  uint32_t GIF2       : 1;            /*!< [8..8] Global interrupt flag of channel 2                                 */
      __I  uint32_t FTFIF2     : 1;            /*!< [9..9] Full Transfer finish flag of channe 2                              */
      __I  uint32_t HTFIF2     : 1;            /*!< [10..10] Half transfer finish flag of channel 2                           */
      __I  uint32_t ERRIF2     : 1;            /*!< [11..11] Error flag of channel 2                                          */
      __I  uint32_t GIF3       : 1;            /*!< [12..12] Global interrupt flag of channel 3                               */
      __I  uint32_t FTFIF3     : 1;            /*!< [13..13] Full Transfer finish flag of channe 3                            */
      __I  uint32_t HTFIF3     : 1;            /*!< [14..14] Half transfer finish flag of channel 3                           */
      __I  uint32_t ERRIF3     : 1;            /*!< [15..15] Error flag of channel 3                                          */
      __I  uint32_t GIF4       : 1;            /*!< [16..16] Global interrupt flag of channel 4                               */
      __I  uint32_t FTFIF4     : 1;            /*!< [17..17] Full Transfer finish flag of channe 4                            */
      __I  uint32_t HTFIF4     : 1;            /*!< [18..18] Half transfer finish flag of channel 4                           */
      __I  uint32_t ERRIF4     : 1;            /*!< [19..19] Error flag of channel 4                                          */
      __I  uint32_t GIF5       : 1;            /*!< [20..20] Global interrupt flag of channel 5                               */
      __I  uint32_t FTFIF5     : 1;            /*!< [21..21] Full Transfer finish flag of channe 5                            */
      __I  uint32_t HTFIF5     : 1;            /*!< [22..22] Half transfer finish flag of channel 5                           */
      __I  uint32_t ERRIF5     : 1;            /*!< [23..23] Error flag of channel 5                                          */
      __I  uint32_t GIF6       : 1;            /*!< [24..24] Global interrupt flag of channel 6                               */
      __I  uint32_t FTFIF6     : 1;            /*!< [25..25] Full Transfer finish flag of channe 6                            */
      __I  uint32_t HTFIF6     : 1;            /*!< [26..26] Half transfer finish flag of channel 6                           */
      __I  uint32_t ERRIF6     : 1;            /*!< [27..27] Error flag of channel 6                                          */
            uint32_t            : 4;
    } INTF_b;
  } ;

  union {
    __O  uint32_t INTC;                        /*!< (@ 0x00000004) Interrupt flag clear register                              */

    struct {
      __O  uint32_t GIFC0      : 1;            /*!< [0..0] Clear global interrupt flag of channel 0                           */
      __O  uint32_t FTFIFC0    : 1;            /*!< [1..1] Clear bit for full transfer finish flag of channel 0               */
      __O  uint32_t HTFIFC0    : 1;            /*!< [2..2] Clear bit for half transfer finish flag of channel 0               */
      __O  uint32_t ERRIFC0    : 1;            /*!< [3..3] Clear bit for error flag of channel 0                              */
      __O  uint32_t GIFC1      : 1;            /*!< [4..4] Clear global interrupt flag of channel 1                           */
      __O  uint32_t FTFIFC1    : 1;            /*!< [5..5] Clear bit for full transfer finish flag of channel 1               */
      __O  uint32_t HTFIFC1    : 1;            /*!< [6..6] Clear bit for half transfer finish flag of channel 1               */
      __O  uint32_t ERRIFC1    : 1;            /*!< [7..7] Clear bit for error flag of channel 1                              */
      __O  uint32_t GIFC2      : 1;            /*!< [8..8] Clear global interrupt flag of channel 2                           */
      __O  uint32_t FTFIFC2    : 1;            /*!< [9..9] Clear bit for full transfer finish flag of channel 2               */
      __O  uint32_t HTFIFC2    : 1;            /*!< [10..10] Clear bit for half transfer finish flag of channel
                                                     2                                                                         */
      __O  uint32_t ERRIFC2    : 1;            /*!< [11..11] Clear bit for error flag of channel 2                            */
      __O  uint32_t GIFC3      : 1;            /*!< [12..12] Clear global interrupt flag of channel 3                         */
      __O  uint32_t FTFIFC3    : 1;            /*!< [13..13] Clear bit for full transfer finish flag of channel
                                                     3                                                                         */
      __O  uint32_t HTFIFC3    : 1;            /*!< [14..14] Clear bit for half transfer finish flag of channel
                                                     3                                                                         */
      __O  uint32_t ERRIFC3    : 1;            /*!< [15..15] Clear bit for error flag of channel 3                            */
      __O  uint32_t GIFC4      : 1;            /*!< [16..16] Clear global interrupt flag of channel 4                         */
      __O  uint32_t FTFIFC4    : 1;            /*!< [17..17] Clear bit for full transfer finish flag of channel
                                                     4                                                                         */
      __O  uint32_t HTFIFC4    : 1;            /*!< [18..18] Clear bit for half transfer finish flag of channel
                                                     4                                                                         */
      __O  uint32_t ERRIFC4    : 1;            /*!< [19..19] Clear bit for error flag of channel 4                            */
      __O  uint32_t GIFC5      : 1;            /*!< [20..20] Clear global interrupt flag of channel 5                         */
      __O  uint32_t FTFIFC5    : 1;            /*!< [21..21] Clear bit for full transfer finish flag of channel
                                                     5                                                                         */
      __O  uint32_t HTFIFC5    : 1;            /*!< [22..22] Clear bit for half transfer finish flag of channel
                                                     5                                                                         */
      __O  uint32_t ERRIFC5    : 1;            /*!< [23..23] Clear bit for error flag of channel 5                            */
      __O  uint32_t GIFC6      : 1;            /*!< [24..24] Clear global interrupt flag of channel 6                         */
      __O  uint32_t FTFIFC6    : 1;            /*!< [25..25] Clear bit for full transfer finish flag of channel
                                                     6                                                                         */
      __O  uint32_t HTFIFC6    : 1;            /*!< [26..26] Clear bit for half transfer finish flag of channel
                                                     6                                                                         */
      __O  uint32_t ERRIFC6    : 1;            /*!< [27..27] Clear bit for error flag of channel 6                            */
            uint32_t            : 4;
    } INTC_b;
  } ;

  union {
    __IO uint32_t CH0CTL;                      /*!< (@ 0x00000008) Channel 0 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH0CTL_b;
  } ;

  union {
    __IO uint32_t CH0CNT;                      /*!< (@ 0x0000000C) Channel 0 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH0CNT_b;
  } ;

  union {
    __IO uint32_t CH0PADDR;                    /*!< (@ 0x00000010) Channel 0 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH0PADDR_b;
  } ;

  union {
    __IO uint32_t CH0MADDR;                    /*!< (@ 0x00000014) Channel 0 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH0MADDR_b;
  } ;
  __I  uint32_t  RESERVED;

  union {
    __IO uint32_t CH1CTL;                      /*!< (@ 0x0000001C) Channel 1 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH1CTL_b;
  } ;

  union {
    __IO uint32_t CH1CNT;                      /*!< (@ 0x00000020) Channel 1 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH1CNT_b;
  } ;

  union {
    __IO uint32_t CH1PADDR;                    /*!< (@ 0x00000024) Channel 1 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH1PADDR_b;
  } ;

  union {
    __IO uint32_t CH1MADDR;                    /*!< (@ 0x00000028) Channel 1 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH1MADDR_b;
  } ;
  __I  uint32_t  RESERVED1;

  union {
    __IO uint32_t CH2CTL;                      /*!< (@ 0x00000030) Channel 2 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH2CTL_b;
  } ;

  union {
    __IO uint32_t CH2CNT;                      /*!< (@ 0x00000034) Channel 2 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH2CNT_b;
  } ;

  union {
    __IO uint32_t CH2PADDR;                    /*!< (@ 0x00000038) Channel 2 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH2PADDR_b;
  } ;

  union {
    __IO uint32_t CH2MADDR;                    /*!< (@ 0x0000003C) Channel 2 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH2MADDR_b;
  } ;
  __I  uint32_t  RESERVED2;

  union {
    __IO uint32_t CH3CTL;                      /*!< (@ 0x00000044) Channel 3 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH3CTL_b;
  } ;

  union {
    __IO uint32_t CH3CNT;                      /*!< (@ 0x00000048) Channel 3 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH3CNT_b;
  } ;

  union {
    __IO uint32_t CH3PADDR;                    /*!< (@ 0x0000004C) Channel 3 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH3PADDR_b;
  } ;

  union {
    __IO uint32_t CH3MADDR;                    /*!< (@ 0x00000050) Channel 3 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH3MADDR_b;
  } ;
  __I  uint32_t  RESERVED3;

  union {
    __IO uint32_t CH4CTL;                      /*!< (@ 0x00000058) Channel 4 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH4CTL_b;
  } ;

  union {
    __IO uint32_t CH4CNT;                      /*!< (@ 0x0000005C) Channel 4 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH4CNT_b;
  } ;

  union {
    __IO uint32_t CH4PADDR;                    /*!< (@ 0x00000060) Channel 4 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH4PADDR_b;
  } ;

  union {
    __IO uint32_t CH4MADDR;                    /*!< (@ 0x00000064) Channel 4 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH4MADDR_b;
  } ;
  __I  uint32_t  RESERVED4;

  union {
    __IO uint32_t CH5CTL;                      /*!< (@ 0x0000006C) Channel 5 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH5CTL_b;
  } ;

  union {
    __IO uint32_t CH5CNT;                      /*!< (@ 0x00000070) Channel 5 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH5CNT_b;
  } ;

  union {
    __IO uint32_t CH5PADDR;                    /*!< (@ 0x00000074) Channel 5 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH5PADDR_b;
  } ;

  union {
    __IO uint32_t CH5MADDR;                    /*!< (@ 0x00000078) Channel 5 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH5MADDR_b;
  } ;
  __I  uint32_t  RESERVED5;

  union {
    __IO uint32_t CH6CTL;                      /*!< (@ 0x00000080) Channel 6 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH6CTL_b;
  } ;

  union {
    __IO uint32_t CH6CNT;                      /*!< (@ 0x00000084) Channel 6 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH6CNT_b;
  } ;

  union {
    __IO uint32_t CH6PADDR;                    /*!< (@ 0x00000088) Channel 6 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH6PADDR_b;
  } ;

  union {
    __IO uint32_t CH6MADDR;                    /*!< (@ 0x0000008C) Channel 6 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH6MADDR_b;
  } ;
} DMA0_Type;                                    /*!< Size = 144 (0x90)                                                         */



/* =========================================================================================================================== */
/* ================                                           DMA1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Direct memory access controller (DMA1)
  */

typedef struct {                                /*!< (@ 0x40020400) DMA1 Structure                                             */

  union {
    __I  uint32_t INTF;                        /*!< (@ 0x00000000) Interrupt flag register                                    */

    struct {
      __I  uint32_t GIF0       : 1;            /*!< [0..0] Global interrupt flag of channel 0                                 */
      __I  uint32_t FTFIF0     : 1;            /*!< [1..1] Full Transfer finish flag of channe 0                              */
      __I  uint32_t HTFIF0     : 1;            /*!< [2..2] Half transfer finish flag of channel 0                             */
      __I  uint32_t ERRIF0     : 1;            /*!< [3..3] Error flag of channel 0                                            */
      __I  uint32_t GIF1       : 1;            /*!< [4..4] Global interrupt flag of channel 1                                 */
      __I  uint32_t FTFIF1     : 1;            /*!< [5..5] Full Transfer finish flag of channe 1                              */
      __I  uint32_t HTFIF1     : 1;            /*!< [6..6] Half transfer finish flag of channel 1                             */
      __I  uint32_t ERRIF1     : 1;            /*!< [7..7] Error flag of channel 1                                            */
      __I  uint32_t GIF2       : 1;            /*!< [8..8] Global interrupt flag of channel 2                                 */
      __I  uint32_t FTFIF2     : 1;            /*!< [9..9] Full Transfer finish flag of channe 2                              */
      __I  uint32_t HTFIF2     : 1;            /*!< [10..10] Half transfer finish flag of channel 2                           */
      __I  uint32_t ERRIF2     : 1;            /*!< [11..11] Error flag of channel 2                                          */
      __I  uint32_t GIF3       : 1;            /*!< [12..12] Global interrupt flag of channel 3                               */
      __I  uint32_t FTFIF3     : 1;            /*!< [13..13] Full Transfer finish flag of channe 3                            */
      __I  uint32_t HTFIF3     : 1;            /*!< [14..14] Half transfer finish flag of channel 3                           */
      __I  uint32_t ERRIF3     : 1;            /*!< [15..15] Error flag of channel 3                                          */
      __I  uint32_t GIF4       : 1;            /*!< [16..16] Global interrupt flag of channel 4                               */
      __I  uint32_t FTFIF4     : 1;            /*!< [17..17] Full Transfer finish flag of channe 4                            */
      __I  uint32_t HTFIF4     : 1;            /*!< [18..18] Half transfer finish flag of channel 4                           */
      __I  uint32_t ERRIF4     : 1;            /*!< [19..19] Error flag of channel 4                                          */
            uint32_t            : 12;
    } INTF_b;
  } ;

  union {
    __O  uint32_t INTC;                        /*!< (@ 0x00000004) Interrupt flag clear register                              */

    struct {
      __O  uint32_t GIFC0      : 1;            /*!< [0..0] Clear global interrupt flag of channel 0                           */
      __O  uint32_t FTFIFC0    : 1;            /*!< [1..1] Clear bit for full transfer finish flag of channel 0               */
      __O  uint32_t HTFIFC0    : 1;            /*!< [2..2] Clear bit for half transfer finish flag of channel 0               */
      __O  uint32_t ERRIFC0    : 1;            /*!< [3..3] Clear bit for error flag of channel 0                              */
      __O  uint32_t GIFC1      : 1;            /*!< [4..4] Clear global interrupt flag of channel 1                           */
      __O  uint32_t FTFIFC1    : 1;            /*!< [5..5] Clear bit for full transfer finish flag of channel 1               */
      __O  uint32_t HTFIFC1    : 1;            /*!< [6..6] Clear bit for half transfer finish flag of channel 1               */
      __O  uint32_t ERRIFC1    : 1;            /*!< [7..7] Clear bit for error flag of channel 1                              */
      __O  uint32_t GIFC2      : 1;            /*!< [8..8] Clear global interrupt flag of channel 2                           */
      __O  uint32_t FTFIFC2    : 1;            /*!< [9..9] Clear bit for full transfer finish flag of channel 2               */
      __O  uint32_t HTFIFC2    : 1;            /*!< [10..10] Clear bit for half transfer finish flag of channel
                                                     2                                                                         */
      __O  uint32_t ERRIFC2    : 1;            /*!< [11..11] Clear bit for error flag of channel 2                            */
      __O  uint32_t GIFC3      : 1;            /*!< [12..12] Clear global interrupt flag of channel 3                         */
      __O  uint32_t FTFIFC3    : 1;            /*!< [13..13] Clear bit for full transfer finish flag of channel
                                                     3                                                                         */
      __O  uint32_t HTFIFC3    : 1;            /*!< [14..14] Clear bit for half transfer finish flag of channel
                                                     3                                                                         */
      __O  uint32_t ERRIFC3    : 1;            /*!< [15..15] Clear bit for error flag of channel 3                            */
      __O  uint32_t GIFC4      : 1;            /*!< [16..16] Clear global interrupt flag of channel 4                         */
      __O  uint32_t FTFIFC4    : 1;            /*!< [17..17] Clear bit for full transfer finish flag of channel
                                                     4                                                                         */
      __O  uint32_t HTFIFC4    : 1;            /*!< [18..18] Clear bit for half transfer finish flag of channel
                                                     4                                                                         */
      __O  uint32_t ERRIFC4    : 1;            /*!< [19..19] Clear bit for error flag of channel 4                            */
            uint32_t            : 12;
    } INTC_b;
  } ;

  union {
    __IO uint32_t CH0CTL;                      /*!< (@ 0x00000008) Channel 0 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH0CTL_b;
  } ;

  union {
    __IO uint32_t CH0CNT;                      /*!< (@ 0x0000000C) Channel 0 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH0CNT_b;
  } ;

  union {
    __IO uint32_t CH0PADDR;                    /*!< (@ 0x00000010) Channel 0 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH0PADDR_b;
  } ;

  union {
    __IO uint32_t CH0MADDR;                    /*!< (@ 0x00000014) Channel 0 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH0MADDR_b;
  } ;
  __I  uint32_t  RESERVED;

  union {
    __IO uint32_t CH1CTL;                      /*!< (@ 0x0000001C) Channel 1 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH1CTL_b;
  } ;

  union {
    __IO uint32_t CH1CNT;                      /*!< (@ 0x00000020) Channel 1 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH1CNT_b;
  } ;

  union {
    __IO uint32_t CH1PADDR;                    /*!< (@ 0x00000024) Channel 1 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH1PADDR_b;
  } ;

  union {
    __IO uint32_t CH1MADDR;                    /*!< (@ 0x00000028) Channel 1 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH1MADDR_b;
  } ;
  __I  uint32_t  RESERVED1;

  union {
    __IO uint32_t CH2CTL;                      /*!< (@ 0x00000030) Channel 2 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH2CTL_b;
  } ;

  union {
    __IO uint32_t CH2CNT;                      /*!< (@ 0x00000034) Channel 2 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH2CNT_b;
  } ;

  union {
    __IO uint32_t CH2PADDR;                    /*!< (@ 0x00000038) Channel 2 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH2PADDR_b;
  } ;

  union {
    __IO uint32_t CH2MADDR;                    /*!< (@ 0x0000003C) Channel 2 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH2MADDR_b;
  } ;
  __I  uint32_t  RESERVED2;

  union {
    __IO uint32_t CH3CTL;                      /*!< (@ 0x00000044) Channel 3 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH3CTL_b;
  } ;

  union {
    __IO uint32_t CH3CNT;                      /*!< (@ 0x00000048) Channel 3 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH3CNT_b;
  } ;

  union {
    __IO uint32_t CH3PADDR;                    /*!< (@ 0x0000004C) Channel 3 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH3PADDR_b;
  } ;

  union {
    __IO uint32_t CH3MADDR;                    /*!< (@ 0x00000050) Channel 3 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH3MADDR_b;
  } ;
  __I  uint32_t  RESERVED3;

  union {
    __IO uint32_t CH4CTL;                      /*!< (@ 0x00000058) Channel 4 control register                                 */

    struct {
      __IO uint32_t CHEN       : 1;            /*!< [0..0] Channel enable                                                     */
      __IO uint32_t FTFIE      : 1;            /*!< [1..1] Enable bit for channel full transfer finish interrupt              */
      __IO uint32_t HTFIE      : 1;            /*!< [2..2] Enable bit for channel half transfer finish interrupt              */
      __IO uint32_t ERRIE      : 1;            /*!< [3..3] Enable bit for channel error interrupt                             */
      __IO uint32_t DIR        : 1;            /*!< [4..4] Transfer direction                                                 */
      __IO uint32_t CMEN       : 1;            /*!< [5..5] Circular mode enable                                               */
      __IO uint32_t PNAGA      : 1;            /*!< [6..6] Next address generation algorithm of peripheral                    */
      __IO uint32_t MNAGA      : 1;            /*!< [7..7] Next address generation algorithm of memory                        */
      __IO uint32_t PWIDTH     : 2;            /*!< [9..8] Transfer data size of peripheral                                   */
      __IO uint32_t MWIDTH     : 2;            /*!< [11..10] Transfer data size of memory                                     */
      __IO uint32_t PRIO       : 2;            /*!< [13..12] Priority level                                                   */
      __IO uint32_t M2M        : 1;            /*!< [14..14] Memory to Memory Mode                                            */
            uint32_t            : 17;
    } CH4CTL_b;
  } ;

  union {
    __IO uint32_t CH4CNT;                      /*!< (@ 0x0000005C) Channel 4 counter register                                 */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] Transfer counter                                                  */
            uint32_t            : 16;
    } CH4CNT_b;
  } ;

  union {
    __IO uint32_t CH4PADDR;                    /*!< (@ 0x00000060) Channel 4 peripheral base address register                 */

    struct {
      __IO uint32_t PADDR      : 32;           /*!< [31..0] Peripheral base address                                           */
    } CH4PADDR_b;
  } ;

  union {
    __IO uint32_t CH4MADDR;                    /*!< (@ 0x00000064) Channel 4 memory base address register                     */

    struct {
      __IO uint32_t MADDR      : 32;           /*!< [31..0] Memory base address                                               */
    } CH4MADDR_b;
  } ;
} DMA1_Type;                                    /*!< Size = 104 (0x68)                                                         */



/* =========================================================================================================================== */
/* ================                                           EXMC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief External memory controller (EXMC)
  */

typedef struct {                                /*!< (@ 0xA0000000) EXMC Structure                                             */

  union {
    __IO uint32_t SNCTL0;                      /*!< (@ 0x00000000) SRAM/NOR flash control register 0                          */

    struct {
      __IO uint32_t NRBKEN     : 1;            /*!< [0..0] NOR bank enable                                                    */
      __IO uint32_t NRMUX      : 1;            /*!< [1..1] NOR bank memory address/data multiplexing                          */
      __IO uint32_t NRTP       : 2;            /*!< [3..2] NOR bank memory type                                               */
      __IO uint32_t NRW        : 2;            /*!< [5..4] NOR bank memory data bus width                                     */
      __IO uint32_t NREN       : 1;            /*!< [6..6] NOR Flash access enable                                            */
            uint32_t            : 2;
      __IO uint32_t NRWTPOL    : 1;            /*!< [9..9] NWAIT signal polarity                                              */
            uint32_t            : 2;
      __IO uint32_t WREN       : 1;            /*!< [12..12] Write enable                                                     */
      __IO uint32_t NRWTEN     : 1;            /*!< [13..13] NWAIT signal enable                                              */
            uint32_t            : 1;
      __IO uint32_t ASYNCWAIT  : 1;            /*!< [15..15] Asynchronous wait                                                */
            uint32_t            : 16;
    } SNCTL0_b;
  } ;

  union {
    __IO uint32_t SNTCFG0;                     /*!< (@ 0x00000004) SRAM/NOR flash timing configuration register
                                                                    0                                                          */

    struct {
      __IO uint32_t ASET       : 4;            /*!< [3..0] Address setup time                                                 */
      __IO uint32_t AHLD       : 4;            /*!< [7..4] Address hold time                                                  */
      __IO uint32_t DSET       : 8;            /*!< [15..8] Data setup time                                                   */
      __IO uint32_t BUSLAT     : 4;            /*!< [19..16] Bus latency                                                      */
            uint32_t            : 12;
    } SNTCFG0_b;
  } ;

  union {
    __IO uint32_t SNCTL1;                      /*!< (@ 0x00000008) SRAM/NOR flash control register 1                          */

    struct {
      __IO uint32_t NRBKEN     : 1;            /*!< [0..0] NOR bank enable                                                    */
      __IO uint32_t NRMUX      : 1;            /*!< [1..1] NOR bank memory address/data multiplexing                          */
      __IO uint32_t NRTP       : 2;            /*!< [3..2] NOR bank memory type                                               */
      __IO uint32_t NRW        : 2;            /*!< [5..4] NOR bank memory data bus width                                     */
      __IO uint32_t NREN       : 1;            /*!< [6..6] NOR Flash access enable                                            */
            uint32_t            : 2;
      __IO uint32_t NRWTPOL    : 1;            /*!< [9..9] NWAIT signal polarity                                              */
            uint32_t            : 2;
      __IO uint32_t WREN       : 1;            /*!< [12..12] Write enable                                                     */
      __IO uint32_t NRWTEN     : 1;            /*!< [13..13] NWAIT signal enable                                              */
            uint32_t            : 1;
      __IO uint32_t ASYNCWAIT  : 1;            /*!< [15..15] Asynchronous wait                                                */
            uint32_t            : 16;
    } SNCTL1_b;
  } ;
} EXMC_Type;                                    /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                           EXTI                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief External interrupt/event
      controller (EXTI)
  */

typedef struct {                                /*!< (@ 0x40010400) EXTI Structure                                             */

  union {
    __IO uint32_t INTEN;                       /*!< (@ 0x00000000) Interrupt enable register (EXTI_INTEN)                     */

    struct {
      __IO uint32_t INTEN0     : 1;            /*!< [0..0] Enable Interrupt on line 0                                         */
      __IO uint32_t INTEN1     : 1;            /*!< [1..1] Enable Interrupt on line 1                                         */
      __IO uint32_t INTEN2     : 1;            /*!< [2..2] Enable Interrupt on line 2                                         */
      __IO uint32_t INTEN3     : 1;            /*!< [3..3] Enable Interrupt on line 3                                         */
      __IO uint32_t INTEN4     : 1;            /*!< [4..4] Enable Interrupt on line 4                                         */
      __IO uint32_t INTEN5     : 1;            /*!< [5..5] Enable Interrupt on line 5                                         */
      __IO uint32_t INTEN6     : 1;            /*!< [6..6] Enable Interrupt on line 6                                         */
      __IO uint32_t INTEN7     : 1;            /*!< [7..7] Enable Interrupt on line 7                                         */
      __IO uint32_t INTEN8     : 1;            /*!< [8..8] Enable Interrupt on line 8                                         */
      __IO uint32_t INTEN9     : 1;            /*!< [9..9] Enable Interrupt on line 9                                         */
      __IO uint32_t INTEN10    : 1;            /*!< [10..10] Enable Interrupt on line 10                                      */
      __IO uint32_t INTEN11    : 1;            /*!< [11..11] Enable Interrupt on line 11                                      */
      __IO uint32_t INTEN12    : 1;            /*!< [12..12] Enable Interrupt on line 12                                      */
      __IO uint32_t INTEN13    : 1;            /*!< [13..13] Enable Interrupt on line 13                                      */
      __IO uint32_t INTEN14    : 1;            /*!< [14..14] Enable Interrupt on line 14                                      */
      __IO uint32_t INTEN15    : 1;            /*!< [15..15] Enable Interrupt on line 15                                      */
      __IO uint32_t INTEN16    : 1;            /*!< [16..16] Enable Interrupt on line 16                                      */
      __IO uint32_t INTEN17    : 1;            /*!< [17..17] Enable Interrupt on line 17                                      */
      __IO uint32_t INTEN18    : 1;            /*!< [18..18] Enable Interrupt on line 18                                      */
            uint32_t            : 13;
    } INTEN_b;
  } ;

  union {
    __IO uint32_t EVEN;                        /*!< (@ 0x00000004) Event enable register (EXTI_EVEN)                          */

    struct {
      __IO uint32_t EVEN0      : 1;            /*!< [0..0] Enable Event on line 0                                             */
      __IO uint32_t EVEN1      : 1;            /*!< [1..1] Enable Event on line 1                                             */
      __IO uint32_t EVEN2      : 1;            /*!< [2..2] Enable Event on line 2                                             */
      __IO uint32_t EVEN3      : 1;            /*!< [3..3] Enable Event on line 3                                             */
      __IO uint32_t EVEN4      : 1;            /*!< [4..4] Enable Event on line 4                                             */
      __IO uint32_t EVEN5      : 1;            /*!< [5..5] Enable Event on line 5                                             */
      __IO uint32_t EVEN6      : 1;            /*!< [6..6] Enable Event on line 6                                             */
      __IO uint32_t EVEN7      : 1;            /*!< [7..7] Enable Event on line 7                                             */
      __IO uint32_t EVEN8      : 1;            /*!< [8..8] Enable Event on line 8                                             */
      __IO uint32_t EVEN9      : 1;            /*!< [9..9] Enable Event on line 9                                             */
      __IO uint32_t EVEN10     : 1;            /*!< [10..10] Enable Event on line 10                                          */
      __IO uint32_t EVEN11     : 1;            /*!< [11..11] Enable Event on line 11                                          */
      __IO uint32_t EVEN12     : 1;            /*!< [12..12] Enable Event on line 12                                          */
      __IO uint32_t EVEN13     : 1;            /*!< [13..13] Enable Event on line 13                                          */
      __IO uint32_t EVEN14     : 1;            /*!< [14..14] Enable Event on line 14                                          */
      __IO uint32_t EVEN15     : 1;            /*!< [15..15] Enable Event on line 15                                          */
      __IO uint32_t EVEN16     : 1;            /*!< [16..16] Enable Event on line 16                                          */
      __IO uint32_t EVEN17     : 1;            /*!< [17..17] Enable Event on line 17                                          */
      __IO uint32_t EVEN18     : 1;            /*!< [18..18] Enable Event on line 18                                          */
            uint32_t            : 13;
    } EVEN_b;
  } ;

  union {
    __IO uint32_t RTEN;                        /*!< (@ 0x00000008) Rising Edge Trigger Enable register (EXTI_RTEN)            */

    struct {
      __IO uint32_t RTEN0      : 1;            /*!< [0..0] Rising edge trigger enable of line 0                               */
      __IO uint32_t RTEN1      : 1;            /*!< [1..1] Rising edge trigger enable of line 1                               */
      __IO uint32_t RTEN2      : 1;            /*!< [2..2] Rising edge trigger enable of line 2                               */
      __IO uint32_t RTEN3      : 1;            /*!< [3..3] Rising edge trigger enable of line 3                               */
      __IO uint32_t RTEN4      : 1;            /*!< [4..4] Rising edge trigger enable of line 4                               */
      __IO uint32_t RTEN5      : 1;            /*!< [5..5] Rising edge trigger enable of line 5                               */
      __IO uint32_t RTEN6      : 1;            /*!< [6..6] Rising edge trigger enable of line 6                               */
      __IO uint32_t RTEN7      : 1;            /*!< [7..7] Rising edge trigger enable of line 7                               */
      __IO uint32_t RTEN8      : 1;            /*!< [8..8] Rising edge trigger enable of line 8                               */
      __IO uint32_t RTEN9      : 1;            /*!< [9..9] Rising edge trigger enable of line 9                               */
      __IO uint32_t RTEN10     : 1;            /*!< [10..10] Rising edge trigger enable of line 10                            */
      __IO uint32_t RTEN11     : 1;            /*!< [11..11] Rising edge trigger enable of line 11                            */
      __IO uint32_t RTEN12     : 1;            /*!< [12..12] Rising edge trigger enable of line 12                            */
      __IO uint32_t RTEN13     : 1;            /*!< [13..13] Rising edge trigger enable of line 13                            */
      __IO uint32_t RTEN14     : 1;            /*!< [14..14] Rising edge trigger enable of line 14                            */
      __IO uint32_t RTEN15     : 1;            /*!< [15..15] Rising edge trigger enable of line 15                            */
      __IO uint32_t RTEN16     : 1;            /*!< [16..16] Rising edge trigger enable of line 16                            */
      __IO uint32_t RTEN17     : 1;            /*!< [17..17] Rising edge trigger enable of line 17                            */
      __IO uint32_t RTEN18     : 1;            /*!< [18..18] Rising edge trigger enable of line 18                            */
            uint32_t            : 13;
    } RTEN_b;
  } ;

  union {
    __IO uint32_t FTEN;                        /*!< (@ 0x0000000C) Falling Egde Trigger Enable register (EXTI_FTEN)           */

    struct {
      __IO uint32_t FTEN0      : 1;            /*!< [0..0] Falling edge trigger enable of line 0                              */
      __IO uint32_t FTEN1      : 1;            /*!< [1..1] Falling edge trigger enable of line 1                              */
      __IO uint32_t FTEN2      : 1;            /*!< [2..2] Falling edge trigger enable of line 2                              */
      __IO uint32_t FTEN3      : 1;            /*!< [3..3] Falling edge trigger enable of line 3                              */
      __IO uint32_t FTEN4      : 1;            /*!< [4..4] Falling edge trigger enable of line 4                              */
      __IO uint32_t FTEN5      : 1;            /*!< [5..5] Falling edge trigger enable of line 5                              */
      __IO uint32_t FTEN6      : 1;            /*!< [6..6] Falling edge trigger enable of line 6                              */
      __IO uint32_t FTEN7      : 1;            /*!< [7..7] Falling edge trigger enable of line 7                              */
      __IO uint32_t FTEN8      : 1;            /*!< [8..8] Falling edge trigger enable of line 8                              */
      __IO uint32_t FTEN9      : 1;            /*!< [9..9] Falling edge trigger enable of line 9                              */
      __IO uint32_t FTEN10     : 1;            /*!< [10..10] Falling edge trigger enable of line 10                           */
      __IO uint32_t FTEN11     : 1;            /*!< [11..11] Falling edge trigger enable of line 11                           */
      __IO uint32_t FTEN12     : 1;            /*!< [12..12] Falling edge trigger enable of line 12                           */
      __IO uint32_t FTEN13     : 1;            /*!< [13..13] Falling edge trigger enable of line 13                           */
      __IO uint32_t FTEN14     : 1;            /*!< [14..14] Falling edge trigger enable of line 14                           */
      __IO uint32_t FTEN15     : 1;            /*!< [15..15] Falling edge trigger enable of line 15                           */
      __IO uint32_t FTEN16     : 1;            /*!< [16..16] Falling edge trigger enable of line 16                           */
      __IO uint32_t FTEN17     : 1;            /*!< [17..17] Falling edge trigger enable of line 17                           */
      __IO uint32_t FTEN18     : 1;            /*!< [18..18] Falling edge trigger enable of line 18                           */
            uint32_t            : 13;
    } FTEN_b;
  } ;

  union {
    __IO uint32_t SWIEV;                       /*!< (@ 0x00000010) Software interrupt event register (EXTI_SWIEV)             */

    struct {
      __IO uint32_t SWIEV0     : 1;            /*!< [0..0] Interrupt/Event software trigger on line 0                         */
      __IO uint32_t SWIEV1     : 1;            /*!< [1..1] Interrupt/Event software trigger on line 1                         */
      __IO uint32_t SWIEV2     : 1;            /*!< [2..2] Interrupt/Event software trigger on line 2                         */
      __IO uint32_t SWIEV3     : 1;            /*!< [3..3] Interrupt/Event software trigger on line 3                         */
      __IO uint32_t SWIEV4     : 1;            /*!< [4..4] Interrupt/Event software trigger on line 4                         */
      __IO uint32_t SWIEV5     : 1;            /*!< [5..5] Interrupt/Event software trigger on line 5                         */
      __IO uint32_t SWIEV6     : 1;            /*!< [6..6] Interrupt/Event software trigger on line 6                         */
      __IO uint32_t SWIEV7     : 1;            /*!< [7..7] Interrupt/Event software trigger on line 7                         */
      __IO uint32_t SWIEV8     : 1;            /*!< [8..8] Interrupt/Event software trigger on line 8                         */
      __IO uint32_t SWIEV9     : 1;            /*!< [9..9] Interrupt/Event software trigger on line 9                         */
      __IO uint32_t SWIEV10    : 1;            /*!< [10..10] Interrupt/Event software trigger on line 10                      */
      __IO uint32_t SWIEV11    : 1;            /*!< [11..11] Interrupt/Event software trigger on line 11                      */
      __IO uint32_t SWIEV12    : 1;            /*!< [12..12] Interrupt/Event software trigger on line 12                      */
      __IO uint32_t SWIEV13    : 1;            /*!< [13..13] Interrupt/Event software trigger on line 13                      */
      __IO uint32_t SWIEV14    : 1;            /*!< [14..14] Interrupt/Event software trigger on line 14                      */
      __IO uint32_t SWIEV15    : 1;            /*!< [15..15] Interrupt/Event software trigger on line 15                      */
      __IO uint32_t SWIEV16    : 1;            /*!< [16..16] Interrupt/Event software trigger on line 16                      */
      __IO uint32_t SWIEV17    : 1;            /*!< [17..17] Interrupt/Event software trigger on line 17                      */
      __IO uint32_t SWIEV18    : 1;            /*!< [18..18] Interrupt/Event software trigger on line 18                      */
            uint32_t            : 13;
    } SWIEV_b;
  } ;

  union {
    __IO uint32_t PD;                          /*!< (@ 0x00000014) Pending register (EXTI_PD)                                 */

    struct {
      __IO uint32_t PD0        : 1;            /*!< [0..0] Interrupt pending status of line 0                                 */
      __IO uint32_t PD1        : 1;            /*!< [1..1] Interrupt pending status of line 1                                 */
      __IO uint32_t PD2        : 1;            /*!< [2..2] Interrupt pending status of line 2                                 */
      __IO uint32_t PD3        : 1;            /*!< [3..3] Interrupt pending status of line 3                                 */
      __IO uint32_t PD4        : 1;            /*!< [4..4] Interrupt pending status of line 4                                 */
      __IO uint32_t PD5        : 1;            /*!< [5..5] Interrupt pending status of line 5                                 */
      __IO uint32_t PD6        : 1;            /*!< [6..6] Interrupt pending status of line 6                                 */
      __IO uint32_t PD7        : 1;            /*!< [7..7] Interrupt pending status of line 7                                 */
      __IO uint32_t PD8        : 1;            /*!< [8..8] Interrupt pending status of line 8                                 */
      __IO uint32_t PD9        : 1;            /*!< [9..9] Interrupt pending status of line 9                                 */
      __IO uint32_t PD10       : 1;            /*!< [10..10] Interrupt pending status of line 10                              */
      __IO uint32_t PD11       : 1;            /*!< [11..11] Interrupt pending status of line 11                              */
      __IO uint32_t PD12       : 1;            /*!< [12..12] Interrupt pending status of line 12                              */
      __IO uint32_t PD13       : 1;            /*!< [13..13] Interrupt pending status of line 13                              */
      __IO uint32_t PD14       : 1;            /*!< [14..14] Interrupt pending status of line 14                              */
      __IO uint32_t PD15       : 1;            /*!< [15..15] Interrupt pending status of line 15                              */
      __IO uint32_t PD16       : 1;            /*!< [16..16] Interrupt pending status of line 16                              */
      __IO uint32_t PD17       : 1;            /*!< [17..17] Interrupt pending status of line 17                              */
      __IO uint32_t PD18       : 1;            /*!< [18..18] Interrupt pending status of line 18                              */
            uint32_t            : 13;
    } PD_b;
  } ;
} EXTI_Type;                                    /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                            FMC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief FMC (FMC)
  */

typedef struct {                                /*!< (@ 0x40022000) FMC Structure                                              */

  union {
    __IO uint32_t WS;                          /*!< (@ 0x00000000) wait state counter register                                */

    struct {
      __IO uint32_t WSCNT      : 3;            /*!< [2..0] wait state counter register                                        */
            uint32_t            : 29;
    } WS_b;
  } ;

  union {
    __O  uint32_t KEY0;                        /*!< (@ 0x00000004) Unlock key register 0                                      */

    struct {
      __O  uint32_t KEY        : 32;           /*!< [31..0] FMC_CTL0 unlock key                                               */
    } KEY0_b;
  } ;

  union {
    __O  uint32_t OBKEY;                       /*!< (@ 0x00000008) Option byte unlock key register                            */

    struct {
      __O  uint32_t OBKEY      : 32;           /*!< [31..0] FMC_ CTL0 option byte operation unlock register                   */
    } OBKEY_b;
  } ;

  union {
    __IO uint32_t STAT0;                       /*!< (@ 0x0000000C) Status register 0                                          */

    struct {
      __I  uint32_t BUSY       : 1;            /*!< [0..0] The flash is busy bit                                              */
            uint32_t            : 1;
      __IO uint32_t PGERR      : 1;            /*!< [2..2] Program error flag bit                                             */
            uint32_t            : 1;
      __IO uint32_t WPERR      : 1;            /*!< [4..4] Erase/Program protection error flag bit                            */
      __IO uint32_t ENDF       : 1;            /*!< [5..5] End of operation flag bit                                          */
            uint32_t            : 26;
    } STAT0_b;
  } ;

  union {
    __IO uint32_t CTL0;                        /*!< (@ 0x00000010) Control register 0                                         */

    struct {
      __IO uint32_t PG         : 1;            /*!< [0..0] Main flash program for bank0 command bit                           */
      __IO uint32_t PER        : 1;            /*!< [1..1] Main flash page erase for bank0 command bit                        */
      __IO uint32_t MER        : 1;            /*!< [2..2] Main flash mass erase for bank0 command bit                        */
            uint32_t            : 1;
      __IO uint32_t OBPG       : 1;            /*!< [4..4] Option bytes program command bit                                   */
      __IO uint32_t OBER       : 1;            /*!< [5..5] Option bytes erase command bit                                     */
      __IO uint32_t START      : 1;            /*!< [6..6] Send erase command to FMC bit                                      */
      __IO uint32_t LK         : 1;            /*!< [7..7] FMC_CTL0 lock bit                                                  */
            uint32_t            : 1;
      __IO uint32_t OBWEN      : 1;            /*!< [9..9] Option byte erase/program enable bit                               */
      __IO uint32_t ERRIE      : 1;            /*!< [10..10] Error interrupt enable bit                                       */
            uint32_t            : 1;
      __IO uint32_t ENDIE      : 1;            /*!< [12..12] End of operation interrupt enable bit                            */
            uint32_t            : 19;
    } CTL0_b;
  } ;

  union {
    __O  uint32_t ADDR0;                       /*!< (@ 0x00000014) Address register 0                                         */

    struct {
      __O  uint32_t ADDR       : 32;           /*!< [31..0] Flash erase/program command address bits                          */
    } ADDR0_b;
  } ;
  __I  uint32_t  RESERVED;

  union {
    __I  uint32_t OBSTAT;                      /*!< (@ 0x0000001C) Option byte status register                                */

    struct {
      __I  uint32_t OBERR      : 1;            /*!< [0..0] Option bytes read error bit                                        */
      __I  uint32_t SPC        : 1;            /*!< [1..1] Option bytes security protection code                              */
      __I  uint32_t USER       : 8;            /*!< [9..2] Store USER of option bytes block after system reset                */
      __I  uint32_t DATA       : 16;           /*!< [25..10] Store DATA[15:0] of option bytes block after system
                                                     reset                                                                     */
            uint32_t            : 6;
    } OBSTAT_b;
  } ;

  union {
    __I  uint32_t WP;                          /*!< (@ 0x00000020) Erase/Program Protection register                          */

    struct {
      __I  uint32_t WP         : 32;           /*!< [31..0] Store WP[31:0] of option bytes block after system reset           */
    } WP_b;
  } ;
  __I  uint32_t  RESERVED1[55];

  union {
    __I  uint32_t PID;                         /*!< (@ 0x00000100) Product ID register                                        */

    struct {
      __I  uint32_t PID        : 32;           /*!< [31..0] Product reserved ID code register                                 */
    } PID_b;
  } ;
} FMC_Type;                                     /*!< Size = 260 (0x104)                                                        */



/* =========================================================================================================================== */
/* ================                                           FWDGT                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief free watchdog timer (FWDGT)
  */

typedef struct {                                /*!< (@ 0x40003000) FWDGT Structure                                            */

  union {
    __O  uint32_t CTL;                         /*!< (@ 0x00000000) Control register                                           */

    struct {
      __O  uint32_t CMD        : 16;           /*!< [15..0] Key value                                                         */
            uint32_t            : 16;
    } CTL_b;
  } ;

  union {
    __IO uint32_t PSC;                         /*!< (@ 0x00000004) Prescaler register                                         */

    struct {
      __IO uint32_t PSC        : 3;            /*!< [2..0] Free watchdog timer prescaler selection                            */
            uint32_t            : 29;
    } PSC_b;
  } ;

  union {
    __IO uint32_t RLD;                         /*!< (@ 0x00000008) Reload register                                            */

    struct {
      __IO uint32_t RLD        : 12;           /*!< [11..0] Free watchdog timer counter reload value                          */
            uint32_t            : 20;
    } RLD_b;
  } ;

  union {
    __I  uint32_t STAT;                        /*!< (@ 0x0000000C) Status register                                            */

    struct {
      __I  uint32_t PUD        : 1;            /*!< [0..0] Free watchdog timer prescaler value update                         */
      __I  uint32_t RUD        : 1;            /*!< [1..1] Free watchdog timer counter reload value update                    */
            uint32_t            : 30;
    } STAT_b;
  } ;
} FWDGT_Type;                                   /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief General-purpose I/Os (GPIO)
  */

typedef struct {                                /*!< (@ 0x40010800) GPIO Structure                                            */

  union {
    __IO uint32_t CTL0;                        /*!< (@ 0x00000000) port control register 0                                    */

    struct {
      __IO uint32_t MD0        : 2;            /*!< [1..0] Port x mode bits (x = 0)                                           */
      __IO uint32_t CTL0       : 2;            /*!< [3..2] Port x configuration bits (x = 0)                                  */
      __IO uint32_t MD1        : 2;            /*!< [5..4] Port x mode bits (x = 1)                                           */
      __IO uint32_t CTL1       : 2;            /*!< [7..6] Port x configuration bits (x = 1)                                  */
      __IO uint32_t MD2        : 2;            /*!< [9..8] Port x mode bits (x = 2 )                                          */
      __IO uint32_t CTL2       : 2;            /*!< [11..10] Port x configuration bits (x = 2)                                */
      __IO uint32_t MD3        : 2;            /*!< [13..12] Port x mode bits (x = 3 )                                        */
      __IO uint32_t CTL3       : 2;            /*!< [15..14] Port x configuration bits (x = 3)                                */
      __IO uint32_t MD4        : 2;            /*!< [17..16] Port x mode bits (x = 4)                                         */
      __IO uint32_t CTL4       : 2;            /*!< [19..18] Port x configuration bits (x = 4)                                */
      __IO uint32_t MD5        : 2;            /*!< [21..20] Port x mode bits (x = 5)                                         */
      __IO uint32_t CTL5       : 2;            /*!< [23..22] Port x configuration bits (x = 5)                                */
      __IO uint32_t MD6        : 2;            /*!< [25..24] Port x mode bits (x = 6)                                         */
      __IO uint32_t CTL6       : 2;            /*!< [27..26] Port x configuration bits (x = 6)                                */
      __IO uint32_t MD7        : 2;            /*!< [29..28] Port x mode bits (x = 7)                                         */
      __IO uint32_t CTL7       : 2;            /*!< [31..30] Port x configuration bits (x = 7)                                */
    } CTL0_b;
  } ;

  union {
    __IO uint32_t CTL1;                        /*!< (@ 0x00000004) port control register 1                                    */

    struct {
      __IO uint32_t MD8        : 2;            /*!< [1..0] Port x mode bits (x = 8)                                           */
      __IO uint32_t CTL8       : 2;            /*!< [3..2] Port x configuration bits (x = 8)                                  */
      __IO uint32_t MD9        : 2;            /*!< [5..4] Port x mode bits (x = 9)                                           */
      __IO uint32_t CTL9       : 2;            /*!< [7..6] Port x configuration bits (x = 9)                                  */
      __IO uint32_t MD10       : 2;            /*!< [9..8] Port x mode bits (x = 10 )                                         */
      __IO uint32_t CTL10      : 2;            /*!< [11..10] Port x configuration bits (x = 10)                               */
      __IO uint32_t MD11       : 2;            /*!< [13..12] Port x mode bits (x = 11 )                                       */
      __IO uint32_t CTL11      : 2;            /*!< [15..14] Port x configuration bits (x = 11)                               */
      __IO uint32_t MD12       : 2;            /*!< [17..16] Port x mode bits (x = 12)                                        */
      __IO uint32_t CTL12      : 2;            /*!< [19..18] Port x configuration bits (x = 12)                               */
      __IO uint32_t MD13       : 2;            /*!< [21..20] Port x mode bits (x = 13)                                        */
      __IO uint32_t CTL13      : 2;            /*!< [23..22] Port x configuration bits (x = 13)                               */
      __IO uint32_t MD14       : 2;            /*!< [25..24] Port x mode bits (x = 14)                                        */
      __IO uint32_t CTL14      : 2;            /*!< [27..26] Port x configuration bits (x = 14)                               */
      __IO uint32_t MD15       : 2;            /*!< [29..28] Port x mode bits (x = 15)                                        */
      __IO uint32_t CTL15      : 2;            /*!< [31..30] Port x configuration bits (x = 15)                               */
    } CTL1_b;
  } ;

  union {
    __I  uint32_t ISTAT;                       /*!< (@ 0x00000008) Port input status register                                 */

    struct {
      __I  uint32_t ISTAT0     : 1;            /*!< [0..0] Port input status                                                  */
      __I  uint32_t ISTAT1     : 1;            /*!< [1..1] Port input status                                                  */
      __I  uint32_t ISTAT2     : 1;            /*!< [2..2] Port input status                                                  */
      __I  uint32_t ISTAT3     : 1;            /*!< [3..3] Port input status                                                  */
      __I  uint32_t ISTAT4     : 1;            /*!< [4..4] Port input status                                                  */
      __I  uint32_t ISTAT5     : 1;            /*!< [5..5] Port input status                                                  */
      __I  uint32_t ISTAT6     : 1;            /*!< [6..6] Port input status                                                  */
      __I  uint32_t ISTAT7     : 1;            /*!< [7..7] Port input status                                                  */
      __I  uint32_t ISTAT8     : 1;            /*!< [8..8] Port input status                                                  */
      __I  uint32_t ISTAT9     : 1;            /*!< [9..9] Port input status                                                  */
      __I  uint32_t ISTAT10    : 1;            /*!< [10..10] Port input status                                                */
      __I  uint32_t ISTAT11    : 1;            /*!< [11..11] Port input status                                                */
      __I  uint32_t ISTAT12    : 1;            /*!< [12..12] Port input status                                                */
      __I  uint32_t ISTAT13    : 1;            /*!< [13..13] Port input status                                                */
      __I  uint32_t ISTAT14    : 1;            /*!< [14..14] Port input status                                                */
      __I  uint32_t ISTAT15    : 1;            /*!< [15..15] Port input status                                                */
            uint32_t            : 16;
    } ISTAT_b;
  } ;

  union {
    __IO uint32_t OCTL;                        /*!< (@ 0x0000000C) Port output control register                               */

    struct {
      __IO uint32_t OCTL0      : 1;            /*!< [0..0] Port output control                                                */
      __IO uint32_t OCTL1      : 1;            /*!< [1..1] Port output control                                                */
      __IO uint32_t OCTL2      : 1;            /*!< [2..2] Port output control                                                */
      __IO uint32_t OCTL3      : 1;            /*!< [3..3] Port output control                                                */
      __IO uint32_t OCTL4      : 1;            /*!< [4..4] Port output control                                                */
      __IO uint32_t OCTL5      : 1;            /*!< [5..5] Port output control                                                */
      __IO uint32_t OCTL6      : 1;            /*!< [6..6] Port output control                                                */
      __IO uint32_t OCTL7      : 1;            /*!< [7..7] Port output control                                                */
      __IO uint32_t OCTL8      : 1;            /*!< [8..8] Port output control                                                */
      __IO uint32_t OCTL9      : 1;            /*!< [9..9] Port output control                                                */
      __IO uint32_t OCTL10     : 1;            /*!< [10..10] Port output control                                              */
      __IO uint32_t OCTL11     : 1;            /*!< [11..11] Port output control                                              */
      __IO uint32_t OCTL12     : 1;            /*!< [12..12] Port output control                                              */
      __IO uint32_t OCTL13     : 1;            /*!< [13..13] Port output control                                              */
      __IO uint32_t OCTL14     : 1;            /*!< [14..14] Port output control                                              */
      __IO uint32_t OCTL15     : 1;            /*!< [15..15] Port output control                                              */
            uint32_t            : 16;
    } OCTL_b;
  } ;

  union {
    __O  uint32_t BOP;                         /*!< (@ 0x00000010) Port bit operate register                                  */

    struct {
      __O  uint32_t BOP0       : 1;            /*!< [0..0] Port 0 Set bit                                                     */
      __O  uint32_t BOP1       : 1;            /*!< [1..1] Port 1 Set bit                                                     */
      __O  uint32_t BOP2       : 1;            /*!< [2..2] Port 2 Set bit                                                     */
      __O  uint32_t BOP3       : 1;            /*!< [3..3] Port 3 Set bit                                                     */
      __O  uint32_t BOP4       : 1;            /*!< [4..4] Port 4 Set bit                                                     */
      __O  uint32_t BOP5       : 1;            /*!< [5..5] Port 5 Set bit                                                     */
      __O  uint32_t BOP6       : 1;            /*!< [6..6] Port 6 Set bit                                                     */
      __O  uint32_t BOP7       : 1;            /*!< [7..7] Port 7 Set bit                                                     */
      __O  uint32_t BOP8       : 1;            /*!< [8..8] Port 8 Set bit                                                     */
      __O  uint32_t BOP9       : 1;            /*!< [9..9] Port 9 Set bit                                                     */
      __O  uint32_t BOP10      : 1;            /*!< [10..10] Port 10 Set bit                                                  */
      __O  uint32_t BOP11      : 1;            /*!< [11..11] Port 11 Set bit                                                  */
      __O  uint32_t BOP12      : 1;            /*!< [12..12] Port 12 Set bit                                                  */
      __O  uint32_t BOP13      : 1;            /*!< [13..13] Port 13 Set bit                                                  */
      __O  uint32_t BOP14      : 1;            /*!< [14..14] Port 14 Set bit                                                  */
      __O  uint32_t BOP15      : 1;            /*!< [15..15] Port 15 Set bit                                                  */
      __O  uint32_t CR0        : 1;            /*!< [16..16] Port 0 Clear bit                                                 */
      __O  uint32_t CR1        : 1;            /*!< [17..17] Port 1 Clear bit                                                 */
      __O  uint32_t CR2        : 1;            /*!< [18..18] Port 2 Clear bit                                                 */
      __O  uint32_t CR3        : 1;            /*!< [19..19] Port 3 Clear bit                                                 */
      __O  uint32_t CR4        : 1;            /*!< [20..20] Port 4 Clear bit                                                 */
      __O  uint32_t CR5        : 1;            /*!< [21..21] Port 5 Clear bit                                                 */
      __O  uint32_t CR6        : 1;            /*!< [22..22] Port 6 Clear bit                                                 */
      __O  uint32_t CR7        : 1;            /*!< [23..23] Port 7 Clear bit                                                 */
      __O  uint32_t CR8        : 1;            /*!< [24..24] Port 8 Clear bit                                                 */
      __O  uint32_t CR9        : 1;            /*!< [25..25] Port 9 Clear bit                                                 */
      __O  uint32_t CR10       : 1;            /*!< [26..26] Port 10 Clear bit                                                */
      __O  uint32_t CR11       : 1;            /*!< [27..27] Port 11 Clear bit                                                */
      __O  uint32_t CR12       : 1;            /*!< [28..28] Port 12 Clear bit                                                */
      __O  uint32_t CR13       : 1;            /*!< [29..29] Port 13 Clear bit                                                */
      __O  uint32_t CR14       : 1;            /*!< [30..30] Port 14 Clear bit                                                */
      __O  uint32_t CR15       : 1;            /*!< [31..31] Port 15 Clear bit                                                */
    } BOP_b;
  } ;

  union {
    __O  uint32_t BC;                          /*!< (@ 0x00000014) Port bit clear register                                    */

    struct {
      __O  uint32_t CR0        : 1;            /*!< [0..0] Port 0 Clear bit                                                   */
      __O  uint32_t CR1        : 1;            /*!< [1..1] Port 1 Clear bit                                                   */
      __O  uint32_t CR2        : 1;            /*!< [2..2] Port 2 Clear bit                                                   */
      __O  uint32_t CR3        : 1;            /*!< [3..3] Port 3 Clear bit                                                   */
      __O  uint32_t CR4        : 1;            /*!< [4..4] Port 4 Clear bit                                                   */
      __O  uint32_t CR5        : 1;            /*!< [5..5] Port 5 Clear bit                                                   */
      __O  uint32_t CR6        : 1;            /*!< [6..6] Port 6 Clear bit                                                   */
      __O  uint32_t CR7        : 1;            /*!< [7..7] Port 7 Clear bit                                                   */
      __O  uint32_t CR8        : 1;            /*!< [8..8] Port 8 Clear bit                                                   */
      __O  uint32_t CR9        : 1;            /*!< [9..9] Port 9 Clear bit                                                   */
      __O  uint32_t CR10       : 1;            /*!< [10..10] Port 10 Clear bit                                                */
      __O  uint32_t CR11       : 1;            /*!< [11..11] Port 11 Clear bit                                                */
      __O  uint32_t CR12       : 1;            /*!< [12..12] Port 12 Clear bit                                                */
      __O  uint32_t CR13       : 1;            /*!< [13..13] Port 13 Clear bit                                                */
      __O  uint32_t CR14       : 1;            /*!< [14..14] Port 14 Clear bit                                                */
      __O  uint32_t CR15       : 1;            /*!< [15..15] Port 15 Clear bit                                                */
            uint32_t            : 16;
    } BC_b;
  } ;

  union {
    __IO uint32_t LOCK;                        /*!< (@ 0x00000018) GPIO port configuration lock register                      */

    struct {
      __IO uint32_t LK0        : 1;            /*!< [0..0] Port Lock bit 0                                                    */
      __IO uint32_t LK1        : 1;            /*!< [1..1] Port Lock bit 1                                                    */
      __IO uint32_t LK2        : 1;            /*!< [2..2] Port Lock bit 2                                                    */
      __IO uint32_t LK3        : 1;            /*!< [3..3] Port Lock bit 3                                                    */
      __IO uint32_t LK4        : 1;            /*!< [4..4] Port Lock bit 4                                                    */
      __IO uint32_t LK5        : 1;            /*!< [5..5] Port Lock bit 5                                                    */
      __IO uint32_t LK6        : 1;            /*!< [6..6] Port Lock bit 6                                                    */
      __IO uint32_t LK7        : 1;            /*!< [7..7] Port Lock bit 7                                                    */
      __IO uint32_t LK8        : 1;            /*!< [8..8] Port Lock bit 8                                                    */
      __IO uint32_t LK9        : 1;            /*!< [9..9] Port Lock bit 9                                                    */
      __IO uint32_t LK10       : 1;            /*!< [10..10] Port Lock bit 10                                                 */
      __IO uint32_t LK11       : 1;            /*!< [11..11] Port Lock bit 11                                                 */
      __IO uint32_t LK12       : 1;            /*!< [12..12] Port Lock bit 12                                                 */
      __IO uint32_t LK13       : 1;            /*!< [13..13] Port Lock bit 13                                                 */
      __IO uint32_t LK14       : 1;            /*!< [14..14] Port Lock bit 14                                                 */
      __IO uint32_t LK15       : 1;            /*!< [15..15] Port Lock bit 15                                                 */
      __IO uint32_t LKK        : 1;            /*!< [16..16] Lock sequence key                                                */
            uint32_t            : 15;
    } LOCK_b;
  } ;
} GPIO_Type;                                   /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                           I2C0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Inter integrated circuit (I2C0)
  */

typedef struct {                                /*!< (@ 0x40005400) I2C0 Structure                                             */

  union {
    __IO uint16_t CTL0;                        /*!< (@ 0x00000000) Control register 0                                         */

    struct {
      __IO uint16_t I2CEN      : 1;            /*!< [0..0] I2C peripheral enable                                              */
      __IO uint16_t SMBEN      : 1;            /*!< [1..1] SMBus/I2C mode switch                                              */
            uint16_t            : 1;
      __IO uint16_t SMBSEL     : 1;            /*!< [3..3] SMBusType Selection                                                */
      __IO uint16_t ARPEN      : 1;            /*!< [4..4] ARP protocol in SMBus switch                                       */
      __IO uint16_t PECEN      : 1;            /*!< [5..5] PEC Calculation Switch                                             */
      __IO uint16_t GCEN       : 1;            /*!< [6..6] Whether or not to response to a General Call (0x00)                */
      __IO uint16_t SS         : 1;            /*!< [7..7] Whether to stretch SCL low when data is not ready in
                                                     slave mode                                                                */
      __IO uint16_t START      : 1;            /*!< [8..8] Generate a START condition on I2C bus                              */
      __IO uint16_t STOP       : 1;            /*!< [9..9] Generate a STOP condition on I2C bus                               */
      __IO uint16_t ACKEN      : 1;            /*!< [10..10] Whether or not to send an ACK                                    */
      __IO uint16_t POAP       : 1;            /*!< [11..11] Position of ACK and PEC when receiving                           */
      __IO uint16_t PECTRANS   : 1;            /*!< [12..12] PEC Transfer                                                     */
      __IO uint16_t SALT       : 1;            /*!< [13..13] SMBus alert                                                      */
            uint16_t            : 1;
      __IO uint16_t SRESET     : 1;            /*!< [15..15] Software reset                                                   */
    } CTL0_b;
  } ;
  __I  uint16_t  RESERVED;

  union {
    __IO uint16_t CTL1;                        /*!< (@ 0x00000004) Control register 1                                         */

    struct {
      __IO uint16_t I2CCLK     : 6;            /*!< [5..0] I2C Peripheral clock frequency                                     */
            uint16_t            : 2;
      __IO uint16_t ERRIE      : 1;            /*!< [8..8] Error interrupt enable                                             */
      __IO uint16_t EVIE       : 1;            /*!< [9..9] Event interrupt enable                                             */
      __IO uint16_t BUFIE      : 1;            /*!< [10..10] Buffer interrupt enable                                          */
      __IO uint16_t DMAON      : 1;            /*!< [11..11] DMA mode switch                                                  */
      __IO uint16_t DMALST     : 1;            /*!< [12..12] Flag indicating DMA last transfer                                */
            uint16_t            : 3;
    } CTL1_b;
  } ;
  __I  uint16_t  RESERVED1;

  union {
    __IO uint16_t SADDR0;                      /*!< (@ 0x00000008) Slave address register 0                                   */

    struct {
      __IO uint16_t ADDRESS0   : 1;            /*!< [0..0] Bit 0 of a 10-bit address                                          */
      __IO uint16_t ADDRESS7_1 : 7;            /*!< [7..1] 7-bit address or bits 7:1 of a 10-bit address                      */
      __IO uint16_t ADDRESS9_8 : 2;            /*!< [9..8] Highest two bits of a 10-bit address                               */
            uint16_t            : 5;
      __IO uint16_t ADDFORMAT  : 1;            /*!< [15..15] Address mode for the I2C slave                                   */
    } SADDR0_b;
  } ;
  __I  uint16_t  RESERVED2;

  union {
    __IO uint16_t SADDR1;                      /*!< (@ 0x0000000C) Slave address register 1                                   */

    struct {
      __IO uint16_t DUADEN     : 1;            /*!< [0..0] Dual-Address mode switch                                           */
      __IO uint16_t ADDRESS2   : 7;            /*!< [7..1] Second I2C address for the slave in Dual-Address mode              */
            uint16_t            : 8;
    } SADDR1_b;
  } ;
  __I  uint16_t  RESERVED3;

  union {
    __IO uint16_t DATA;                        /*!< (@ 0x00000010) Transfer buffer register                                   */

    struct {
      __IO uint16_t TRB        : 8;            /*!< [7..0] Transmission or reception data buffer register                     */
            uint16_t            : 8;
    } DATA_b;
  } ;
  __I  uint16_t  RESERVED4;

  union {
    __IO uint16_t STAT0;                       /*!< (@ 0x00000014) Transfer status register 0                                 */

    struct {
      __I  uint16_t SBSEND     : 1;            /*!< [0..0] START condition sent out in master mode                            */
      __I  uint16_t ADDSEND    : 1;            /*!< [1..1] Address is sent in master mode or received and matches
                                                     in slave mode                                                             */
      __I  uint16_t BTC        : 1;            /*!< [2..2] Byte transmission completed                                        */
      __I  uint16_t ADD10SEND  : 1;            /*!< [3..3] Header of 10-bit address is sent in master mode                    */
      __I  uint16_t STPDET     : 1;            /*!< [4..4] STOP condition detected in slave mode                              */
            uint16_t            : 1;
      __I  uint16_t RBNE       : 1;            /*!< [6..6] I2C_DATA is not Empty during receiving                             */
      __I  uint16_t TBE        : 1;            /*!< [7..7] I2C_DATA is Empty during transmitting                              */
      __IO uint16_t BERR       : 1;            /*!< [8..8] A bus error occurs indication a unexpected START or STOP
                                                     condition on I2C bus                                                      */
      __IO uint16_t LOSTARB    : 1;            /*!< [9..9] Arbitration Lost in master mode                                    */
      __IO uint16_t AERR       : 1;            /*!< [10..10] Acknowledge error                                                */
      __IO uint16_t OUERR      : 1;            /*!< [11..11] Over-run or under-run situation occurs in slave mode             */
      __IO uint16_t PECERR     : 1;            /*!< [12..12] PEC error when receiving data                                    */
            uint16_t            : 1;
      __IO uint16_t SMBTO      : 1;            /*!< [14..14] Timeout signal in SMBus mode                                     */
      __IO uint16_t SMBALT     : 1;            /*!< [15..15] SMBus Alert status                                               */
    } STAT0_b;
  } ;
  __I  uint16_t  RESERVED5;

  union {
    __I  uint16_t STAT1;                       /*!< (@ 0x00000018) Transfer status register 1                                 */

    struct {
      __I  uint16_t MASTER     : 1;            /*!< [0..0] A flag indicating whether I2C block is in master or slave
                                                     mode                                                                      */
      __I  uint16_t I2CBSY     : 1;            /*!< [1..1] Busy flag                                                          */
      __I  uint16_t TR         : 1;            /*!< [2..2] Whether the I2C is a transmitter or a receiver                     */
            uint16_t            : 1;
      __I  uint16_t RXGC       : 1;            /*!< [4..4] General call address (00h) received                                */
      __I  uint16_t DEFSMB     : 1;            /*!< [5..5] Default address of SMBusDevice                                     */
      __I  uint16_t HSTSMB     : 1;            /*!< [6..6] SMBus Host Header detected in slave mode                           */
      __I  uint16_t DUMODF     : 1;            /*!< [7..7] Dual Flag in slave mode                                            */
      __I  uint16_t PECV       : 8;            /*!< [15..8] Packet Error Checking Value that calculated by hardware
                                                     when PEC is enabled                                                       */
    } STAT1_b;
  } ;
  __I  uint16_t  RESERVED6;

  union {
    __IO uint16_t CKCFG;                       /*!< (@ 0x0000001C) Clock configure register                                   */

    struct {
      __IO uint16_t CLKC       : 12;           /*!< [11..0] I2C Clock control in master mode                                  */
            uint16_t            : 2;
      __IO uint16_t DTCY       : 1;            /*!< [14..14] Duty cycle in fast mode                                          */
      __IO uint16_t FAST       : 1;            /*!< [15..15] I2C speed selection in master mode                               */
    } CKCFG_b;
  } ;
  __I  uint16_t  RESERVED7;

  union {
    __IO uint16_t RT;                          /*!< (@ 0x00000020) Rise time register                                         */

    struct {
      __IO uint16_t RISETIME   : 6;            /*!< [5..0] Maximum rise time in master mode                                   */
            uint16_t            : 10;
    } RT_b;
  } ;
} I2C_Type;                                    /*!< Size = 34 (0x22)                                                          */



/* =========================================================================================================================== */
/* ================                                           ECLIC                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Enhanced Core Local Interrupt Controller (ECLIC)
  */

typedef struct {                                /*!< (@ 0xD2000000) ECLIC Structure                                            */

  union {
    __IO uint8_t CLICCFG;                      /*!< (@ 0x00000000) cliccfg Register                                           */

    struct {
            uint8_t             : 1;
      __IO uint8_t NLBITS      : 4;            /*!< [4..1] NLBITS                                                             */
            uint8_t             : 3;
    } CLICCFG_b;
  } ;
  __I  uint8_t   RESERVED;
  __I  uint16_t  RESERVED1;

  union {
    __I  uint32_t CLICINFO;                    /*!< (@ 0x00000004) clicinfo Register                                          */

    struct {
      __I  uint32_t NUM_INTERRUPT : 13;        /*!< [12..0] NUM_INTERRUPT                                                     */
      __I  uint32_t VERSION    : 8;            /*!< [20..13] VERSION                                                          */
      __I  uint32_t CLICINTCTLBITS : 4;        /*!< [24..21] CLICINTCTLBITS                                                   */
            uint32_t            : 7;
    } CLICINFO_b;
  } ;
  __I  uint16_t  RESERVED2;
  __I  uint8_t   RESERVED3;

  union {
    __IO uint8_t MTH;                          /*!< (@ 0x0000000B) MTH Register                                               */

    struct {
      __IO uint8_t MTH         : 8;            /*!< [7..0] MTH                                                                */
    } MTH_b;
  } ;
  __I  uint32_t  RESERVED4[1021];

  union {
    __IO uint8_t CLICINTIP_0;                  /*!< (@ 0x00001000) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_0_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_0;                  /*!< (@ 0x00001001) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_0_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_0;                /*!< (@ 0x00001002) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_0_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_0;                 /*!< (@ 0x00001003) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_0_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_1;                  /*!< (@ 0x00001004) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_1_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_1;                  /*!< (@ 0x00001005) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_1_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_1;                /*!< (@ 0x00001006) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_1_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_1;                 /*!< (@ 0x00001007) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_1_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_2;                  /*!< (@ 0x00001008) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_2_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_2;                  /*!< (@ 0x00001009) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_2_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_2;                /*!< (@ 0x0000100A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_2_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_2;                 /*!< (@ 0x0000100B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_2_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_3;                  /*!< (@ 0x0000100C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_3_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_3;                  /*!< (@ 0x0000100D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_3_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_3;                /*!< (@ 0x0000100E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_3_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_3;                 /*!< (@ 0x0000100F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_3_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_4;                  /*!< (@ 0x00001010) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_4_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_4;                  /*!< (@ 0x00001011) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_4_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_4;                /*!< (@ 0x00001012) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_4_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_4;                 /*!< (@ 0x00001013) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_4_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_5;                  /*!< (@ 0x00001014) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_5_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_5;                  /*!< (@ 0x00001015) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_5_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_5;                /*!< (@ 0x00001016) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_5_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_5;                 /*!< (@ 0x00001017) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_5_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_6;                  /*!< (@ 0x00001018) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_6_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_6;                  /*!< (@ 0x00001019) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_6_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_6;                /*!< (@ 0x0000101A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_6_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_6;                 /*!< (@ 0x0000101B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_6_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_7;                  /*!< (@ 0x0000101C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_7_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_7;                  /*!< (@ 0x0000101D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_7_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_7;                /*!< (@ 0x0000101E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_7_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_7;                 /*!< (@ 0x0000101F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_7_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_8;                  /*!< (@ 0x00001020) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_8_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_8;                  /*!< (@ 0x00001021) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_8_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_8;                /*!< (@ 0x00001022) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_8_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_8;                 /*!< (@ 0x00001023) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_8_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_9;                  /*!< (@ 0x00001024) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_9_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_9;                  /*!< (@ 0x00001025) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_9_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_9;                /*!< (@ 0x00001026) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_9_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_9;                 /*!< (@ 0x00001027) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_9_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_10;                 /*!< (@ 0x00001028) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_10_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_10;                 /*!< (@ 0x00001029) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_10_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_10;               /*!< (@ 0x0000102A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_10_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_10;                /*!< (@ 0x0000102B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_10_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_11;                 /*!< (@ 0x0000102C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_11_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_11;                 /*!< (@ 0x0000102D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_11_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_11;               /*!< (@ 0x0000102E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_11_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_11;                /*!< (@ 0x0000102F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_11_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_12;                 /*!< (@ 0x00001030) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_12_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_12;                 /*!< (@ 0x00001031) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_12_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_12;               /*!< (@ 0x00001032) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_12_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_12;                /*!< (@ 0x00001033) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_12_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_13;                 /*!< (@ 0x00001034) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_13_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_13;                 /*!< (@ 0x00001035) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_13_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_13;               /*!< (@ 0x00001036) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_13_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_13;                /*!< (@ 0x00001037) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_13_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_14;                 /*!< (@ 0x00001038) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_14_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_14;                 /*!< (@ 0x00001039) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_14_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_14;               /*!< (@ 0x0000103A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_14_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_14;                /*!< (@ 0x0000103B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_14_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_15;                 /*!< (@ 0x0000103C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_15_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_15;                 /*!< (@ 0x0000103D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_15_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_15;               /*!< (@ 0x0000103E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_15_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_15;                /*!< (@ 0x0000103F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_15_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_16;                 /*!< (@ 0x00001040) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_16_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_16;                 /*!< (@ 0x00001041) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_16_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_16;               /*!< (@ 0x00001042) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_16_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_16;                /*!< (@ 0x00001043) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_16_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_17;                 /*!< (@ 0x00001044) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_17_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_17;                 /*!< (@ 0x00001045) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_17_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_17;               /*!< (@ 0x00001046) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_17_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_17;                /*!< (@ 0x00001047) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_17_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_18;                 /*!< (@ 0x00001048) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_18_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_18;                 /*!< (@ 0x00001049) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_18_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_18;               /*!< (@ 0x0000104A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_18_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_18;                /*!< (@ 0x0000104B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_18_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_19;                 /*!< (@ 0x0000104C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_19_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_19;                 /*!< (@ 0x0000104D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_19_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_19;               /*!< (@ 0x0000104E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_19_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_19;                /*!< (@ 0x0000104F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_19_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_20;                 /*!< (@ 0x00001050) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_20_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_20;                 /*!< (@ 0x00001051) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_20_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_20;               /*!< (@ 0x00001052) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_20_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_20;                /*!< (@ 0x00001053) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_20_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_21;                 /*!< (@ 0x00001054) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_21_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_21;                 /*!< (@ 0x00001055) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_21_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_21;               /*!< (@ 0x00001056) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_21_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_21;                /*!< (@ 0x00001057) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_21_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_22;                 /*!< (@ 0x00001058) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_22_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_22;                 /*!< (@ 0x00001059) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_22_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_22;               /*!< (@ 0x0000105A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_22_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_22;                /*!< (@ 0x0000105B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_22_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_23;                 /*!< (@ 0x0000105C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_23_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_23;                 /*!< (@ 0x0000105D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_23_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_23;               /*!< (@ 0x0000105E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_23_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_23;                /*!< (@ 0x0000105F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_23_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_24;                 /*!< (@ 0x00001060) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_24_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_24;                 /*!< (@ 0x00001061) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_24_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_24;               /*!< (@ 0x00001062) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_24_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_24;                /*!< (@ 0x00001063) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_24_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_25;                 /*!< (@ 0x00001064) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_25_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_25;                 /*!< (@ 0x00001065) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_25_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_25;               /*!< (@ 0x00001066) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_25_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_25;                /*!< (@ 0x00001067) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_25_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_26;                 /*!< (@ 0x00001068) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_26_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_26;                 /*!< (@ 0x00001069) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_26_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_26;               /*!< (@ 0x0000106A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_26_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_26;                /*!< (@ 0x0000106B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_26_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_27;                 /*!< (@ 0x0000106C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_27_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_27;                 /*!< (@ 0x0000106D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_27_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_27;               /*!< (@ 0x0000106E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_27_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_27;                /*!< (@ 0x0000106F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_27_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_28;                 /*!< (@ 0x00001070) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_28_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_28;                 /*!< (@ 0x00001071) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_28_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_28;               /*!< (@ 0x00001072) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_28_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_28;                /*!< (@ 0x00001073) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_28_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_29;                 /*!< (@ 0x00001074) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_29_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_29;                 /*!< (@ 0x00001075) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_29_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_29;               /*!< (@ 0x00001076) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_29_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_29;                /*!< (@ 0x00001077) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_29_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_30;                 /*!< (@ 0x00001078) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_30_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_30;                 /*!< (@ 0x00001079) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_30_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_30;               /*!< (@ 0x0000107A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_30_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_30;                /*!< (@ 0x0000107B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_30_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_31;                 /*!< (@ 0x0000107C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_31_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_31;                 /*!< (@ 0x0000107D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_31_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_31;               /*!< (@ 0x0000107E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_31_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_31;                /*!< (@ 0x0000107F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_31_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_32;                 /*!< (@ 0x00001080) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_32_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_32;                 /*!< (@ 0x00001081) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_32_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_32;               /*!< (@ 0x00001082) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_32_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_32;                /*!< (@ 0x00001083) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_32_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_33;                 /*!< (@ 0x00001084) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_33_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_33;                 /*!< (@ 0x00001085) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_33_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_33;               /*!< (@ 0x00001086) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_33_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_33;                /*!< (@ 0x00001087) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_33_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_34;                 /*!< (@ 0x00001088) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_34_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_34;                 /*!< (@ 0x00001089) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_34_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_34;               /*!< (@ 0x0000108A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_34_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_34;                /*!< (@ 0x0000108B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_34_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_35;                 /*!< (@ 0x0000108C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_35_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_35;                 /*!< (@ 0x0000108D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_35_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_35;               /*!< (@ 0x0000108E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_35_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_35;                /*!< (@ 0x0000108F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_35_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_36;                 /*!< (@ 0x00001090) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_36_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_36;                 /*!< (@ 0x00001091) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_36_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_36;               /*!< (@ 0x00001092) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_36_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_36;                /*!< (@ 0x00001093) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_36_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_37;                 /*!< (@ 0x00001094) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_37_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_37;                 /*!< (@ 0x00001095) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_37_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_37;               /*!< (@ 0x00001096) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_37_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_37;                /*!< (@ 0x00001097) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_37_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_38;                 /*!< (@ 0x00001098) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_38_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_38;                 /*!< (@ 0x00001099) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_38_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_38;               /*!< (@ 0x0000109A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_38_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_38;                /*!< (@ 0x0000109B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_38_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_39;                 /*!< (@ 0x0000109C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_39_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_39;                 /*!< (@ 0x0000109D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_39_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_39;               /*!< (@ 0x0000109E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_39_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_39;                /*!< (@ 0x0000109F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_39_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_40;                 /*!< (@ 0x000010A0) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_40_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_40;                 /*!< (@ 0x000010A1) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_40_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_40;               /*!< (@ 0x000010A2) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_40_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_40;                /*!< (@ 0x000010A3) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_40_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_41;                 /*!< (@ 0x000010A4) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_41_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_41;                 /*!< (@ 0x000010A5) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_41_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_41;               /*!< (@ 0x000010A6) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_41_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_41;                /*!< (@ 0x000010A7) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_41_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_42;                 /*!< (@ 0x000010A8) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_42_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_42;                 /*!< (@ 0x000010A9) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_42_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_42;               /*!< (@ 0x000010AA) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_42_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_42;                /*!< (@ 0x000010AB) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_42_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_43;                 /*!< (@ 0x000010AC) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_43_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_43;                 /*!< (@ 0x000010AD) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_43_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_43;               /*!< (@ 0x000010AE) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_43_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_43;                /*!< (@ 0x000010AF) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_43_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_44;                 /*!< (@ 0x000010B0) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_44_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_44;                 /*!< (@ 0x000010B1) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_44_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_44;               /*!< (@ 0x000010B2) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_44_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_44;                /*!< (@ 0x000010B3) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_44_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_45;                 /*!< (@ 0x000010B4) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_45_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_45;                 /*!< (@ 0x000010B5) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_45_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_45;               /*!< (@ 0x000010B6) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_45_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_45;                /*!< (@ 0x000010B7) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_45_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_46;                 /*!< (@ 0x000010B8) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_46_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_46;                 /*!< (@ 0x000010B9) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_46_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_46;               /*!< (@ 0x000010BA) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_46_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_46;                /*!< (@ 0x000010BB) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_46_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_47;                 /*!< (@ 0x000010BC) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_47_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_47;                 /*!< (@ 0x000010BD) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_47_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_47;               /*!< (@ 0x000010BE) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_47_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_47;                /*!< (@ 0x000010BF) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_47_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_48;                 /*!< (@ 0x000010C0) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_48_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_48;                 /*!< (@ 0x000010C1) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_48_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_48;               /*!< (@ 0x000010C2) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_48_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_48;                /*!< (@ 0x000010C3) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_48_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_49;                 /*!< (@ 0x000010C4) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_49_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_49;                 /*!< (@ 0x000010C5) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_49_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_49;               /*!< (@ 0x000010C6) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_49_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_49;                /*!< (@ 0x000010C7) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_49_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_50;                 /*!< (@ 0x000010C8) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_50_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_50;                 /*!< (@ 0x000010C9) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_50_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_50;               /*!< (@ 0x000010CA) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_50_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_50;                /*!< (@ 0x000010CB) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_50_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_51;                 /*!< (@ 0x000010CC) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_51_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_51;                 /*!< (@ 0x000010CD) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_51_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_51;               /*!< (@ 0x000010CE) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_51_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_51;                /*!< (@ 0x000010CF) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_51_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_52;                 /*!< (@ 0x000010D0) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_52_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_52;                 /*!< (@ 0x000010D1) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_52_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_52;               /*!< (@ 0x000010D2) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_52_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_52;                /*!< (@ 0x000010D3) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_52_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_53;                 /*!< (@ 0x000010D4) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_53_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_53;                 /*!< (@ 0x000010D5) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_53_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_53;               /*!< (@ 0x000010D6) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_53_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_53;                /*!< (@ 0x000010D7) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_53_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_54;                 /*!< (@ 0x000010D8) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_54_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_54;                 /*!< (@ 0x000010D9) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_54_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_54;               /*!< (@ 0x000010DA) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_54_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_54;                /*!< (@ 0x000010DB) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_54_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_55;                 /*!< (@ 0x000010DC) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_55_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_55;                 /*!< (@ 0x000010DD) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_55_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_55;               /*!< (@ 0x000010DE) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_55_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_55;                /*!< (@ 0x000010DF) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_55_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_56;                 /*!< (@ 0x000010E0) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_56_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_56;                 /*!< (@ 0x000010E1) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_56_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_56;               /*!< (@ 0x000010E2) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_56_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_56;                /*!< (@ 0x000010E3) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_56_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_57;                 /*!< (@ 0x000010E4) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_57_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_57;                 /*!< (@ 0x000010E5) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_57_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_57;               /*!< (@ 0x000010E6) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_57_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_57;                /*!< (@ 0x000010E7) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_57_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_58;                 /*!< (@ 0x000010E8) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_58_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_58;                 /*!< (@ 0x000010E9) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_58_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_58;               /*!< (@ 0x000010EA) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_58_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_58;                /*!< (@ 0x000010EB) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_58_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_59;                 /*!< (@ 0x000010EC) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_59_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_59;                 /*!< (@ 0x000010ED) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_59_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_59;               /*!< (@ 0x000010EE) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_59_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_59;                /*!< (@ 0x000010EF) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_59_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_60;                 /*!< (@ 0x000010F0) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_60_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_60;                 /*!< (@ 0x000010F1) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_60_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_60;               /*!< (@ 0x000010F2) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_60_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_60;                /*!< (@ 0x000010F3) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_60_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_61;                 /*!< (@ 0x000010F4) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_61_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_61;                 /*!< (@ 0x000010F5) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_61_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_61;               /*!< (@ 0x000010F6) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_61_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_61;                /*!< (@ 0x000010F7) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_61_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_62;                 /*!< (@ 0x000010F8) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_62_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_62;                 /*!< (@ 0x000010F9) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_62_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_62;               /*!< (@ 0x000010FA) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_62_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_62;                /*!< (@ 0x000010FB) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_62_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_63;                 /*!< (@ 0x000010FC) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_63_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_63;                 /*!< (@ 0x000010FD) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_63_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_63;               /*!< (@ 0x000010FE) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_63_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_63;                /*!< (@ 0x000010FF) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_63_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_64;                 /*!< (@ 0x00001100) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_64_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_64;                 /*!< (@ 0x00001101) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_64_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_64;               /*!< (@ 0x00001102) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_64_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_64;                /*!< (@ 0x00001103) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_64_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_65;                 /*!< (@ 0x00001104) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_65_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_65;                 /*!< (@ 0x00001105) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_65_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_65;               /*!< (@ 0x00001106) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_65_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_65;                /*!< (@ 0x00001107) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_65_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_66;                 /*!< (@ 0x00001108) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_66_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_66;                 /*!< (@ 0x00001109) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_66_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_66;               /*!< (@ 0x0000110A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_66_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_66;                /*!< (@ 0x0000110B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_66_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_67;                 /*!< (@ 0x0000110C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_67_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_67;                 /*!< (@ 0x0000110D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_67_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_67;               /*!< (@ 0x0000110E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_67_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_67;                /*!< (@ 0x0000110F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_67_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_68;                 /*!< (@ 0x00001110) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_68_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_68;                 /*!< (@ 0x00001111) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_68_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_68;               /*!< (@ 0x00001112) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_68_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_68;                /*!< (@ 0x00001113) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_68_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_69;                 /*!< (@ 0x00001114) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_69_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_69;                 /*!< (@ 0x00001115) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_69_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_69;               /*!< (@ 0x00001116) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_69_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_69;                /*!< (@ 0x00001117) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_69_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_70;                 /*!< (@ 0x00001118) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_70_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_70;                 /*!< (@ 0x00001119) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_70_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_70;               /*!< (@ 0x0000111A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_70_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_70;                /*!< (@ 0x0000111B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_70_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_71;                 /*!< (@ 0x0000111C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_71_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_71;                 /*!< (@ 0x0000111D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_71_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_71;               /*!< (@ 0x0000111E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_71_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_71;                /*!< (@ 0x0000111F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_71_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_72;                 /*!< (@ 0x00001120) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_72_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_72;                 /*!< (@ 0x00001121) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_72_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_72;               /*!< (@ 0x00001122) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_72_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_72;                /*!< (@ 0x00001123) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_72_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_73;                 /*!< (@ 0x00001124) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_73_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_73;                 /*!< (@ 0x00001125) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_73_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_73;               /*!< (@ 0x00001126) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_73_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_73;                /*!< (@ 0x00001127) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_73_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_74;                 /*!< (@ 0x00001128) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_74_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_74;                 /*!< (@ 0x00001129) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_74_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_74;               /*!< (@ 0x0000112A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_74_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_74;                /*!< (@ 0x0000112B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_74_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_75;                 /*!< (@ 0x0000112C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_75_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_75;                 /*!< (@ 0x0000112D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_75_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_75;               /*!< (@ 0x0000112E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_75_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_75;                /*!< (@ 0x0000112F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_75_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_76;                 /*!< (@ 0x00001130) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_76_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_76;                 /*!< (@ 0x00001131) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_76_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_76;               /*!< (@ 0x00001132) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_76_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_76;                /*!< (@ 0x00001133) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_76_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_77;                 /*!< (@ 0x00001134) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_77_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_77;                 /*!< (@ 0x00001135) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_77_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_77;               /*!< (@ 0x00001136) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_77_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_77;                /*!< (@ 0x00001137) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_77_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_78;                 /*!< (@ 0x00001138) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_78_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_78;                 /*!< (@ 0x00001139) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_78_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_78;               /*!< (@ 0x0000113A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_78_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_78;                /*!< (@ 0x0000113B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_78_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_79;                 /*!< (@ 0x0000113C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_79_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_79;                 /*!< (@ 0x0000113D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_79_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_79;               /*!< (@ 0x0000113E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_79_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_79;                /*!< (@ 0x0000113F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_79_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_80;                 /*!< (@ 0x00001140) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_80_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_80;                 /*!< (@ 0x00001141) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_80_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_80;               /*!< (@ 0x00001142) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_80_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_80;                /*!< (@ 0x00001143) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_80_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_81;                 /*!< (@ 0x00001144) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_81_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_81;                 /*!< (@ 0x00001145) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_81_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_81;               /*!< (@ 0x00001146) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_81_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_81;                /*!< (@ 0x00001147) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_81_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_82;                 /*!< (@ 0x00001148) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_82_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_82;                 /*!< (@ 0x00001149) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_82_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_82;               /*!< (@ 0x0000114A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_82_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_82;                /*!< (@ 0x0000114B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_82_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_83;                 /*!< (@ 0x0000114C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_83_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_83;                 /*!< (@ 0x0000114D) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_83_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_83;               /*!< (@ 0x0000114E) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_83_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_83;                /*!< (@ 0x0000114F) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_83_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_84;                 /*!< (@ 0x00001150) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_84_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_84;                 /*!< (@ 0x00001151) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_84_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_84;               /*!< (@ 0x00001152) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_84_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_84;                /*!< (@ 0x00001153) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_84_b;
  } ;
  __I  uint8_t   RESERVED5;

  union {
    __IO uint8_t CLICINTIE_85;                 /*!< (@ 0x00001155) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_85_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_85;               /*!< (@ 0x00001156) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_85_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_85;                /*!< (@ 0x00001157) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_85_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_85;                 /*!< (@ 0x00001158) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_85_b;
  } ;

  union {
    __IO uint8_t CLICINTIE_86;                 /*!< (@ 0x00001159) clicintie Register                                         */

    struct {
      __IO uint8_t IE          : 1;            /*!< [0..0] IE                                                                 */
            uint8_t             : 7;
    } CLICINTIE_86_b;
  } ;

  union {
    __IO uint8_t CLICINTATTR_86;               /*!< (@ 0x0000115A) clicintattr Register                                       */

    struct {
      __IO uint8_t SHV         : 1;            /*!< [0..0] SHV                                                                */
      __IO uint8_t TRIG        : 2;            /*!< [2..1] TRIG                                                               */
            uint8_t             : 5;
    } CLICINTATTR_86_b;
  } ;

  union {
    __IO uint8_t CLICINTCTL_86;                /*!< (@ 0x0000115B) clicintctl Register                                        */

    struct {
      __IO uint8_t LEVEL_PRIORITY : 8;         /*!< [7..0] LEVEL_PRIORITY                                                     */
    } CLICINTCTL_86_b;
  } ;

  union {
    __IO uint8_t CLICINTIP_86;                 /*!< (@ 0x0000115C) clicintip Register                                         */

    struct {
      __IO uint8_t IP          : 1;            /*!< [0..0] IP                                                                 */
            uint8_t             : 7;
    } CLICINTIP_86_b;
  } ;
  __I  uint8_t   RESERVED6;
  __I  uint16_t  RESERVED7;
} ECLIC_Type;                                   /*!< Size = 4448 (0x1160)                                                      */



/* =========================================================================================================================== */
/* ================                                            PMU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Power management unit (PMU)
  */

typedef struct {                                /*!< (@ 0x40007000) PMU Structure                                              */

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000000) power control register                                     */

    struct {
      __IO uint32_t LDOLP      : 1;            /*!< [0..0] LDO Low Power Mode                                                 */
      __IO uint32_t STBMOD     : 1;            /*!< [1..1] Standby Mode                                                       */
      __IO uint32_t WURST      : 1;            /*!< [2..2] Wakeup Flag Reset                                                  */
      __IO uint32_t STBRST     : 1;            /*!< [3..3] Standby Flag Reset                                                 */
      __IO uint32_t LVDEN      : 1;            /*!< [4..4] Low Voltage Detector Enable                                        */
      __IO uint32_t LVDT       : 3;            /*!< [7..5] Low Voltage Detector Threshold                                     */
      __IO uint32_t BKPWEN     : 1;            /*!< [8..8] Backup Domain Write Enable                                         */
            uint32_t            : 23;
    } CTL_b;
  } ;

  union {
    __IO uint32_t CS;                          /*!< (@ 0x00000004) power control/status register                              */

    struct {
      __I  uint32_t WUF        : 1;            /*!< [0..0] Wakeup flag                                                        */
      __I  uint32_t STBF       : 1;            /*!< [1..1] Standby flag                                                       */
      __I  uint32_t LVDF       : 1;            /*!< [2..2] Low Voltage Detector Status Flag                                   */
            uint32_t            : 5;
      __IO uint32_t WUPEN      : 1;            /*!< [8..8] Enable WKUP pin                                                    */
            uint32_t            : 23;
    } CS_b;
  } ;
} PMU_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                            RCU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Reset and clock unit (RCU)
  */

typedef struct {                                /*!< (@ 0x40021000) RCU Structure                                              */

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000000) Control register                                           */

    struct {
      __IO uint32_t IRC8MEN    : 1;            /*!< [0..0] Internal 8MHz RC oscillator Enable                                 */
      __I  uint32_t IRC8MSTB   : 1;            /*!< [1..1] IRC8M Internal 8MHz RC Oscillator stabilization Flag               */
            uint32_t            : 1;
      __IO uint32_t IRC8MADJ   : 5;            /*!< [7..3] Internal 8MHz RC Oscillator clock trim adjust value                */
      __I  uint32_t IRC8MCALIB : 8;            /*!< [15..8] Internal 8MHz RC Oscillator calibration value register            */
      __IO uint32_t HXTALEN    : 1;            /*!< [16..16] External High Speed oscillator Enable                            */
      __I  uint32_t HXTALSTB   : 1;            /*!< [17..17] External crystal oscillator (HXTAL) clock stabilization
                                                     flag                                                                      */
      __IO uint32_t HXTALBPS   : 1;            /*!< [18..18] External crystal oscillator (HXTAL) clock bypass mode
                                                     enable                                                                    */
      __IO uint32_t CKMEN      : 1;            /*!< [19..19] HXTAL Clock Monitor Enable                                       */
            uint32_t            : 4;
      __IO uint32_t PLLEN      : 1;            /*!< [24..24] PLL enable                                                       */
      __I  uint32_t PLLSTB     : 1;            /*!< [25..25] PLL Clock Stabilization Flag                                     */
      __IO uint32_t PLL1EN     : 1;            /*!< [26..26] PLL1 enable                                                      */
      __I  uint32_t PLL1STB    : 1;            /*!< [27..27] PLL1 Clock Stabilization Flag                                    */
      __IO uint32_t PLL2EN     : 1;            /*!< [28..28] PLL2 enable                                                      */
      __I  uint32_t PLL2STB    : 1;            /*!< [29..29] PLL2 Clock Stabilization Flag                                    */
            uint32_t            : 2;
    } CTL_b;
  } ;

  union {
    __IO uint32_t CFG0;                        /*!< (@ 0x00000004) Clock configuration register 0 (RCU_CFG0)                  */

    struct {
      __IO uint32_t SCS        : 2;            /*!< [1..0] System clock switch                                                */
      __I  uint32_t SCSS       : 2;            /*!< [3..2] System clock switch status                                         */
      __IO uint32_t AHBPSC     : 4;            /*!< [7..4] AHB prescaler selection                                            */
      __IO uint32_t APB1PSC    : 3;            /*!< [10..8] APB1 prescaler selection                                          */
      __IO uint32_t APB2PSC    : 3;            /*!< [13..11] APB2 prescaler selection                                         */
      __IO uint32_t ADCPSC_1_0 : 2;            /*!< [15..14] ADC clock prescaler selection                                    */
      __IO uint32_t PLLSEL     : 1;            /*!< [16..16] PLL Clock Source Selection                                       */
      __IO uint32_t PREDV0_LSB : 1;            /*!< [17..17] The LSB of PREDV0 division factor                                */
      __IO uint32_t PLLMF_3_0  : 4;            /*!< [21..18] The PLL clock multiplication factor                              */
      __IO uint32_t USBFSPSC   : 2;            /*!< [23..22] USBFS clock prescaler selection                                  */
      __IO uint32_t CKOUT0SEL  : 4;            /*!< [27..24] CKOUT0 Clock Source Selection                                    */
      __IO uint32_t ADCPSC_2   : 1;            /*!< [28..28] Bit 2 of ADCPSC                                                  */
      __IO uint32_t PLLMF_4    : 1;            /*!< [29..29] Bit 4 of PLLMF                                                   */
            uint32_t            : 2;
    } CFG0_b;
  } ;

  union {
    __IO uint32_t INT;                         /*!< (@ 0x00000008) Clock interrupt register (RCU_INT)                         */

    struct {
      __I  uint32_t IRC40KSTBIF : 1;           /*!< [0..0] IRC40K stabilization interrupt flag                                */
      __I  uint32_t LXTALSTBIF : 1;            /*!< [1..1] LXTAL stabilization interrupt flag                                 */
      __I  uint32_t IRC8MSTBIF : 1;            /*!< [2..2] IRC8M stabilization interrupt flag                                 */
      __I  uint32_t HXTALSTBIF : 1;            /*!< [3..3] HXTAL stabilization interrupt flag                                 */
      __I  uint32_t PLLSTBIF   : 1;            /*!< [4..4] PLL stabilization interrupt flag                                   */
      __I  uint32_t PLL1STBIF  : 1;            /*!< [5..5] PLL1 stabilization interrupt flag                                  */
      __I  uint32_t PLL2STBIF  : 1;            /*!< [6..6] PLL2 stabilization interrupt flag                                  */
      __I  uint32_t CKMIF      : 1;            /*!< [7..7] HXTAL Clock Stuck Interrupt Flag                                   */
      __IO uint32_t IRC40KSTBIE : 1;           /*!< [8..8] IRC40K Stabilization interrupt enable                              */
      __IO uint32_t LXTALSTBIE : 1;            /*!< [9..9] LXTAL Stabilization Interrupt Enable                               */
      __IO uint32_t IRC8MSTBIE : 1;            /*!< [10..10] IRC8M Stabilization Interrupt Enable                             */
      __IO uint32_t HXTALSTBIE : 1;            /*!< [11..11] HXTAL Stabilization Interrupt Enable                             */
      __IO uint32_t PLLSTBIE   : 1;            /*!< [12..12] PLL Stabilization Interrupt Enable                               */
      __IO uint32_t PLL1STBIE  : 1;            /*!< [13..13] PLL1 Stabilization Interrupt Enable                              */
      __IO uint32_t PLL2STBIE  : 1;            /*!< [14..14] PLL2 Stabilization Interrupt Enable                              */
            uint32_t            : 1;
      __O  uint32_t IRC40KSTBIC : 1;           /*!< [16..16] IRC40K Stabilization Interrupt Clear                             */
      __O  uint32_t LXTALSTBIC : 1;            /*!< [17..17] LXTAL Stabilization Interrupt Clear                              */
      __O  uint32_t IRC8MSTBIC : 1;            /*!< [18..18] IRC8M Stabilization Interrupt Clear                              */
      __O  uint32_t HXTALSTBIC : 1;            /*!< [19..19] HXTAL Stabilization Interrupt Clear                              */
      __O  uint32_t PLLSTBIC   : 1;            /*!< [20..20] PLL stabilization Interrupt Clear                                */
      __O  uint32_t PLL1STBIC  : 1;            /*!< [21..21] PLL1 stabilization Interrupt Clear                               */
      __O  uint32_t PLL2STBIC  : 1;            /*!< [22..22] PLL2 stabilization Interrupt Clear                               */
      __O  uint32_t CKMIC      : 1;            /*!< [23..23] HXTAL Clock Stuck Interrupt Clear                                */
            uint32_t            : 8;
    } INT_b;
  } ;

  union {
    __IO uint32_t APB2RST;                     /*!< (@ 0x0000000C) APB2 reset register (RCU_APB2RST)                          */

    struct {
      __IO uint32_t AFRST      : 1;            /*!< [0..0] Alternate function I/O reset                                       */
            uint32_t            : 1;
      __IO uint32_t PARST      : 1;            /*!< [2..2] GPIO port A reset                                                  */
      __IO uint32_t PBRST      : 1;            /*!< [3..3] GPIO port B reset                                                  */
      __IO uint32_t PCRST      : 1;            /*!< [4..4] GPIO port C reset                                                  */
      __IO uint32_t PDRST      : 1;            /*!< [5..5] GPIO port D reset                                                  */
      __IO uint32_t PERST      : 1;            /*!< [6..6] GPIO port E reset                                                  */
            uint32_t            : 2;
      __IO uint32_t ADC0RST    : 1;            /*!< [9..9] ADC0 reset                                                         */
      __IO uint32_t ADC1RST    : 1;            /*!< [10..10] ADC1 reset                                                       */
      __IO uint32_t TIMER0RST  : 1;            /*!< [11..11] Timer 0 reset                                                    */
      __IO uint32_t SPI0RST    : 1;            /*!< [12..12] SPI0 reset                                                       */
            uint32_t            : 1;
      __IO uint32_t USART0RST  : 1;            /*!< [14..14] USART0 Reset                                                     */
            uint32_t            : 17;
    } APB2RST_b;
  } ;

  union {
    __IO uint32_t APB1RST;                     /*!< (@ 0x00000010) APB1 reset register (RCU_APB1RST)                          */

    struct {
      __IO uint32_t TIMER1RST  : 1;            /*!< [0..0] TIMER1 timer reset                                                 */
      __IO uint32_t TIMER2RST  : 1;            /*!< [1..1] TIMER2 timer reset                                                 */
      __IO uint32_t TIMER3RST  : 1;            /*!< [2..2] TIMER3 timer reset                                                 */
      __IO uint32_t TIMER4RST  : 1;            /*!< [3..3] TIMER4 timer reset                                                 */
      __IO uint32_t TIMER5RST  : 1;            /*!< [4..4] TIMER5 timer reset                                                 */
      __IO uint32_t TIMER6RST  : 1;            /*!< [5..5] TIMER6 timer reset                                                 */
            uint32_t            : 5;
      __IO uint32_t WWDGTRST   : 1;            /*!< [11..11] Window watchdog timer reset                                      */
            uint32_t            : 2;
      __IO uint32_t SPI1RST    : 1;            /*!< [14..14] SPI1 reset                                                       */
      __IO uint32_t SPI2RST    : 1;            /*!< [15..15] SPI2 reset                                                       */
            uint32_t            : 1;
      __IO uint32_t USART1RST  : 1;            /*!< [17..17] USART1 reset                                                     */
      __IO uint32_t USART2RST  : 1;            /*!< [18..18] USART2 reset                                                     */
      __IO uint32_t UART3RST   : 1;            /*!< [19..19] UART3 reset                                                      */
      __IO uint32_t UART4RST   : 1;            /*!< [20..20] UART4 reset                                                      */
      __IO uint32_t I2C0RST    : 1;            /*!< [21..21] I2C0 reset                                                       */
      __IO uint32_t I2C1RST    : 1;            /*!< [22..22] I2C1 reset                                                       */
            uint32_t            : 2;
      __IO uint32_t CAN0RST    : 1;            /*!< [25..25] CAN0 reset                                                       */
      __IO uint32_t CAN1RST    : 1;            /*!< [26..26] CAN1 reset                                                       */
      __IO uint32_t BKPIRST    : 1;            /*!< [27..27] Backup interface reset                                           */
      __IO uint32_t PMURST     : 1;            /*!< [28..28] Power control reset                                              */
      __IO uint32_t DACRST     : 1;            /*!< [29..29] DAC reset                                                        */
            uint32_t            : 2;
    } APB1RST_b;
  } ;

  union {
    __IO uint32_t AHBEN;                       /*!< (@ 0x00000014) AHB enable register                                        */

    struct {
      __IO uint32_t DMA0EN     : 1;            /*!< [0..0] DMA0 clock enable                                                  */
      __IO uint32_t DMA1EN     : 1;            /*!< [1..1] DMA1 clock enable                                                  */
      __IO uint32_t SRAMSPEN   : 1;            /*!< [2..2] SRAM interface clock enable when sleep mode                        */
            uint32_t            : 1;
      __IO uint32_t FMCSPEN    : 1;            /*!< [4..4] FMC clock enable when sleep mode                                   */
            uint32_t            : 1;
      __IO uint32_t CRCEN      : 1;            /*!< [6..6] CRC clock enable                                                   */
            uint32_t            : 1;
      __IO uint32_t EXMCEN     : 1;            /*!< [8..8] EXMC clock enable                                                  */
            uint32_t            : 3;
      __IO uint32_t USBFSEN    : 1;            /*!< [12..12] USBFS clock enable                                               */
            uint32_t            : 19;
    } AHBEN_b;
  } ;

  union {
    __IO uint32_t APB2EN;                      /*!< (@ 0x00000018) APB2 clock enable register (RCU_APB2EN)                    */

    struct {
      __IO uint32_t AFEN       : 1;            /*!< [0..0] Alternate function IO clock enable                                 */
            uint32_t            : 1;
      __IO uint32_t PAEN       : 1;            /*!< [2..2] GPIO port A clock enable                                           */
      __IO uint32_t PBEN       : 1;            /*!< [3..3] GPIO port B clock enable                                           */
      __IO uint32_t PCEN       : 1;            /*!< [4..4] GPIO port C clock enable                                           */
      __IO uint32_t PDEN       : 1;            /*!< [5..5] GPIO port D clock enable                                           */
      __IO uint32_t PEEN       : 1;            /*!< [6..6] GPIO port E clock enable                                           */
            uint32_t            : 2;
      __IO uint32_t ADC0EN     : 1;            /*!< [9..9] ADC0 clock enable                                                  */
      __IO uint32_t ADC1EN     : 1;            /*!< [10..10] ADC1 clock enable                                                */
      __IO uint32_t TIMER0EN   : 1;            /*!< [11..11] TIMER0 clock enable                                              */
      __IO uint32_t SPI0EN     : 1;            /*!< [12..12] SPI0 clock enable                                                */
            uint32_t            : 1;
      __IO uint32_t USART0EN   : 1;            /*!< [14..14] USART0 clock enable                                              */
            uint32_t            : 17;
    } APB2EN_b;
  } ;

  union {
    __IO uint32_t APB1EN;                      /*!< (@ 0x0000001C) APB1 clock enable register (RCU_APB1EN)                    */

    struct {
      __IO uint32_t TIMER1EN   : 1;            /*!< [0..0] TIMER1 timer clock enable                                          */
      __IO uint32_t TIMER2EN   : 1;            /*!< [1..1] TIMER2 timer clock enable                                          */
      __IO uint32_t TIMER3EN   : 1;            /*!< [2..2] TIMER3 timer clock enable                                          */
      __IO uint32_t TIMER4EN   : 1;            /*!< [3..3] TIMER4 timer clock enable                                          */
      __IO uint32_t TIMER5EN   : 1;            /*!< [4..4] TIMER5 timer clock enable                                          */
      __IO uint32_t TIMER6EN   : 1;            /*!< [5..5] TIMER6 timer clock enable                                          */
            uint32_t            : 5;
      __IO uint32_t WWDGTEN    : 1;            /*!< [11..11] Window watchdog timer clock enable                               */
            uint32_t            : 2;
      __IO uint32_t SPI1EN     : 1;            /*!< [14..14] SPI1 clock enable                                                */
      __IO uint32_t SPI2EN     : 1;            /*!< [15..15] SPI2 clock enable                                                */
            uint32_t            : 1;
      __IO uint32_t USART1EN   : 1;            /*!< [17..17] USART1 clock enable                                              */
      __IO uint32_t USART2EN   : 1;            /*!< [18..18] USART2 clock enable                                              */
      __IO uint32_t UART3EN    : 1;            /*!< [19..19] UART3 clock enable                                               */
      __IO uint32_t UART4EN    : 1;            /*!< [20..20] UART4 clock enable                                               */
      __IO uint32_t I2C0EN     : 1;            /*!< [21..21] I2C0 clock enable                                                */
      __IO uint32_t I2C1EN     : 1;            /*!< [22..22] I2C1 clock enable                                                */
            uint32_t            : 2;
      __IO uint32_t CAN0EN     : 1;            /*!< [25..25] CAN0 clock enable                                                */
      __IO uint32_t CAN1EN     : 1;            /*!< [26..26] CAN1 clock enable                                                */
      __IO uint32_t BKPIEN     : 1;            /*!< [27..27] Backup interface clock enable                                    */
      __IO uint32_t PMUEN      : 1;            /*!< [28..28] Power control clock enable                                       */
      __IO uint32_t DACEN      : 1;            /*!< [29..29] DAC clock enable                                                 */
            uint32_t            : 2;
    } APB1EN_b;
  } ;

  union {
    __IO uint32_t BDCTL;                       /*!< (@ 0x00000020) Backup domain control register (RCU_BDCTL)                 */

    struct {
      __IO uint32_t LXTALEN    : 1;            /*!< [0..0] LXTAL enable                                                       */
      __I  uint32_t LXTALSTB   : 1;            /*!< [1..1] External low-speed oscillator stabilization                        */
      __IO uint32_t LXTALBPS   : 1;            /*!< [2..2] LXTAL bypass mode enable                                           */
            uint32_t            : 5;
      __IO uint32_t RTCSRC     : 2;            /*!< [9..8] RTC clock entry selection                                          */
            uint32_t            : 5;
      __IO uint32_t RTCEN      : 1;            /*!< [15..15] RTC clock enable                                                 */
      __IO uint32_t BKPRST     : 1;            /*!< [16..16] Backup domain reset                                              */
            uint32_t            : 15;
    } BDCTL_b;
  } ;

  union {
    __IO uint32_t RSTSCK;                      /*!< (@ 0x00000024) Reset source /clock register (RCU_RSTSCK)                  */

    struct {
      __IO uint32_t IRC40KEN   : 1;            /*!< [0..0] IRC40K enable                                                      */
      __I  uint32_t IRC40KSTB  : 1;            /*!< [1..1] IRC40K stabilization                                               */
            uint32_t            : 22;
      __IO uint32_t RSTFC      : 1;            /*!< [24..24] Reset flag clear                                                 */
            uint32_t            : 1;
      __I  uint32_t EPRSTF     : 1;            /*!< [26..26] External PIN reset flag                                          */
      __I  uint32_t PORRSTF    : 1;            /*!< [27..27] Power reset flag                                                 */
      __I  uint32_t SWRSTF     : 1;            /*!< [28..28] Software reset flag                                              */
      __I  uint32_t FWDGTRSTF  : 1;            /*!< [29..29] Free Watchdog timer reset flag                                   */
      __I  uint32_t WWDGTRSTF  : 1;            /*!< [30..30] Window watchdog timer reset flag                                 */
      __I  uint32_t LPRSTF     : 1;            /*!< [31..31] Low-power reset flag                                             */
    } RSTSCK_b;
  } ;

  union {
    __IO uint32_t AHBRST;                      /*!< (@ 0x00000028) AHB reset register                                         */

    struct {
            uint32_t            : 12;
      __IO uint32_t USBFSRST   : 1;            /*!< [12..12] USBFS reset                                                      */
            uint32_t            : 19;
    } AHBRST_b;
  } ;

  union {
    __IO uint32_t CFG1;                        /*!< (@ 0x0000002C) Clock Configuration register 1                             */

    struct {
      __IO uint32_t PREDV0     : 4;            /*!< [3..0] PREDV0 division factor                                             */
      __IO uint32_t PREDV1     : 4;            /*!< [7..4] PREDV1 division factor                                             */
      __IO uint32_t PLL1MF     : 4;            /*!< [11..8] The PLL1 clock multiplication factor                              */
      __IO uint32_t PLL2MF     : 4;            /*!< [15..12] The PLL2 clock multiplication factor                             */
      __IO uint32_t PREDV0SEL  : 1;            /*!< [16..16] PREDV0 input Clock Source Selection                              */
      __IO uint32_t I2S1SEL    : 1;            /*!< [17..17] I2S1 Clock Source Selection                                      */
      __IO uint32_t I2S2SEL    : 1;            /*!< [18..18] I2S2 Clock Source Selection                                      */
            uint32_t            : 13;
    } CFG1_b;
  } ;
  __I  uint32_t  RESERVED;

  union {
    __IO uint32_t DSV;                         /*!< (@ 0x00000034) Deep sleep mode Voltage register                           */

    struct {
      __IO uint32_t DSLPVS     : 2;            /*!< [1..0] Deep-sleep mode voltage select                                     */
            uint32_t            : 30;
    } DSV_b;
  } ;
} RCU_Type;                                     /*!< Size = 56 (0x38)                                                          */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Real-time clock (RTC)
  */

typedef struct {                                /*!< (@ 0x40002800) RTC Structure                                              */

  union {
    __IO uint32_t INTEN;                       /*!< (@ 0x00000000) RTC interrupt enable register                              */

    struct {
      __IO uint32_t SCIE       : 1;            /*!< [0..0] Second interrupt                                                   */
      __IO uint32_t ALRMIE     : 1;            /*!< [1..1] Alarm interrupt enable                                             */
      __IO uint32_t OVIE       : 1;            /*!< [2..2] Overflow interrupt enable                                          */
            uint32_t            : 29;
    } INTEN_b;
  } ;

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000004) control register                                           */

    struct {
      __IO uint32_t SCIF       : 1;            /*!< [0..0] Sencond interrupt flag                                             */
      __IO uint32_t ALRMIF     : 1;            /*!< [1..1] Alarm interrupt flag                                               */
      __IO uint32_t OVIF       : 1;            /*!< [2..2] Overflow interrupt flag                                            */
      __IO uint32_t RSYNF      : 1;            /*!< [3..3] Registers synchronized flag                                        */
      __IO uint32_t CMF        : 1;            /*!< [4..4] Configuration mode flag                                            */
      __IO uint32_t LWOFF      : 1;            /*!< [5..5] Last write operation finished flag                                 */
            uint32_t            : 26;
    } CTL_b;
  } ;

  union {
    __IO uint32_t PSCH;                        /*!< (@ 0x00000008) RTC prescaler high register                                */

    struct {
      __O  uint32_t PSC        : 4;            /*!< [3..0] RTC prescaler value high                                           */
            uint32_t            : 28;
    } PSCH_b;
  } ;

  union {
    __IO uint32_t PSCL;                        /*!< (@ 0x0000000C) RTC prescaler low register                                 */

    struct {
      __O  uint32_t PSC        : 16;           /*!< [15..0] RTC prescaler value low                                           */
            uint32_t            : 16;
    } PSCL_b;
  } ;

  union {
    __I  uint32_t DIVH;                        /*!< (@ 0x00000010) RTC divider high register                                  */

    struct {
      __I  uint32_t DIV        : 4;            /*!< [3..0] RTC divider value high                                             */
            uint32_t            : 28;
    } DIVH_b;
  } ;

  union {
    __I  uint32_t DIVL;                        /*!< (@ 0x00000014) RTC divider low register                                   */

    struct {
      __I  uint32_t DIV        : 16;           /*!< [15..0] RTC divider value low                                             */
            uint32_t            : 16;
    } DIVL_b;
  } ;

  union {
    __IO uint32_t CNTH;                        /*!< (@ 0x00000018) RTC counter high register                                  */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] RTC counter value high                                            */
            uint32_t            : 16;
    } CNTH_b;
  } ;

  union {
    __IO uint32_t CNTL;                        /*!< (@ 0x0000001C) RTC counter low register                                   */

    struct {
      __IO uint32_t CNT        : 16;           /*!< [15..0] RTC counter value low                                             */
            uint32_t            : 16;
    } CNTL_b;
  } ;

  union {
    __O  uint32_t ALRMH;                       /*!< (@ 0x00000020) Alarm high register                                        */

    struct {
      __O  uint32_t ALRM       : 16;           /*!< [15..0] Alarm value high                                                  */
            uint32_t            : 16;
    } ALRMH_b;
  } ;

  union {
    __O  uint32_t ALRML;                       /*!< (@ 0x00000024) RTC alarm low register                                     */

    struct {
      __O  uint32_t ALRM       : 16;           /*!< [15..0] alarm value low                                                   */
            uint32_t            : 16;
    } ALRML_b;
  } ;
} RTC_Type;                                     /*!< Size = 40 (0x28)                                                          */



/* =========================================================================================================================== */
/* ================                                           SPI0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Serial peripheral interface (SPI0)
  */

typedef struct {                                /*!< (@ 0x40013000) SPI0 Structure                                             */

  union {
    __IO uint16_t CTL0;                        /*!< (@ 0x00000000) control register 0                                         */

    struct {
      __IO uint16_t CKPH       : 1;            /*!< [0..0] Clock Phase Selection                                              */
      __IO uint16_t CKPL       : 1;            /*!< [1..1] Clock polarity Selection                                           */
      __IO uint16_t MSTMOD     : 1;            /*!< [2..2] Master Mode Enable                                                 */
      __IO uint16_t PSC        : 3;            /*!< [5..3] Master Clock Prescaler Selection                                   */
      __IO uint16_t SPIEN      : 1;            /*!< [6..6] SPI enable                                                         */
      __IO uint16_t LF         : 1;            /*!< [7..7] LSB First Mode                                                     */
      __IO uint16_t SWNSS      : 1;            /*!< [8..8] NSS Pin Selection In NSS Software Mode                             */
      __IO uint16_t SWNSSEN    : 1;            /*!< [9..9] NSS Software Mode Selection                                        */
      __IO uint16_t RO         : 1;            /*!< [10..10] Receive only                                                     */
      __IO uint16_t FF16       : 1;            /*!< [11..11] Data frame format                                                */
      __IO uint16_t CRCNT      : 1;            /*!< [12..12] CRC Next Transfer                                                */
      __IO uint16_t CRCEN      : 1;            /*!< [13..13] CRC Calculation Enable                                           */
      __IO uint16_t BDOEN      : 1;            /*!< [14..14] Bidirectional Transmit output enable                             */
      __IO uint16_t BDEN       : 1;            /*!< [15..15] Bidirectional  enable                                            */
    } CTL0_b;
  } ;
  __I  uint16_t  RESERVED;

  union {
    __IO uint16_t CTL1;                        /*!< (@ 0x00000004) control register 1                                         */

    struct {
      __IO uint16_t DMAREN     : 1;            /*!< [0..0] Rx buffer DMA enable                                               */
      __IO uint16_t DMATEN     : 1;            /*!< [1..1] Transmit Buffer DMA Enable                                         */
      __IO uint16_t NSSDRV     : 1;            /*!< [2..2] Drive NSS Output                                                   */
      __IO uint16_t NSSP       : 1;            /*!< [3..3] SPI NSS pulse mode enable                                          */
      __IO uint16_t TMOD       : 1;            /*!< [4..4] SPI TI mode enable                                                 */
      __IO uint16_t ERRIE      : 1;            /*!< [5..5] Error interrupt enable                                             */
      __IO uint16_t RBNEIE     : 1;            /*!< [6..6] RX buffer not empty interrupt enable                               */
      __IO uint16_t TBEIE      : 1;            /*!< [7..7] Tx buffer empty interrupt enable                                   */
            uint16_t            : 8;
    } CTL1_b;
  } ;
  __I  uint16_t  RESERVED1;

  union {
    __IO uint16_t STAT;                        /*!< (@ 0x00000008) status register                                            */

    struct {
      __I  uint16_t RBNE       : 1;            /*!< [0..0] Receive Buffer Not Empty                                           */
      __I  uint16_t TBE        : 1;            /*!< [1..1] Transmit Buffer Empty                                              */
      __I  uint16_t I2SCH      : 1;            /*!< [2..2] I2S channel side                                                   */
      __I  uint16_t TXURERR    : 1;            /*!< [3..3] Transmission underrun error bit                                    */
      __IO uint16_t CRCERR     : 1;            /*!< [4..4] SPI CRC Error Bit                                                  */
      __I  uint16_t CONFERR    : 1;            /*!< [5..5] SPI Configuration error                                            */
      __I  uint16_t RXORERR    : 1;            /*!< [6..6] Reception Overrun Error Bit                                        */
      __I  uint16_t TRANS      : 1;            /*!< [7..7] Transmitting On-going Bit                                          */
      __I  uint16_t FERR       : 1;            /*!< [8..8] Format error                                                       */
            uint16_t            : 7;
    } STAT_b;
  } ;
  __I  uint16_t  RESERVED2;

  union {
    __IO uint16_t DATA;                        /*!< (@ 0x0000000C) data register                                              */

    struct {
      __IO uint16_t SPI_DATA   : 16;           /*!< [15..0] Data transfer register                                            */
    } DATA_b;
  } ;
  __I  uint16_t  RESERVED3;

  union {
    __IO uint16_t CRCPOLY;                     /*!< (@ 0x00000010) CRC polynomial register                                    */

    struct {
      __IO uint16_t CRCPOLY    : 16;           /*!< [15..0] CRC polynomial value                                              */
    } CRCPOLY_b;
  } ;
  __I  uint16_t  RESERVED4;

  union {
    __I  uint16_t RCRC;                        /*!< (@ 0x00000014) RX CRC register                                            */

    struct {
      __I  uint16_t RCRC       : 16;           /*!< [15..0] RX CRC value                                                      */
    } RCRC_b;
  } ;
  __I  uint16_t  RESERVED5;

  union {
    __I  uint16_t TCRC;                        /*!< (@ 0x00000018) TX CRC register                                            */

    struct {
      __I  uint16_t TCRC       : 16;           /*!< [15..0] Tx CRC value                                                      */
    } TCRC_b;
  } ;
  __I  uint16_t  RESERVED6;

  union {
    __IO uint16_t I2SCTL;                      /*!< (@ 0x0000001C) I2S control register                                       */

    struct {
      __IO uint16_t CHLEN      : 1;            /*!< [0..0] Channel length (number of bits per audio channel)                  */
      __IO uint16_t DTLEN      : 2;            /*!< [2..1] Data length                                                        */
      __IO uint16_t CKPL       : 1;            /*!< [3..3] Idle state clock polarity                                          */
      __IO uint16_t I2SSTD     : 2;            /*!< [5..4] I2S standard selection                                             */
            uint16_t            : 1;
      __IO uint16_t PCMSMOD    : 1;            /*!< [7..7] PCM frame synchronization mode                                     */
      __IO uint16_t I2SOPMOD   : 2;            /*!< [9..8] I2S operation mode                                                 */
      __IO uint16_t I2SEN      : 1;            /*!< [10..10] I2S Enable                                                       */
      __IO uint16_t I2SSEL     : 1;            /*!< [11..11] I2S mode selection                                               */
            uint16_t            : 4;
    } I2SCTL_b;
  } ;
  __I  uint16_t  RESERVED7;

  union {
    __IO uint16_t I2SPSC;                      /*!< (@ 0x00000020) I2S prescaler register                                     */

    struct {
      __IO uint16_t DIV        : 8;            /*!< [7..0] Dividing factor for the prescaler                                  */
      __IO uint16_t OF         : 1;            /*!< [8..8] Odd factor for the prescaler                                       */
      __IO uint16_t MCKOEN     : 1;            /*!< [9..9] I2S_MCK output enable                                              */
            uint16_t            : 6;
    } I2SPSC_b;
  } ;
} SPI_Type;                                    /*!< Size = 34 (0x22)                                                          */



/* =========================================================================================================================== */
/* ================                                          TIMER                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief timers (TIMER)
  */

typedef struct {                                /*!< (@ 0x40012C00) TIMER0 Structure                                           */

  union {
    __IO uint16_t CTL0;                        /*!< (@ 0x00000000) control register 0                                         */

    struct {
      __IO uint16_t CEN        : 1;            /*!< [0..0] Counter enable                                                     */
      __IO uint16_t UPDIS      : 1;            /*!< [1..1] Update disable                                                     */
      __IO uint16_t UPS        : 1;            /*!< [2..2] Update source                                                      */
      __IO uint16_t SPM        : 1;            /*!< [3..3] Single pulse mode                                                  */
      __IO uint16_t DIR        : 1;            /*!< [4..4] Direction                                                          */
      __IO uint16_t CAM        : 2;            /*!< [6..5] Counter aligns mode selection                                      */
      __IO uint16_t ARSE       : 1;            /*!< [7..7] Auto-reload shadow enable                                          */
      __IO uint16_t CKDIV      : 2;            /*!< [9..8] Clock division                                                     */
            uint16_t            : 6;
    } CTL0_b;
  } ;
  __I  uint16_t  RESERVED;

  union {
    __IO uint16_t CTL1;                        /*!< (@ 0x00000004) control register 1                                         */

    struct {
      __IO uint16_t CCSE       : 1;            /*!< [0..0] Commutation control shadow enable                                  */
            uint16_t            : 1;
      __IO uint16_t CCUC       : 1;            /*!< [2..2] Commutation control shadow register update control                 */
      __IO uint16_t DMAS       : 1;            /*!< [3..3] DMA request source selection                                       */
      __IO uint16_t MMC        : 3;            /*!< [6..4] Master mode control                                                */
      __IO uint16_t TI0S       : 1;            /*!< [7..7] Channel 0 trigger input selection                                  */
      __IO uint16_t ISO0       : 1;            /*!< [8..8] Idle state of channel 0 output                                     */
      __IO uint16_t ISO0N      : 1;            /*!< [9..9] Idle state of channel 0 complementary output                       */
      __IO uint16_t ISO1       : 1;            /*!< [10..10] Idle state of channel 1 output                                   */
      __IO uint16_t ISO1N      : 1;            /*!< [11..11] Idle state of channel 1 complementary output                     */
      __IO uint16_t ISO2       : 1;            /*!< [12..12] Idle state of channel 2 output                                   */
      __IO uint16_t ISO2N      : 1;            /*!< [13..13] Idle state of channel 2 complementary output                     */
      __IO uint16_t ISO3       : 1;            /*!< [14..14] Idle state of channel 3 output                                   */
            uint16_t            : 1;
    } CTL1_b;
  } ;
  __I  uint16_t  RESERVED1;

  union {
    __IO uint16_t SMCFG;                       /*!< (@ 0x00000008) slave mode configuration register                          */

    struct {
      __IO uint16_t SMC        : 3;            /*!< [2..0] Slave mode selection                                               */
            uint16_t            : 1;
      __IO uint16_t TRGS       : 3;            /*!< [6..4] Trigger selection                                                  */
      __IO uint16_t MSM        : 1;            /*!< [7..7] Master/Slave mode                                                  */
      __IO uint16_t ETFC       : 4;            /*!< [11..8] External trigger filter control                                   */
      __IO uint16_t ETPSC      : 2;            /*!< [13..12] External trigger prescaler                                       */
      __IO uint16_t SMC1       : 1;            /*!< [14..14] Part of SMC for enable External clock mode1                      */
      __IO uint16_t ETP        : 1;            /*!< [15..15] External trigger polarity                                        */
    } SMCFG_b;
  } ;
  __I  uint16_t  RESERVED2;

  union {
    __IO uint16_t DMAINTEN;                    /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */

    struct {
      __IO uint16_t UPIE       : 1;            /*!< [0..0] Update interrupt enable                                            */
      __IO uint16_t CH0IE      : 1;            /*!< [1..1] Channel 0 capture/compare interrupt enable                         */
      __IO uint16_t CH1IE      : 1;            /*!< [2..2] Channel 1 capture/compare interrupt enable                         */
      __IO uint16_t CH2IE      : 1;            /*!< [3..3] Channel 2 capture/compare interrupt enable                         */
      __IO uint16_t CH3IE      : 1;            /*!< [4..4] Channel 3 capture/compare interrupt enable                         */
      __IO uint16_t CMTIE      : 1;            /*!< [5..5] commutation interrupt enable                                       */
      __IO uint16_t TRGIE      : 1;            /*!< [6..6] Trigger interrupt enable                                           */
      __IO uint16_t BRKIE      : 1;            /*!< [7..7] Break interrupt enable                                             */
      __IO uint16_t UPDEN      : 1;            /*!< [8..8] Update DMA request enable                                          */
      __IO uint16_t CH0DEN     : 1;            /*!< [9..9] Channel 0 capture/compare DMA request enable                       */
      __IO uint16_t CH1DEN     : 1;            /*!< [10..10] Channel 1 capture/compare DMA request enable                     */
      __IO uint16_t CH2DEN     : 1;            /*!< [11..11] Channel 2 capture/compare DMA request enable                     */
      __IO uint16_t CH3DEN     : 1;            /*!< [12..12] Channel 3 capture/compare DMA request enable                     */
      __IO uint16_t CMTDEN     : 1;            /*!< [13..13] Commutation DMA request enable                                   */
      __IO uint16_t TRGDEN     : 1;            /*!< [14..14] Trigger DMA request enable                                       */
            uint16_t            : 1;
    } DMAINTEN_b;
  } ;
  __I  uint16_t  RESERVED3;

  union {
    __IO uint16_t INTF;                        /*!< (@ 0x00000010) Interrupt flag register                                    */

    struct {
      __IO uint16_t UPIF       : 1;            /*!< [0..0] Update interrupt flag                                              */
      __IO uint16_t CH0IF      : 1;            /*!< [1..1] Channel 0 capture/compare interrupt flag                           */
      __IO uint16_t CH1IF      : 1;            /*!< [2..2] Channel 1 capture/compare interrupt flag                           */
      __IO uint16_t CH2IF      : 1;            /*!< [3..3] Channel 2 capture/compare interrupt flag                           */
      __IO uint16_t CH3IF      : 1;            /*!< [4..4] Channel 3 capture/compare interrupt flag                           */
      __IO uint16_t CMTIF      : 1;            /*!< [5..5] Channel commutation interrupt flag                                 */
      __IO uint16_t TRGIF      : 1;            /*!< [6..6] Trigger interrupt flag                                             */
      __IO uint16_t BRKIF      : 1;            /*!< [7..7] Break interrupt flag                                               */
            uint16_t            : 1;
      __IO uint16_t CH0OF      : 1;            /*!< [9..9] Channel 0 over capture flag                                        */
      __IO uint16_t CH1OF      : 1;            /*!< [10..10] Channel 1 over capture flag                                      */
      __IO uint16_t CH2OF      : 1;            /*!< [11..11] Channel 2 over capture flag                                      */
      __IO uint16_t CH3OF      : 1;            /*!< [12..12] Channel 3 over capture flag                                      */
            uint16_t            : 3;
    } INTF_b;
  } ;
  __I  uint16_t  RESERVED4;

  union {
    __O  uint16_t SWEVG;                       /*!< (@ 0x00000014) Software event generation register                         */

    struct {
      __O  uint16_t UPG        : 1;            /*!< [0..0] Update event generation                                            */
      __O  uint16_t CH0G       : 1;            /*!< [1..1] Channel 0 capture or compare event generation                      */
      __O  uint16_t CH1G       : 1;            /*!< [2..2] Channel 1 capture or compare event generation                      */
      __O  uint16_t CH2G       : 1;            /*!< [3..3] Channel 2 capture or compare event generation                      */
      __O  uint16_t CH3G       : 1;            /*!< [4..4] Channel 3 capture or compare event generation                      */
      __O  uint16_t CMTG       : 1;            /*!< [5..5] Channel commutation event generation                               */
      __O  uint16_t TRGG       : 1;            /*!< [6..6] Trigger event generation                                           */
      __O  uint16_t BRKG       : 1;            /*!< [7..7] Break event generation                                             */
            uint16_t            : 8;
    } SWEVG_b;
  } ;
  __I  uint16_t  RESERVED5;

  union {
    union {
      __IO uint16_t CHCTL0_Output;             /*!< (@ 0x00000018) Channel control register 0 (output mode)                   */

      struct {
        __IO uint16_t CH0MS    : 2;            /*!< [1..0] Channel 0 I/O mode selection                                       */
        __IO uint16_t CH0COMFEN : 1;           /*!< [2..2] Channel 0 output compare fast enable                               */
        __IO uint16_t CH0COMSEN : 1;           /*!< [3..3] Channel 0 compare output shadow enable                             */
        __IO uint16_t CH0COMCTL : 3;           /*!< [6..4] Channel 0 compare output control                                   */
        __IO uint16_t CH0COMCEN : 1;           /*!< [7..7] Channel 0 output compare clear enable                              */
        __IO uint16_t CH1MS    : 2;            /*!< [9..8] Channel 1 mode selection                                           */
        __IO uint16_t CH1COMFEN : 1;           /*!< [10..10] Channel 1 output compare fast enable                             */
        __IO uint16_t CH1COMSEN : 1;           /*!< [11..11] Channel 1 output compare shadow enable                           */
        __IO uint16_t CH1COMCTL : 3;           /*!< [14..12] Channel 1 compare output control                                 */
        __IO uint16_t CH1COMCEN : 1;           /*!< [15..15] Channel 1 output compare clear enable                            */
      } CHCTL0_Output_b;
    } ;

    union {
      __IO uint16_t CHCTL0_Input;              /*!< (@ 0x00000018) Channel control register 0 (input mode)                    */

      struct {
        __IO uint16_t CH0MS    : 2;            /*!< [1..0] Channel 0 mode selection                                           */
        __IO uint16_t CH0CAPPSC : 2;           /*!< [3..2] Channel 0 input capture prescaler                                  */
        __IO uint16_t CH0CAPFLT : 4;           /*!< [7..4] Channel 0 input capture filter control                             */
        __IO uint16_t CH1MS    : 2;            /*!< [9..8] Channel 1 mode selection                                           */
        __IO uint16_t CH1CAPPSC : 2;           /*!< [11..10] Channel 1 input capture prescaler                                */
        __IO uint16_t CH1CAPFLT : 4;           /*!< [15..12] Channel 1 input capture filter control                           */
      } CHCTL0_Input_b;
    } ;
  };
  __I  uint16_t  RESERVED6;

  union {
    union {
      __IO uint16_t CHCTL1_Output;             /*!< (@ 0x0000001C) Channel control register 1 (output mode)                   */

      struct {
        __IO uint16_t CH2MS    : 2;            /*!< [1..0] Channel 2 I/O mode selection                                       */
        __IO uint16_t CH2COMFEN : 1;           /*!< [2..2] Channel 2 output compare fast enable                               */
        __IO uint16_t CH2COMSEN : 1;           /*!< [3..3] Channel 2 compare output shadow enable                             */
        __IO uint16_t CH2COMCTL : 3;           /*!< [6..4] Channel 2 compare output control                                   */
        __IO uint16_t CH2COMCEN : 1;           /*!< [7..7] Channel 2 output compare clear enable                              */
        __IO uint16_t CH3MS    : 2;            /*!< [9..8] Channel 3 mode selection                                           */
        __IO uint16_t CH3COMFEN : 1;           /*!< [10..10] Channel 3 output compare fast enable                             */
        __IO uint16_t CH3COMSEN : 1;           /*!< [11..11] Channel 3 output compare shadow enable                           */
        __IO uint16_t CH3COMCTL : 3;           /*!< [14..12] Channel 3 compare output control                                 */
        __IO uint16_t CH3COMCEN : 1;           /*!< [15..15] Channel 3 output compare clear enable                            */
      } CHCTL1_Output_b;
    } ;

    union {
      __IO uint16_t CHCTL1_Input;              /*!< (@ 0x0000001C) Channel control register 1 (input mode)                    */

      struct {
        __IO uint16_t CH2MS    : 2;            /*!< [1..0] Channel 2 mode selection                                           */
        __IO uint16_t CH2CAPPSC : 2;           /*!< [3..2] Channel 2 input capture prescaler                                  */
        __IO uint16_t CH2CAPFLT : 4;           /*!< [7..4] Channel 2 input capture filter control                             */
        __IO uint16_t CH3MS    : 2;            /*!< [9..8] Channel 3 mode selection                                           */
        __IO uint16_t CH3CAPPSC : 2;           /*!< [11..10] Channel 3 input capture prescaler                                */
        __IO uint16_t CH3CAPFLT : 4;           /*!< [15..12] Channel 3 input capture filter control                           */
      } CHCTL1_Input_b;
    } ;
  };
  __I  uint16_t  RESERVED7;

  union {
    __IO uint16_t CHCTL2;                      /*!< (@ 0x00000020) Channel control register 2                                 */

    struct {
      __IO uint16_t CH0EN      : 1;            /*!< [0..0] Channel 0 capture/compare function enable                          */
      __IO uint16_t CH0P       : 1;            /*!< [1..1] Channel 0 capture/compare function polarity                        */
      __IO uint16_t CH0NEN     : 1;            /*!< [2..2] Channel 0 complementary output enable                              */
      __IO uint16_t CH0NP      : 1;            /*!< [3..3] Channel 0 complementary output polarity                            */
      __IO uint16_t CH1EN      : 1;            /*!< [4..4] Channel 1 capture/compare function enable                          */
      __IO uint16_t CH1P       : 1;            /*!< [5..5] Channel 1 capture/compare function polarity                        */
      __IO uint16_t CH1NEN     : 1;            /*!< [6..6] Channel 1 complementary output enable                              */
      __IO uint16_t CH1NP      : 1;            /*!< [7..7] Channel 1 complementary output polarity                            */
      __IO uint16_t CH2EN      : 1;            /*!< [8..8] Channel 2 capture/compare function enable                          */
      __IO uint16_t CH2P       : 1;            /*!< [9..9] Channel 2 capture/compare function polarity                        */
      __IO uint16_t CH2NEN     : 1;            /*!< [10..10] Channel 2 complementary output enable                            */
      __IO uint16_t CH2NP      : 1;            /*!< [11..11] Channel 2 complementary output polarity                          */
      __IO uint16_t CH3EN      : 1;            /*!< [12..12] Channel 3 capture/compare function enable                        */
      __IO uint16_t CH3P       : 1;            /*!< [13..13] Channel 3 capture/compare function polarity                      */
            uint16_t            : 2;
    } CHCTL2_b;
  } ;
  __I  uint16_t  RESERVED8;

  union {
    __IO uint16_t CNT;                         /*!< (@ 0x00000024) counter                                                    */

    struct {
      __IO uint16_t CNT        : 16;           /*!< [15..0] current counter value                                             */
    } CNT_b;
  } ;
  __I  uint16_t  RESERVED9;

  union {
    __IO uint16_t PSC;                         /*!< (@ 0x00000028) prescaler                                                  */

    struct {
      __IO uint16_t PSC        : 16;           /*!< [15..0] Prescaler value of the counter clock                              */
    } PSC_b;
  } ;
  __I  uint16_t  RESERVED10;

  union {
    __IO uint16_t CAR;                         /*!< (@ 0x0000002C) Counter auto reload register                               */

    struct {
      __IO uint16_t CARL       : 16;           /*!< [15..0] Counter auto reload value                                         */
    } CAR_b;
  } ;
  __I  uint16_t  RESERVED11;

  union {
    __IO uint16_t CREP;                        /*!< (@ 0x00000030) Counter repetition register                                */

    struct {
      __IO uint16_t CREP       : 8;            /*!< [7..0] Counter repetition value                                           */
            uint16_t            : 8;
    } CREP_b;
  } ;
  __I  uint16_t  RESERVED12;

  union {
    __IO uint16_t CH0CV;                       /*!< (@ 0x00000034) Channel 0 capture/compare value register                   */

    struct {
      __IO uint16_t CH0VAL     : 16;           /*!< [15..0] Capture or compare value of channel0                              */
    } CH0CV_b;
  } ;
  __I  uint16_t  RESERVED13;

  union {
    __IO uint16_t CH1CV;                       /*!< (@ 0x00000038) Channel 1 capture/compare value register                   */

    struct {
      __IO uint16_t CH1VAL     : 16;           /*!< [15..0] Capture or compare value of channel1                              */
    } CH1CV_b;
  } ;
  __I  uint16_t  RESERVED14;

  union {
    __IO uint16_t CH2CV;                       /*!< (@ 0x0000003C) Channel 2 capture/compare value register                   */

    struct {
      __IO uint16_t CH2VAL     : 16;           /*!< [15..0] Capture or compare value of channel 2                             */
    } CH2CV_b;
  } ;
  __I  uint16_t  RESERVED15;

  union {
    __IO uint16_t CH3CV;                       /*!< (@ 0x00000040) Channel 3 capture/compare value register                   */

    struct {
      __IO uint16_t CH3VAL     : 16;           /*!< [15..0] Capture or compare value of channel 3                             */
    } CH3CV_b;
  } ;
  __I  uint16_t  RESERVED16;

  union {
    __IO uint16_t CCHP;                        /*!< (@ 0x00000044) channel complementary protection register                  */

    struct {
      __IO uint16_t DTCFG      : 8;            /*!< [7..0] Dead time configure                                                */
      __IO uint16_t PROT       : 2;            /*!< [9..8] Complementary register protect control                             */
      __IO uint16_t IOS        : 1;            /*!< [10..10] Idle mode off-state configure                                    */
      __IO uint16_t ROS        : 1;            /*!< [11..11] Run mode off-state configure                                     */
      __IO uint16_t BRKEN      : 1;            /*!< [12..12] Break enable                                                     */
      __IO uint16_t BRKP       : 1;            /*!< [13..13] Break polarity                                                   */
      __IO uint16_t OAEN       : 1;            /*!< [14..14] Output automatic enable                                          */
      __IO uint16_t POEN       : 1;            /*!< [15..15] Primary output enable                                            */
    } CCHP_b;
  } ;
  __I  uint16_t  RESERVED17;

  union {
    __IO uint16_t DMACFG;                      /*!< (@ 0x00000048) DMA configuration register                                 */

    struct {
      __IO uint16_t DMATA      : 5;            /*!< [4..0] DMA transfer access start address                                  */
            uint16_t            : 3;
      __IO uint16_t DMATC      : 5;            /*!< [12..8] DMA transfer count                                                */
            uint16_t            : 3;
    } DMACFG_b;
  } ;
  __I  uint16_t  RESERVED18;

  union {
    __IO uint16_t DMATB;                       /*!< (@ 0x0000004C) DMA transfer buffer register                               */

    struct {
      __IO uint16_t DMATB      : 16;           /*!< [15..0] DMA transfer buffer                                               */
    } DMATB_b;
  } ;
} TIMER_Type;                                  /*!< Size = 78 (0x4e)                                                          */



/* =========================================================================================================================== */
/* ================                                          USART0                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Universal synchronous asynchronous receiver
      transmitter (USART0)
  */

typedef struct {                                /*!< (@ 0x40013800) USART0 Structure                                           */

  union {
    __IO uint32_t STAT;                        /*!< (@ 0x00000000) Status register                                            */

    struct {
      __I  uint32_t PERR       : 1;            /*!< [0..0] Parity error flag                                                  */
      __I  uint32_t FERR       : 1;            /*!< [1..1] Frame error flag                                                   */
      __I  uint32_t NERR       : 1;            /*!< [2..2] Noise error flag                                                   */
      __I  uint32_t ORERR      : 1;            /*!< [3..3] Overrun error                                                      */
      __I  uint32_t IDLEF      : 1;            /*!< [4..4] IDLE frame detected flag                                           */
      __IO uint32_t RBNE       : 1;            /*!< [5..5] Read data buffer not empty                                         */
      __IO uint32_t TC         : 1;            /*!< [6..6] Transmission complete                                              */
      __I  uint32_t TBE        : 1;            /*!< [7..7] Transmit data buffer empty                                         */
      __IO uint32_t LBDF       : 1;            /*!< [8..8] LIN break detection flag                                           */
      __IO uint32_t CTSF       : 1;            /*!< [9..9] CTS change flag                                                    */
            uint32_t            : 22;
    } STAT_b;
  } ;

  union {
    __IO uint32_t DATA;                        /*!< (@ 0x00000004) Data register                                              */

    struct {
      __IO uint32_t DATA       : 9;            /*!< [8..0] Transmit or read data value                                        */
            uint32_t            : 23;
    } DATA_b;
  } ;

  union {
    __IO uint32_t BAUD;                        /*!< (@ 0x00000008) Baud rate register                                         */

    struct {
      __IO uint32_t FRADIV     : 4;            /*!< [3..0] Fraction part of baud-rate divider                                 */
      __IO uint32_t INTDIV     : 12;           /*!< [15..4] Integer part of baud-rate divider                                 */
            uint32_t            : 16;
    } BAUD_b;
  } ;

  union {
    __IO uint32_t CTL0;                        /*!< (@ 0x0000000C) Control register 0                                         */

    struct {
      __IO uint32_t SBKCMD     : 1;            /*!< [0..0] Send break command                                                 */
      __IO uint32_t RWU        : 1;            /*!< [1..1] Receiver wakeup from mute mode                                     */
      __IO uint32_t REN        : 1;            /*!< [2..2] Receiver enable                                                    */
      __IO uint32_t TEN        : 1;            /*!< [3..3] Transmitter enable                                                 */
      __IO uint32_t IDLEIE     : 1;            /*!< [4..4] IDLE line detected interrupt enable                                */
      __IO uint32_t RBNEIE     : 1;            /*!< [5..5] Read data buffer not empty interrupt and overrun error
                                                     interrupt enable                                                          */
      __IO uint32_t TCIE       : 1;            /*!< [6..6] Transmission complete interrupt enable                             */
      __IO uint32_t TBEIE      : 1;            /*!< [7..7] Transmitter buffer empty interrupt enable                          */
      __IO uint32_t PERRIE     : 1;            /*!< [8..8] Parity error interrupt enable                                      */
      __IO uint32_t PM         : 1;            /*!< [9..9] Parity mode                                                        */
      __IO uint32_t PCEN       : 1;            /*!< [10..10] Parity check function enable                                     */
      __IO uint32_t WM         : 1;            /*!< [11..11] Wakeup method in mute mode                                       */
      __IO uint32_t WL         : 1;            /*!< [12..12] Word length                                                      */
      __IO uint32_t UEN        : 1;            /*!< [13..13] USART enable                                                     */
            uint32_t            : 18;
    } CTL0_b;
  } ;

  union {
    __IO uint32_t CTL1;                        /*!< (@ 0x00000010) Control register 1                                         */

    struct {
      __IO uint32_t ADDR       : 4;            /*!< [3..0] Address of the USART                                               */
            uint32_t            : 1;
      __IO uint32_t LBLEN      : 1;            /*!< [5..5] LIN break frame length                                             */
      __IO uint32_t LBDIE      : 1;            /*!< [6..6] LIN break detection interrupt enable                               */
            uint32_t            : 1;
      __IO uint32_t CLEN       : 1;            /*!< [8..8] CK Length                                                          */
      __IO uint32_t CPH        : 1;            /*!< [9..9] Clock phase                                                        */
      __IO uint32_t CPL        : 1;            /*!< [10..10] Clock polarity                                                   */
      __IO uint32_t CKEN       : 1;            /*!< [11..11] CK pin enable                                                    */
      __IO uint32_t STB        : 2;            /*!< [13..12] STOP bits length                                                 */
      __IO uint32_t LMEN       : 1;            /*!< [14..14] LIN mode enable                                                  */
            uint32_t            : 17;
    } CTL1_b;
  } ;

  union {
    __IO uint32_t CTL2;                        /*!< (@ 0x00000014) Control register 2                                         */

    struct {
      __IO uint32_t ERRIE      : 1;            /*!< [0..0] Error interrupt enable                                             */
      __IO uint32_t IREN       : 1;            /*!< [1..1] IrDA mode enable                                                   */
      __IO uint32_t IRLP       : 1;            /*!< [2..2] IrDA low-power                                                     */
      __IO uint32_t HDEN       : 1;            /*!< [3..3] Half-duplex selection                                              */
      __IO uint32_t NKEN       : 1;            /*!< [4..4] Smartcard NACK enable                                              */
      __IO uint32_t SCEN       : 1;            /*!< [5..5] Smartcard mode enable                                              */
      __IO uint32_t DENR       : 1;            /*!< [6..6] DMA request enable for reception                                   */
      __IO uint32_t DENT       : 1;            /*!< [7..7] DMA request enable for transmission                                */
      __IO uint32_t RTSEN      : 1;            /*!< [8..8] RTS enable                                                         */
      __IO uint32_t CTSEN      : 1;            /*!< [9..9] CTS enable                                                         */
      __IO uint32_t CTSIE      : 1;            /*!< [10..10] CTS interrupt enable                                             */
            uint32_t            : 21;
    } CTL2_b;
  } ;

  union {
    __IO uint32_t GP;                          /*!< (@ 0x00000018) Guard time and prescaler register                          */

    struct {
      __IO uint32_t PSC        : 8;            /*!< [7..0] Prescaler value                                                    */
      __IO uint32_t GUAT       : 8;            /*!< [15..8] Guard time value in Smartcard mode                                */
            uint32_t            : 16;
    } GP_b;
  } ;
} USART_Type;                                  /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                           UART3                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Universal  asynchronous receiver
      transmitter (UART3)
  */

typedef struct {                                /*!< (@ 0x40004C00) UART3 Structure                                            */

  union {
    __IO uint32_t STAT;                        /*!< (@ 0x00000000) Status register                                            */

    struct {
      __I  uint32_t PERR       : 1;            /*!< [0..0] Parity error flag                                                  */
      __I  uint32_t FERR       : 1;            /*!< [1..1] Frame error flag                                                   */
      __I  uint32_t NERR       : 1;            /*!< [2..2] Noise error flag                                                   */
      __I  uint32_t ORERR      : 1;            /*!< [3..3] Overrun error                                                      */
      __I  uint32_t IDLEF      : 1;            /*!< [4..4] IDLE frame detected flag                                           */
      __IO uint32_t RBNE       : 1;            /*!< [5..5] Read data buffer not empty                                         */
      __IO uint32_t TC         : 1;            /*!< [6..6] Transmission complete                                              */
      __I  uint32_t TBE        : 1;            /*!< [7..7] Transmit data buffer empty                                         */
      __IO uint32_t LBDF       : 1;            /*!< [8..8] LIN break detection flag                                           */
            uint32_t            : 23;
    } STAT_b;
  } ;

  union {
    __IO uint32_t DATA;                        /*!< (@ 0x00000004) Data register                                              */

    struct {
      __IO uint32_t DATA       : 9;            /*!< [8..0] Transmit or read data value                                        */
            uint32_t            : 23;
    } DATA_b;
  } ;

  union {
    __IO uint32_t BAUD;                        /*!< (@ 0x00000008) Baud rate register                                         */

    struct {
      __IO uint32_t FRADIV     : 4;            /*!< [3..0] Fraction part of baud-rate divider                                 */
      __IO uint32_t INTDIV     : 12;           /*!< [15..4] Integer part of baud-rate divider                                 */
            uint32_t            : 16;
    } BAUD_b;
  } ;

  union {
    __IO uint32_t CTL0;                        /*!< (@ 0x0000000C) Control register 0                                         */

    struct {
      __IO uint32_t SBKCMD     : 1;            /*!< [0..0] Send break command                                                 */
      __IO uint32_t RWU        : 1;            /*!< [1..1] Receiver wakeup from mute mode                                     */
      __IO uint32_t REN        : 1;            /*!< [2..2] Receiver enable                                                    */
      __IO uint32_t TEN        : 1;            /*!< [3..3] Transmitter enable                                                 */
      __IO uint32_t IDLEIE     : 1;            /*!< [4..4] IDLE line detected interrupt enable                                */
      __IO uint32_t RBNEIE     : 1;            /*!< [5..5] Read data buffer not empty interrupt and overrun error
                                                     interrupt enable                                                          */
      __IO uint32_t TCIE       : 1;            /*!< [6..6] Transmission complete interrupt enable                             */
      __IO uint32_t TBEIE      : 1;            /*!< [7..7] Transmitter buffer empty interrupt enable                          */
      __IO uint32_t PERRIE     : 1;            /*!< [8..8] Parity error interrupt enable                                      */
      __IO uint32_t PM         : 1;            /*!< [9..9] Parity mode                                                        */
      __IO uint32_t PCEN       : 1;            /*!< [10..10] Parity check function enable                                     */
      __IO uint32_t WM         : 1;            /*!< [11..11] Wakeup method in mute mode                                       */
      __IO uint32_t WL         : 1;            /*!< [12..12] Word length                                                      */
      __IO uint32_t UEN        : 1;            /*!< [13..13] USART enable                                                     */
            uint32_t            : 18;
    } CTL0_b;
  } ;

  union {
    __IO uint32_t CTL1;                        /*!< (@ 0x00000010) Control register 1                                         */

    struct {
      __IO uint32_t ADDR       : 4;            /*!< [3..0] Address of the USART                                               */
            uint32_t            : 1;
      __IO uint32_t LBLEN      : 1;            /*!< [5..5] LIN break frame length                                             */
      __IO uint32_t LBDIE      : 1;            /*!< [6..6] LIN break detection interrupt enable                               */
            uint32_t            : 5;
      __IO uint32_t STB        : 2;            /*!< [13..12] STOP bits length                                                 */
      __IO uint32_t LMEN       : 1;            /*!< [14..14] LIN mode enable                                                  */
            uint32_t            : 17;
    } CTL1_b;
  } ;

  union {
    __IO uint32_t CTL2;                        /*!< (@ 0x00000014) Control register 2                                         */

    struct {
      __IO uint32_t ERRIE      : 1;            /*!< [0..0] Error interrupt enable                                             */
      __IO uint32_t IREN       : 1;            /*!< [1..1] IrDA mode enable                                                   */
      __IO uint32_t IRLP       : 1;            /*!< [2..2] IrDA low-power                                                     */
      __IO uint32_t HDEN       : 1;            /*!< [3..3] Half-duplex selection                                              */
            uint32_t            : 2;
      __IO uint32_t DENR       : 1;            /*!< [6..6] DMA request enable for reception                                   */
      __IO uint32_t DENT       : 1;            /*!< [7..7] DMA request enable for transmission                                */
            uint32_t            : 24;
    } CTL2_b;
  } ;

  union {
    __IO uint32_t GP;                          /*!< (@ 0x00000018) Guard time and prescaler register                          */

    struct {
      __IO uint32_t PSC        : 8;            /*!< [7..0] Prescaler value                                                    */
            uint32_t            : 24;
    } GP_b;
  } ;
} UART_Type;                                   /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                       USBFS_GLOBAL                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief USB full speed global registers (USBFS_GLOBAL)
  */

typedef struct {                                /*!< (@ 0x50000000) USBFS_GLOBAL Structure                                     */

  union {
    __IO uint32_t GOTGCS;                      /*!< (@ 0x00000000) Global OTG control and status register  (USBFS_GOTGCS)     */

    struct {
      __I  uint32_t SRPS       : 1;            /*!< [0..0] SRP success                                                        */
      __IO uint32_t SRPREQ     : 1;            /*!< [1..1] SRP request                                                        */
            uint32_t            : 6;
      __I  uint32_t HNPS       : 1;            /*!< [8..8] Host success                                                       */
      __IO uint32_t HNPREQ     : 1;            /*!< [9..9] HNP request                                                        */
      __IO uint32_t HHNPEN     : 1;            /*!< [10..10] Host HNP enable                                                  */
      __IO uint32_t DHNPEN     : 1;            /*!< [11..11] Device HNP enabled                                               */
            uint32_t            : 4;
      __I  uint32_t IDPS       : 1;            /*!< [16..16] ID pin status                                                    */
      __I  uint32_t DI         : 1;            /*!< [17..17] Debounce interval                                                */
      __I  uint32_t ASV        : 1;            /*!< [18..18] A-session valid                                                  */
      __I  uint32_t BSV        : 1;            /*!< [19..19] B-session valid                                                  */
            uint32_t            : 12;
    } GOTGCS_b;
  } ;

  union {
    __IO uint32_t GOTGINTF;                    /*!< (@ 0x00000004) Global OTG interrupt flag register (USBFS_GOTGINTF)        */

    struct {
            uint32_t            : 2;
      __IO uint32_t SESEND     : 1;            /*!< [2..2] Session end                                                        */
            uint32_t            : 5;
      __IO uint32_t SRPEND     : 1;            /*!< [8..8] Session request success status change                              */
      __IO uint32_t HNPEND     : 1;            /*!< [9..9] HNP end                                                            */
            uint32_t            : 7;
      __IO uint32_t HNPDET     : 1;            /*!< [17..17] Host negotiation request detected                                */
      __IO uint32_t ADTO       : 1;            /*!< [18..18] A-device timeout                                                 */
      __IO uint32_t DF         : 1;            /*!< [19..19] Debounce finish                                                  */
            uint32_t            : 12;
    } GOTGINTF_b;
  } ;

  union {
    __IO uint32_t GAHBCS;                      /*!< (@ 0x00000008) Global AHB control and status register (USBFS_GAHBCS)      */

    struct {
      __IO uint32_t GINTEN     : 1;            /*!< [0..0] Global interrupt enable                                            */
            uint32_t            : 6;
      __IO uint32_t TXFTH      : 1;            /*!< [7..7] Tx FIFO threshold                                                  */
      __IO uint32_t PTXFTH     : 1;            /*!< [8..8] Periodic Tx FIFO threshold                                         */
            uint32_t            : 23;
    } GAHBCS_b;
  } ;

  union {
    __IO uint32_t GUSBCS;                      /*!< (@ 0x0000000C) Global USB control and status register (USBFS_GUSBCSR)     */

    struct {
      __IO uint32_t TOC        : 3;            /*!< [2..0] Timeout calibration                                                */
            uint32_t            : 5;
      __IO uint32_t SRPCEN     : 1;            /*!< [8..8] SRP capability enable                                              */
      __IO uint32_t HNPCEN     : 1;            /*!< [9..9] HNP capability enable                                              */
      __IO uint32_t UTT        : 4;            /*!< [13..10] USB turnaround time                                              */
            uint32_t            : 15;
      __IO uint32_t FHM        : 1;            /*!< [29..29] Force host mode                                                  */
      __IO uint32_t FDM        : 1;            /*!< [30..30] Force device mode                                                */
            uint32_t            : 1;
    } GUSBCS_b;
  } ;

  union {
    __IO uint32_t GRSTCTL;                     /*!< (@ 0x00000010) Global reset control register (USBFS_GRSTCTL)              */

    struct {
      __IO uint32_t CSRST      : 1;            /*!< [0..0] Core soft reset                                                    */
      __IO uint32_t HCSRST     : 1;            /*!< [1..1] HCLK soft reset                                                    */
      __IO uint32_t HFCRST     : 1;            /*!< [2..2] Host frame counter reset                                           */
            uint32_t            : 1;
      __IO uint32_t RXFF       : 1;            /*!< [4..4] RxFIFO flush                                                       */
      __IO uint32_t TXFF       : 1;            /*!< [5..5] TxFIFO flush                                                       */
      __IO uint32_t TXFNUM     : 5;            /*!< [10..6] TxFIFO number                                                     */
            uint32_t            : 21;
    } GRSTCTL_b;
  } ;

  union {
    __IO uint32_t GINTF;                       /*!< (@ 0x00000014) Global interrupt flag register (USBFS_GINTF)               */

    struct {
      __I  uint32_t COPM       : 1;            /*!< [0..0] Current operation mode                                             */
      __IO uint32_t MFIF       : 1;            /*!< [1..1] Mode fault interrupt flag                                          */
      __I  uint32_t OTGIF      : 1;            /*!< [2..2] OTG interrupt flag                                                 */
      __IO uint32_t SOF        : 1;            /*!< [3..3] Start of frame                                                     */
      __I  uint32_t RXFNEIF    : 1;            /*!< [4..4] RxFIFO non-empty interrupt flag                                    */
      __I  uint32_t NPTXFEIF   : 1;            /*!< [5..5] Non-periodic TxFIFO empty interrupt flag                           */
      __I  uint32_t GNPINAK    : 1;            /*!< [6..6] Global Non-Periodic IN NAK effective                               */
      __I  uint32_t GONAK      : 1;            /*!< [7..7] Global OUT NAK effective                                           */
            uint32_t            : 2;
      __IO uint32_t ESP        : 1;            /*!< [10..10] Early suspend                                                    */
      __IO uint32_t SP         : 1;            /*!< [11..11] USB suspend                                                      */
      __IO uint32_t RST        : 1;            /*!< [12..12] USB reset                                                        */
      __IO uint32_t ENUMF      : 1;            /*!< [13..13] Enumeration finished                                             */
      __IO uint32_t ISOOPDIF   : 1;            /*!< [14..14] Isochronous OUT packet dropped interrupt                         */
      __IO uint32_t EOPFIF     : 1;            /*!< [15..15] End of periodic frame interrupt flag                             */
            uint32_t            : 2;
      __I  uint32_t IEPIF      : 1;            /*!< [18..18] IN endpoint interrupt flag                                       */
      __I  uint32_t OEPIF      : 1;            /*!< [19..19] OUT endpoint interrupt flag                                      */
      __IO uint32_t ISOINCIF   : 1;            /*!< [20..20] Isochronous IN transfer Not Complete Interrupt Flag              */
      __IO uint32_t PXNCIF_ISOONCIF : 1;       /*!< [21..21] periodic transfer not complete interrupt flag(Host
                                                     mode)/isochronous OUT transfer not complete interrupt flag(Device
                                                     mode)                                                                     */
            uint32_t            : 2;
      __I  uint32_t HPIF       : 1;            /*!< [24..24] Host port interrupt flag                                         */
      __I  uint32_t HCIF       : 1;            /*!< [25..25] Host channels interrupt flag                                     */
      __I  uint32_t PTXFEIF    : 1;            /*!< [26..26] Periodic TxFIFO empty interrupt flag                             */
            uint32_t            : 1;
      __IO uint32_t IDPSC      : 1;            /*!< [28..28] ID pin status change                                             */
      __IO uint32_t DISCIF     : 1;            /*!< [29..29] Disconnect interrupt flag                                        */
      __IO uint32_t SESIF      : 1;            /*!< [30..30] Session interrupt flag                                           */
      __IO uint32_t WKUPIF     : 1;            /*!< [31..31] Wakeup interrupt flag                                            */
    } GINTF_b;
  } ;

  union {
    __IO uint32_t GINTEN;                      /*!< (@ 0x00000018) Global interrupt enable register (USBFS_GINTEN)            */

    struct {
            uint32_t            : 1;
      __IO uint32_t MFIE       : 1;            /*!< [1..1] Mode fault interrupt enable                                        */
      __IO uint32_t OTGIE      : 1;            /*!< [2..2] OTG interrupt enable                                               */
      __IO uint32_t SOFIE      : 1;            /*!< [3..3] Start of frame interrupt enable                                    */
      __IO uint32_t RXFNEIE    : 1;            /*!< [4..4] Receive FIFO non-empty interrupt enable                            */
      __IO uint32_t NPTXFEIE   : 1;            /*!< [5..5] Non-periodic TxFIFO empty interrupt enable                         */
      __IO uint32_t GNPINAKIE  : 1;            /*!< [6..6] Global non-periodic IN NAK effective interrupt enable              */
      __IO uint32_t GONAKIE    : 1;            /*!< [7..7] Global OUT NAK effective interrupt enable                          */
            uint32_t            : 2;
      __IO uint32_t ESPIE      : 1;            /*!< [10..10] Early suspend interrupt enable                                   */
      __IO uint32_t SPIE       : 1;            /*!< [11..11] USB suspend interrupt enable                                     */
      __IO uint32_t RSTIE      : 1;            /*!< [12..12] USB reset interrupt enable                                       */
      __IO uint32_t ENUMFIE    : 1;            /*!< [13..13] Enumeration finish interrupt enable                              */
      __IO uint32_t ISOOPDIE   : 1;            /*!< [14..14] Isochronous OUT packet dropped interrupt enable                  */
      __IO uint32_t EOPFIE     : 1;            /*!< [15..15] End of periodic frame interrupt enable                           */
            uint32_t            : 2;
      __IO uint32_t IEPIE      : 1;            /*!< [18..18] IN endpoints interrupt enable                                    */
      __IO uint32_t OEPIE      : 1;            /*!< [19..19] OUT endpoints interrupt enable                                   */
      __IO uint32_t ISOINCIE   : 1;            /*!< [20..20] isochronous IN transfer not complete interrupt enable            */
      __IO uint32_t PXNCIE_ISOONCIE : 1;       /*!< [21..21] periodic transfer not compelete Interrupt enable(Host
                                                     mode)/isochronous OUT transfer not complete interrupt enable(Device
                                                     mode)                                                                     */
            uint32_t            : 2;
      __I  uint32_t HPIE       : 1;            /*!< [24..24] Host port interrupt enable                                       */
      __IO uint32_t HCIE       : 1;            /*!< [25..25] Host channels interrupt enable                                   */
      __IO uint32_t PTXFEIE    : 1;            /*!< [26..26] Periodic TxFIFO empty interrupt enable                           */
            uint32_t            : 1;
      __IO uint32_t IDPSCIE    : 1;            /*!< [28..28] ID pin status change interrupt enable                            */
      __IO uint32_t DISCIE     : 1;            /*!< [29..29] Disconnect interrupt enable                                      */
      __IO uint32_t SESIE      : 1;            /*!< [30..30] Session interrupt enable                                         */
      __IO uint32_t WKUPIE     : 1;            /*!< [31..31] Wakeup interrupt enable                                          */
    } GINTEN_b;
  } ;

  union {
    union {
      __I  uint32_t GRSTATR_Device;            /*!< (@ 0x0000001C) Global Receive status read(Device mode)                    */

      struct {
        __I  uint32_t EPNUM    : 4;            /*!< [3..0] Endpoint number                                                    */
        __I  uint32_t BCOUNT   : 11;           /*!< [14..4] Byte count                                                        */
        __I  uint32_t DPID     : 2;            /*!< [16..15] Data PID                                                         */
        __I  uint32_t RPCKST   : 4;            /*!< [20..17] Recieve packet status                                            */
              uint32_t          : 11;
      } GRSTATR_Device_b;
    } ;

    union {
      __I  uint32_t GRSTATR_Host;              /*!< (@ 0x0000001C) Global Receive status read(Host mode)                      */

      struct {
        __I  uint32_t CNUM     : 4;            /*!< [3..0] Channel number                                                     */
        __I  uint32_t BCOUNT   : 11;           /*!< [14..4] Byte count                                                        */
        __I  uint32_t DPID     : 2;            /*!< [16..15] Data PID                                                         */
        __I  uint32_t RPCKST   : 4;            /*!< [20..17] Reivece packet status                                            */
              uint32_t          : 11;
      } GRSTATR_Host_b;
    } ;
  };

  union {
    union {
      __I  uint32_t GRSTATP_Device;            /*!< (@ 0x00000020) Global Receive status pop(Device mode)                     */

      struct {
        __I  uint32_t EPNUM    : 4;            /*!< [3..0] Endpoint number                                                    */
        __I  uint32_t BCOUNT   : 11;           /*!< [14..4] Byte count                                                        */
        __I  uint32_t DPID     : 2;            /*!< [16..15] Data PID                                                         */
        __I  uint32_t RPCKST   : 4;            /*!< [20..17] Recieve packet status                                            */
              uint32_t          : 11;
      } GRSTATP_Device_b;
    } ;

    union {
      __I  uint32_t GRSTATP_Host;              /*!< (@ 0x00000020) Global Receive status pop(Host mode)                       */

      struct {
        __I  uint32_t CNUM     : 4;            /*!< [3..0] Channel number                                                     */
        __I  uint32_t BCOUNT   : 11;           /*!< [14..4] Byte count                                                        */
        __I  uint32_t DPID     : 2;            /*!< [16..15] Data PID                                                         */
        __I  uint32_t RPCKST   : 4;            /*!< [20..17] Reivece packet status                                            */
              uint32_t          : 11;
      } GRSTATP_Host_b;
    } ;
  };

  union {
    __IO uint32_t GRFLEN;                      /*!< (@ 0x00000024) Global Receive FIFO size register (USBFS_GRFLEN)           */

    struct {
      __IO uint32_t RXFD       : 16;           /*!< [15..0] Rx FIFO depth                                                     */
            uint32_t            : 16;
    } GRFLEN_b;
  } ;

  union {
    union {
      __IO uint32_t HNPTFLEN;                  /*!< (@ 0x00000028) Host non-periodic transmit FIFO length register
                                                                    (Host mode)                                                */

      struct {
        __IO uint32_t HNPTXRSAR : 16;          /*!< [15..0] host non-periodic transmit Tx RAM start address                   */
        __IO uint32_t HNPTXFD  : 16;           /*!< [31..16] host non-periodic TxFIFO depth                                   */
      } HNPTFLEN_b;
    } ;

    union {
      __IO uint32_t DIEP0TFLEN;                /*!< (@ 0x00000028) Device IN endpoint 0 transmit FIFO length (Device
                                                                    mode)                                                      */

      struct {
        __IO uint32_t IEP0TXRSAR : 16;         /*!< [15..0] in endpoint 0 Tx RAM start address                                */
        __IO uint32_t IEP0TXFD : 16;           /*!< [31..16] in endpoint 0 Tx FIFO depth                                      */
      } DIEP0TFLEN_b;
    } ;
  };

  union {
    __I  uint32_t HNPTFQSTAT;                  /*!< (@ 0x0000002C) Host non-periodic transmit FIFO/queue status
                                                                    register (HNPTFQSTAT)                                      */

    struct {
      __I  uint32_t NPTXFS     : 16;           /*!< [15..0] Non-periodic TxFIFO space                                         */
      __I  uint32_t NPTXRQS    : 8;            /*!< [23..16] Non-periodic transmit request queue space                        */
      __I  uint32_t NPTXRQTOP  : 7;            /*!< [30..24] Top of the non-periodic transmit request queue                   */
            uint32_t            : 1;
    } HNPTFQSTAT_b;
  } ;
  __I  uint32_t  RESERVED[2];

  union {
    __IO uint32_t GCCFG;                       /*!< (@ 0x00000038) Global core configuration register (USBFS_GCCFG)           */

    struct {
            uint32_t            : 16;
      __IO uint32_t PWRON      : 1;            /*!< [16..16] Power on                                                         */
            uint32_t            : 1;
      __IO uint32_t VBUSACEN   : 1;            /*!< [18..18] The VBUS A-device Comparer enable                                */
      __IO uint32_t VBUSBCEN   : 1;            /*!< [19..19] The VBUS B-device Comparer enable                                */
      __IO uint32_t SOFOEN     : 1;            /*!< [20..20] SOF output enable                                                */
      __IO uint32_t VBUSIG     : 1;            /*!< [21..21] VBUS ignored                                                     */
            uint32_t            : 10;
    } GCCFG_b;
  } ;

  union {
    __IO uint32_t CID;                         /*!< (@ 0x0000003C) core ID register                                           */

    struct {
      __IO uint32_t CID        : 32;           /*!< [31..0] Core ID                                                           */
    } CID_b;
  } ;
  __I  uint32_t  RESERVED1[48];

  union {
    __IO uint32_t HPTFLEN;                     /*!< (@ 0x00000100) Host periodic transmit FIFO length register (HPTFLEN)      */

    struct {
      __IO uint32_t HPTXFSAR   : 16;           /*!< [15..0] Host periodic TxFIFO start address                                */
      __IO uint32_t HPTXFD     : 16;           /*!< [31..16] Host periodic TxFIFO depth                                       */
    } HPTFLEN_b;
  } ;

  union {
    __IO uint32_t DIEP1TFLEN;                  /*!< (@ 0x00000104) device IN endpoint transmit FIFO size register
                                                                    (DIEP1TFLEN)                                               */

    struct {
      __IO uint32_t IEPTXRSAR  : 16;           /*!< [15..0] IN endpoint FIFO transmit RAM start address                       */
      __IO uint32_t IEPTXFD    : 16;           /*!< [31..16] IN endpoint TxFIFO depth                                         */
    } DIEP1TFLEN_b;
  } ;

  union {
    __IO uint32_t DIEP2TFLEN;                  /*!< (@ 0x00000108) device IN endpoint transmit FIFO size register
                                                                    (DIEP2TFLEN)                                               */

    struct {
      __IO uint32_t IEPTXRSAR  : 16;           /*!< [15..0] IN endpoint FIFO transmit RAM start address                       */
      __IO uint32_t IEPTXFD    : 16;           /*!< [31..16] IN endpoint TxFIFO depth                                         */
    } DIEP2TFLEN_b;
  } ;

  union {
    __IO uint32_t DIEP3TFLEN;                  /*!< (@ 0x0000010C) device IN endpoint transmit FIFO size register
                                                                    (FS_DIEP3TXFLEN)                                           */

    struct {
      __IO uint32_t IEPTXRSAR  : 16;           /*!< [15..0] IN endpoint FIFO4 transmit RAM start address                      */
      __IO uint32_t IEPTXFD    : 16;           /*!< [31..16] IN endpoint TxFIFO depth                                         */
    } DIEP3TFLEN_b;
  } ;
} USBFS_GLOBAL_Type;                            /*!< Size = 272 (0x110)                                                        */



/* =========================================================================================================================== */
/* ================                                        USBFS_HOST                                         ================ */
/* =========================================================================================================================== */


/**
  * @brief USB on the go full speed host (USBFS_HOST)
  */

typedef struct {                                /*!< (@ 0x50000400) USBFS_HOST Structure                                       */

  union {
    __IO uint32_t HCTL;                        /*!< (@ 0x00000000) host configuration register (HCTL)                         */

    struct {
      __IO uint32_t CLKSEL     : 2;            /*!< [1..0] clock select for USB clock                                         */
            uint32_t            : 30;
    } HCTL_b;
  } ;

  union {
    __IO uint32_t HFT;                         /*!< (@ 0x00000004) Host frame interval register                               */

    struct {
      __IO uint32_t FRI        : 16;           /*!< [15..0] Frame interval                                                    */
            uint32_t            : 16;
    } HFT_b;
  } ;

  union {
    __I  uint32_t HFINFR;                      /*!< (@ 0x00000008) FS host frame number/frame time remaining register
                                                                    (HFINFR)                                                   */

    struct {
      __I  uint32_t FRNUM      : 16;           /*!< [15..0] Frame number                                                      */
      __I  uint32_t FRT        : 16;           /*!< [31..16] Frame remaining time                                             */
    } HFINFR_b;
  } ;
  __I  uint32_t  RESERVED;

  union {
    __IO uint32_t HPTFQSTAT;                   /*!< (@ 0x00000010) Host periodic transmit FIFO/queue status register
                                                                    (HPTFQSTAT)                                                */

    struct {
      __I  uint32_t PTXFS      : 16;           /*!< [15..0] Periodic transmit data FIFO space available                       */
      __I  uint32_t PTXREQS    : 8;            /*!< [23..16] Periodic transmit request queue space available                  */
      __I  uint32_t PTXREQT    : 8;            /*!< [31..24] Top of the periodic transmit request queue                       */
    } HPTFQSTAT_b;
  } ;

  union {
    __I  uint32_t HACHINT;                     /*!< (@ 0x00000014) Host all channels interrupt register                       */

    struct {
      __I  uint32_t HACHINT    : 8;            /*!< [7..0] Host all channel interrupts                                        */
            uint32_t            : 24;
    } HACHINT_b;
  } ;

  union {
    __IO uint32_t HACHINTEN;                   /*!< (@ 0x00000018) host all channels interrupt mask register                  */

    struct {
      __IO uint32_t CINTEN     : 8;            /*!< [7..0] Channel interrupt enable                                           */
            uint32_t            : 24;
    } HACHINTEN_b;
  } ;
  __I  uint32_t  RESERVED1[9];

  union {
    __IO uint32_t HPCS;                        /*!< (@ 0x00000040) Host port control and status register (USBFS_HPCS)         */

    struct {
      __I  uint32_t PCST       : 1;            /*!< [0..0] Port connect status                                                */
      __IO uint32_t PCD        : 1;            /*!< [1..1] Port connect detected                                              */
      __IO uint32_t PE         : 1;            /*!< [2..2] Port enable                                                        */
      __IO uint32_t PEDC       : 1;            /*!< [3..3] Port enable/disable change                                         */
            uint32_t            : 2;
      __IO uint32_t PREM       : 1;            /*!< [6..6] Port resume                                                        */
      __IO uint32_t PSP        : 1;            /*!< [7..7] Port suspend                                                       */
      __IO uint32_t PRST       : 1;            /*!< [8..8] Port reset                                                         */
            uint32_t            : 1;
      __I  uint32_t PLST       : 2;            /*!< [11..10] Port line status                                                 */
      __IO uint32_t PP         : 1;            /*!< [12..12] Port power                                                       */
            uint32_t            : 4;
      __I  uint32_t PS         : 2;            /*!< [18..17] Port speed                                                       */
            uint32_t            : 13;
    } HPCS_b;
  } ;
  __I  uint32_t  RESERVED2[47];

  union {
    __IO uint32_t HCH0CTL;                     /*!< (@ 0x00000100) host channel-0 characteristics register (HCH0CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH0CTL_b;
  } ;
  __I  uint32_t  RESERVED3;

  union {
    __IO uint32_t HCH0INTF;                    /*!< (@ 0x00000108) host channel-0 interrupt register (USBFS_HCHxINTF)         */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH0INTF_b;
  } ;

  union {
    __IO uint32_t HCH0INTEN;                   /*!< (@ 0x0000010C) host channel-0 interrupt enable register (HCH0INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH0INTEN_b;
  } ;

  union {
    __IO uint32_t HCH0LEN;                     /*!< (@ 0x00000110) host channel-0 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH0LEN_b;
  } ;
  __I  uint32_t  RESERVED4[3];

  union {
    __IO uint32_t HCH1CTL;                     /*!< (@ 0x00000120) host channel-1 characteristics register (HCH1CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH1CTL_b;
  } ;
  __I  uint32_t  RESERVED5;

  union {
    __IO uint32_t HCH1INTF;                    /*!< (@ 0x00000128) host channel-1 interrupt register (HCH1INTF)               */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH1INTF_b;
  } ;

  union {
    __IO uint32_t HCH1INTEN;                   /*!< (@ 0x0000012C) host channel-1 interrupt enable register (HCH1INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH1INTEN_b;
  } ;

  union {
    __IO uint32_t HCH1LEN;                     /*!< (@ 0x00000130) host channel-1 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH1LEN_b;
  } ;
  __I  uint32_t  RESERVED6[3];

  union {
    __IO uint32_t HCH2CTL;                     /*!< (@ 0x00000140) host channel-2 characteristics register (HCH2CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH2CTL_b;
  } ;
  __I  uint32_t  RESERVED7;

  union {
    __IO uint32_t HCH2INTF;                    /*!< (@ 0x00000148) host channel-2 interrupt register (HCH2INTF)               */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH2INTF_b;
  } ;

  union {
    __IO uint32_t HCH2INTEN;                   /*!< (@ 0x0000014C) host channel-2 interrupt enable register (HCH2INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH2INTEN_b;
  } ;

  union {
    __IO uint32_t HCH2LEN;                     /*!< (@ 0x00000150) host channel-2 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH2LEN_b;
  } ;
  __I  uint32_t  RESERVED8[3];

  union {
    __IO uint32_t HCH3CTL;                     /*!< (@ 0x00000160) host channel-3 characteristics register (HCH3CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH3CTL_b;
  } ;
  __I  uint32_t  RESERVED9;

  union {
    __IO uint32_t HCH3INTF;                    /*!< (@ 0x00000168) host channel-3 interrupt register (HCH3INTF)               */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH3INTF_b;
  } ;

  union {
    __IO uint32_t HCH3INTEN;                   /*!< (@ 0x0000016C) host channel-3 interrupt enable register (HCH3INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH3INTEN_b;
  } ;

  union {
    __IO uint32_t HCH3LEN;                     /*!< (@ 0x00000170) host channel-3 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH3LEN_b;
  } ;
  __I  uint32_t  RESERVED10[3];

  union {
    __IO uint32_t HCH4CTL;                     /*!< (@ 0x00000180) host channel-4 characteristics register (HCH4CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH4CTL_b;
  } ;
  __I  uint32_t  RESERVED11;

  union {
    __IO uint32_t HCH4INTF;                    /*!< (@ 0x00000188) host channel-4 interrupt register (HCH4INTF)               */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH4INTF_b;
  } ;

  union {
    __IO uint32_t HCH4INTEN;                   /*!< (@ 0x0000018C) host channel-4 interrupt enable register (HCH4INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH4INTEN_b;
  } ;

  union {
    __IO uint32_t HCH4LEN;                     /*!< (@ 0x00000190) host channel-4 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH4LEN_b;
  } ;
  __I  uint32_t  RESERVED12[3];

  union {
    __IO uint32_t HCH5CTL;                     /*!< (@ 0x000001A0) host channel-5 characteristics register (HCH5CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH5CTL_b;
  } ;
  __I  uint32_t  RESERVED13;

  union {
    __IO uint32_t HCH5INTF;                    /*!< (@ 0x000001A8) host channel-5 interrupt register (HCH5INTF)               */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH5INTF_b;
  } ;

  union {
    __IO uint32_t HCH5INTEN;                   /*!< (@ 0x000001AC) host channel-5 interrupt enable register (HCH5INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH5INTEN_b;
  } ;

  union {
    __IO uint32_t HCH5LEN;                     /*!< (@ 0x000001B0) host channel-5 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH5LEN_b;
  } ;
  __I  uint32_t  RESERVED14[3];

  union {
    __IO uint32_t HCH6CTL;                     /*!< (@ 0x000001C0) host channel-6 characteristics register (HCH6CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH6CTL_b;
  } ;
  __I  uint32_t  RESERVED15;

  union {
    __IO uint32_t HCH6INTF;                    /*!< (@ 0x000001C8) host channel-6 interrupt register (HCH6INTF)               */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH6INTF_b;
  } ;

  union {
    __IO uint32_t HCH6INTEN;                   /*!< (@ 0x000001CC) host channel-6 interrupt enable register (HCH6INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH6INTEN_b;
  } ;

  union {
    __IO uint32_t HCH6LEN;                     /*!< (@ 0x000001D0) host channel-6 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH6LEN_b;
  } ;
  __I  uint32_t  RESERVED16[3];

  union {
    __IO uint32_t HCH7CTL;                     /*!< (@ 0x000001E0) host channel-7 characteristics register (HCH7CTL)          */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] Maximum packet size                                               */
      __IO uint32_t EPNUM      : 4;            /*!< [14..11] Endpoint number                                                  */
      __IO uint32_t EPDIR      : 1;            /*!< [15..15] Endpoint direction                                               */
            uint32_t            : 1;
      __IO uint32_t LSD        : 1;            /*!< [17..17] Low-speed device                                                 */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 2;
      __IO uint32_t DAR        : 7;            /*!< [28..22] Device address                                                   */
      __IO uint32_t ODDFRM     : 1;            /*!< [29..29] Odd frame                                                        */
      __IO uint32_t CDIS       : 1;            /*!< [30..30] Channel disable                                                  */
      __IO uint32_t CEN        : 1;            /*!< [31..31] Channel enable                                                   */
    } HCH7CTL_b;
  } ;
  __I  uint32_t  RESERVED17;

  union {
    __IO uint32_t HCH7INTF;                    /*!< (@ 0x000001E8) host channel-7 interrupt register (HCH7INTF)               */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t CH         : 1;            /*!< [1..1] Channel halted                                                     */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [3..3] STALL response received interrupt                                  */
      __IO uint32_t NAK        : 1;            /*!< [4..4] NAK response received interrupt                                    */
      __IO uint32_t ACK        : 1;            /*!< [5..5] ACK response received/transmitted interrupt                        */
            uint32_t            : 1;
      __IO uint32_t USBER      : 1;            /*!< [7..7] USB bus error                                                      */
      __IO uint32_t BBER       : 1;            /*!< [8..8] Babble error                                                       */
      __IO uint32_t REQOVR     : 1;            /*!< [9..9] Request queue overrun                                              */
      __IO uint32_t DTER       : 1;            /*!< [10..10] Data toggle error                                                */
            uint32_t            : 21;
    } HCH7INTF_b;
  } ;

  union {
    __IO uint32_t HCH7INTEN;                   /*!< (@ 0x000001EC) host channel-7 interrupt enable register (HCH7INTEN)       */

    struct {
      __IO uint32_t TFIE       : 1;            /*!< [0..0] Transfer completed interrupt enable                                */
      __IO uint32_t CHIE       : 1;            /*!< [1..1] Channel halted interrupt enable                                    */
            uint32_t            : 1;
      __IO uint32_t STALLIE    : 1;            /*!< [3..3] STALL interrupt enable                                             */
      __IO uint32_t NAKIE      : 1;            /*!< [4..4] NAK interrupt enable                                               */
      __IO uint32_t ACKIE      : 1;            /*!< [5..5] ACK interrupt enable                                               */
            uint32_t            : 1;
      __IO uint32_t USBERIE    : 1;            /*!< [7..7] USB bus error interrupt enable                                     */
      __IO uint32_t BBERIE     : 1;            /*!< [8..8] Babble error interrupt enable                                      */
      __IO uint32_t REQOVRIE   : 1;            /*!< [9..9] request queue overrun interrupt enable                             */
      __IO uint32_t DTERIE     : 1;            /*!< [10..10] Data toggle error interrupt enable                               */
            uint32_t            : 21;
    } HCH7INTEN_b;
  } ;

  union {
    __IO uint32_t HCH7LEN;                     /*!< (@ 0x000001F0) host channel-7 transfer length register                    */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t DPID       : 2;            /*!< [30..29] Data PID                                                         */
            uint32_t            : 1;
    } HCH7LEN_b;
  } ;
} USBFS_HOST_Type;                              /*!< Size = 500 (0x1f4)                                                        */



/* =========================================================================================================================== */
/* ================                                       USBFS_DEVICE                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief USB on the go full speed device (USBFS_DEVICE)
  */

typedef struct {                                /*!< (@ 0x50000800) USBFS_DEVICE Structure                                     */

  union {
    __IO uint32_t DCFG;                        /*!< (@ 0x00000000) device configuration register (DCFG)                       */

    struct {
      __IO uint32_t DS         : 2;            /*!< [1..0] Device speed                                                       */
      __IO uint32_t NZLSOH     : 1;            /*!< [2..2] Non-zero-length status OUT handshake                               */
            uint32_t            : 1;
      __IO uint32_t DAR        : 7;            /*!< [10..4] Device address                                                    */
      __IO uint32_t EOPFT      : 2;            /*!< [12..11] end of periodic frame time                                       */
            uint32_t            : 19;
    } DCFG_b;
  } ;

  union {
    __IO uint32_t DCTL;                        /*!< (@ 0x00000004) device control register (DCTL)                             */

    struct {
      __IO uint32_t RWKUP      : 1;            /*!< [0..0] Remote wakeup                                                      */
      __IO uint32_t SD         : 1;            /*!< [1..1] Soft disconnect                                                    */
      __I  uint32_t GINS       : 1;            /*!< [2..2] Global IN NAK status                                               */
      __I  uint32_t GONS       : 1;            /*!< [3..3] Global OUT NAK status                                              */
            uint32_t            : 3;
      __O  uint32_t SGINAK     : 1;            /*!< [7..7] Set global IN NAK                                                  */
      __O  uint32_t CGINAK     : 1;            /*!< [8..8] Clear global IN NAK                                                */
      __O  uint32_t SGONAK     : 1;            /*!< [9..9] Set global OUT NAK                                                 */
      __O  uint32_t CGONAK     : 1;            /*!< [10..10] Clear global OUT NAK                                             */
      __IO uint32_t POIF       : 1;            /*!< [11..11] Power-on initialization flag                                     */
            uint32_t            : 20;
    } DCTL_b;
  } ;

  union {
    __I  uint32_t DSTAT;                       /*!< (@ 0x00000008) device status register (DSTAT)                             */

    struct {
      __I  uint32_t SPST       : 1;            /*!< [0..0] Suspend status                                                     */
      __I  uint32_t ES         : 2;            /*!< [2..1] Enumerated speed                                                   */
            uint32_t            : 5;
      __I  uint32_t FNRSOF     : 14;           /*!< [21..8] Frame number of the received SOF                                  */
            uint32_t            : 10;
    } DSTAT_b;
  } ;
  __I  uint32_t  RESERVED;

  union {
    __IO uint32_t DIEPINTEN;                   /*!< (@ 0x00000010) device IN endpoint common interrupt mask register
                                                                    (DIEPINTEN)                                                */

    struct {
      __IO uint32_t TFEN       : 1;            /*!< [0..0] Transfer finished interrupt enable                                 */
      __IO uint32_t EPDISEN    : 1;            /*!< [1..1] Endpoint disabled interrupt enable                                 */
            uint32_t            : 1;
      __IO uint32_t CITOEN     : 1;            /*!< [3..3] Control IN timeout condition interrupt enable (Non-isochronous
                                                     endpoints)                                                                */
      __IO uint32_t EPTXFUDEN  : 1;            /*!< [4..4] Endpoint Tx FIFO underrun interrupt enable bit                     */
            uint32_t            : 1;
      __IO uint32_t IEPNEEN    : 1;            /*!< [6..6] IN endpoint NAK effective interrupt enable                         */
            uint32_t            : 25;
    } DIEPINTEN_b;
  } ;

  union {
    __IO uint32_t DOEPINTEN;                   /*!< (@ 0x00000014) device OUT endpoint common interrupt enable register
                                                                    (DOEPINTEN)                                                */

    struct {
      __IO uint32_t TFEN       : 1;            /*!< [0..0] Transfer finished interrupt enable                                 */
      __IO uint32_t EPDISEN    : 1;            /*!< [1..1] Endpoint disabled interrupt enable                                 */
            uint32_t            : 1;
      __IO uint32_t STPFEN     : 1;            /*!< [3..3] SETUP phase finished interrupt enable                              */
      __IO uint32_t EPRXFOVREN : 1;            /*!< [4..4] Endpoint Rx FIFO overrun interrupt enable                          */
            uint32_t            : 1;
      __IO uint32_t BTBSTPEN   : 1;            /*!< [6..6] Back-to-back SETUP packets interrupt enable                        */
            uint32_t            : 25;
    } DOEPINTEN_b;
  } ;

  union {
    __I  uint32_t DAEPINT;                     /*!< (@ 0x00000018) device all endpoints interrupt register (DAEPINT)          */

    struct {
      __I  uint32_t IEPITB     : 4;            /*!< [3..0] Device all IN endpoint interrupt bits                              */
            uint32_t            : 12;
      __I  uint32_t OEPITB     : 4;            /*!< [19..16] Device all OUT endpoint interrupt bits                           */
            uint32_t            : 12;
    } DAEPINT_b;
  } ;

  union {
    __IO uint32_t DAEPINTEN;                   /*!< (@ 0x0000001C) Device all endpoints interrupt enable register
                                                                    (DAEPINTEN)                                                */

    struct {
      __IO uint32_t IEPIE      : 4;            /*!< [3..0] IN EP interrupt interrupt enable bits                              */
            uint32_t            : 12;
      __IO uint32_t OEPIE      : 4;            /*!< [19..16] OUT endpoint interrupt enable bits                               */
            uint32_t            : 12;
    } DAEPINTEN_b;
  } ;
  __I  uint32_t  RESERVED1[2];

  union {
    __IO uint32_t DVBUSDT;                     /*!< (@ 0x00000028) device VBUS discharge time register                        */

    struct {
      __IO uint32_t DVBUSDT    : 16;           /*!< [15..0] Device VBUS discharge time                                        */
            uint32_t            : 16;
    } DVBUSDT_b;
  } ;

  union {
    __IO uint32_t DVBUSPT;                     /*!< (@ 0x0000002C) device VBUS pulsing time register                          */

    struct {
      __IO uint32_t DVBUSPT    : 12;           /*!< [11..0] Device VBUS pulsing time                                          */
            uint32_t            : 20;
    } DVBUSPT_b;
  } ;
  __I  uint32_t  RESERVED2;

  union {
    __IO uint32_t DIEPFEINTEN;                 /*!< (@ 0x00000034) device IN endpoint FIFO empty interrupt enable
                                                                    register                                                   */

    struct {
      __IO uint32_t IEPTXFEIE  : 4;            /*!< [3..0] IN EP Tx FIFO empty interrupt enable bits                          */
            uint32_t            : 28;
    } DIEPFEINTEN_b;
  } ;
  __I  uint32_t  RESERVED3[50];

  union {
    __IO uint32_t DIEP0CTL;                    /*!< (@ 0x00000100) device IN endpoint 0 control register (DIEP0CTL)           */

    struct {
      __IO uint32_t MPL        : 2;            /*!< [1..0] Maximum packet length                                              */
            uint32_t            : 13;
      __I  uint32_t EPACT      : 1;            /*!< [15..15] endpoint active                                                  */
            uint32_t            : 1;
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __I  uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
      __IO uint32_t TXFNUM     : 4;            /*!< [25..22] TxFIFO number                                                    */
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
            uint32_t            : 2;
      __IO uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DIEP0CTL_b;
  } ;
  __I  uint32_t  RESERVED4;

  union {
    __IO uint32_t DIEP0INTF;                   /*!< (@ 0x00000108) device endpoint-0 interrupt register                       */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint finished                                                  */
            uint32_t            : 1;
      __IO uint32_t CITO       : 1;            /*!< [3..3] Control in timeout interrupt                                       */
      __IO uint32_t EPTXFUD    : 1;            /*!< [4..4] Endpoint Tx FIFO underrun                                          */
            uint32_t            : 1;
      __IO uint32_t IEPNE      : 1;            /*!< [6..6] IN endpoint NAK effective                                          */
      __I  uint32_t TXFE       : 1;            /*!< [7..7] Transmit FIFO empty                                                */
            uint32_t            : 24;
    } DIEP0INTF_b;
  } ;
  __I  uint32_t  RESERVED5;

  union {
    __IO uint32_t DIEP0LEN;                    /*!< (@ 0x00000110) device IN endpoint-0 transfer length register              */

    struct {
      __IO uint32_t TLEN       : 7;            /*!< [6..0] Transfer length                                                    */
            uint32_t            : 12;
      __IO uint32_t PCNT       : 2;            /*!< [20..19] Packet count                                                     */
            uint32_t            : 11;
    } DIEP0LEN_b;
  } ;
  __I  uint32_t  RESERVED6;

  union {
    __I  uint32_t DIEP0TFSTAT;                 /*!< (@ 0x00000118) device IN endpoint 0 transmit FIFO status register         */

    struct {
      __I  uint32_t IEPTFS     : 16;           /*!< [15..0] IN endpoint TxFIFO space remaining                                */
            uint32_t            : 16;
    } DIEP0TFSTAT_b;
  } ;
  __I  uint32_t  RESERVED7;

  union {
    __IO uint32_t DIEP1CTL;                    /*!< (@ 0x00000120) device in endpoint-1 control register                      */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] maximum packet length                                             */
            uint32_t            : 4;
      __IO uint32_t EPACT      : 1;            /*!< [15..15] Endpoint active                                                  */
      __I  uint32_t EOFRM_DPID : 1;            /*!< [16..16] EOFRM/DPID                                                       */
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
      __IO uint32_t TXFNUM     : 4;            /*!< [25..22] Tx FIFO number                                                   */
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
      __O  uint32_t SD0PID_SEVENFRM : 1;       /*!< [28..28] SD0PID/SEVNFRM                                                   */
      __O  uint32_t SD1PID_SODDFRM : 1;        /*!< [29..29] Set DATA1 PID/Set odd frame                                      */
      __IO uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DIEP1CTL_b;
  } ;
  __I  uint32_t  RESERVED8;

  union {
    __IO uint32_t DIEP1INTF;                   /*!< (@ 0x00000128) device endpoint-1 interrupt register                       */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint finished                                                  */
            uint32_t            : 1;
      __IO uint32_t CITO       : 1;            /*!< [3..3] Control in timeout interrupt                                       */
      __IO uint32_t EPTXFUD    : 1;            /*!< [4..4] Endpoint Tx FIFO underrun                                          */
            uint32_t            : 1;
      __IO uint32_t IEPNE      : 1;            /*!< [6..6] IN endpoint NAK effective                                          */
      __I  uint32_t TXFE       : 1;            /*!< [7..7] Transmit FIFO empty                                                */
            uint32_t            : 24;
    } DIEP1INTF_b;
  } ;
  __I  uint32_t  RESERVED9;

  union {
    __IO uint32_t DIEP1LEN;                    /*!< (@ 0x00000130) device IN endpoint-1 transfer length register              */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t MCPF       : 2;            /*!< [30..29] Multi packet count per frame                                     */
            uint32_t            : 1;
    } DIEP1LEN_b;
  } ;
  __I  uint32_t  RESERVED10;

  union {
    __I  uint32_t DIEP1TFSTAT;                 /*!< (@ 0x00000138) device IN endpoint 1 transmit FIFO status register         */

    struct {
      __I  uint32_t IEPTFS     : 16;           /*!< [15..0] IN endpoint TxFIFO space remaining                                */
            uint32_t            : 16;
    } DIEP1TFSTAT_b;
  } ;
  __I  uint32_t  RESERVED11;

  union {
    __IO uint32_t DIEP2CTL;                    /*!< (@ 0x00000140) device endpoint-2 control register                         */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] maximum packet length                                             */
            uint32_t            : 4;
      __IO uint32_t EPACT      : 1;            /*!< [15..15] Endpoint active                                                  */
      __I  uint32_t EOFRM_DPID : 1;            /*!< [16..16] EOFRM/DPID                                                       */
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
      __IO uint32_t TXFNUM     : 4;            /*!< [25..22] Tx FIFO number                                                   */
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
      __O  uint32_t SD0PID_SEVENFRM : 1;       /*!< [28..28] SD0PID/SEVNFRM                                                   */
      __O  uint32_t SD1PID_SODDFRM : 1;        /*!< [29..29] Set DATA1 PID/Set odd frame                                      */
      __IO uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DIEP2CTL_b;
  } ;
  __I  uint32_t  RESERVED12;

  union {
    __IO uint32_t DIEP2INTF;                   /*!< (@ 0x00000148) device endpoint-2 interrupt register                       */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint finished                                                  */
            uint32_t            : 1;
      __IO uint32_t CITO       : 1;            /*!< [3..3] Control in timeout interrupt                                       */
      __IO uint32_t EPTXFUD    : 1;            /*!< [4..4] Endpoint Tx FIFO underrun                                          */
            uint32_t            : 1;
      __IO uint32_t IEPNE      : 1;            /*!< [6..6] IN endpoint NAK effective                                          */
      __I  uint32_t TXFE       : 1;            /*!< [7..7] Transmit FIFO empty                                                */
            uint32_t            : 24;
    } DIEP2INTF_b;
  } ;
  __I  uint32_t  RESERVED13;

  union {
    __IO uint32_t DIEP2LEN;                    /*!< (@ 0x00000150) device IN endpoint-2 transfer length register              */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t MCPF       : 2;            /*!< [30..29] Multi packet count per frame                                     */
            uint32_t            : 1;
    } DIEP2LEN_b;
  } ;
  __I  uint32_t  RESERVED14;

  union {
    __I  uint32_t DIEP2TFSTAT;                 /*!< (@ 0x00000158) device IN endpoint 2 transmit FIFO status register         */

    struct {
      __I  uint32_t IEPTFS     : 16;           /*!< [15..0] IN endpoint TxFIFO space remaining                                */
            uint32_t            : 16;
    } DIEP2TFSTAT_b;
  } ;
  __I  uint32_t  RESERVED15;

  union {
    __IO uint32_t DIEP3CTL;                    /*!< (@ 0x00000160) device endpoint-3 control register                         */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] maximum packet length                                             */
            uint32_t            : 4;
      __IO uint32_t EPACT      : 1;            /*!< [15..15] Endpoint active                                                  */
      __I  uint32_t EOFRM_DPID : 1;            /*!< [16..16] EOFRM/DPID                                                       */
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
            uint32_t            : 1;
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
      __IO uint32_t TXFNUM     : 4;            /*!< [25..22] Tx FIFO number                                                   */
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
      __O  uint32_t SD0PID_SEVENFRM : 1;       /*!< [28..28] SD0PID/SEVNFRM                                                   */
      __O  uint32_t SD1PID_SODDFRM : 1;        /*!< [29..29] Set DATA1 PID/Set odd frame                                      */
      __IO uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DIEP3CTL_b;
  } ;
  __I  uint32_t  RESERVED16;

  union {
    __IO uint32_t DIEP3INTF;                   /*!< (@ 0x00000168) device endpoint-3 interrupt register                       */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint finished                                                  */
            uint32_t            : 1;
      __IO uint32_t CITO       : 1;            /*!< [3..3] Control in timeout interrupt                                       */
      __IO uint32_t EPTXFUD    : 1;            /*!< [4..4] Endpoint Tx FIFO underrun                                          */
            uint32_t            : 1;
      __IO uint32_t IEPNE      : 1;            /*!< [6..6] IN endpoint NAK effective                                          */
      __I  uint32_t TXFE       : 1;            /*!< [7..7] Transmit FIFO empty                                                */
            uint32_t            : 24;
    } DIEP3INTF_b;
  } ;
  __I  uint32_t  RESERVED17;

  union {
    __IO uint32_t DIEP3LEN;                    /*!< (@ 0x00000170) device IN endpoint-3 transfer length register              */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t MCPF       : 2;            /*!< [30..29] Multi packet count per frame                                     */
            uint32_t            : 1;
    } DIEP3LEN_b;
  } ;
  __I  uint32_t  RESERVED18;

  union {
    __I  uint32_t DIEP3TFSTAT;                 /*!< (@ 0x00000178) device IN endpoint 3 transmit FIFO status register         */

    struct {
      __I  uint32_t IEPTFS     : 16;           /*!< [15..0] IN endpoint TxFIFO space remaining                                */
            uint32_t            : 16;
    } DIEP3TFSTAT_b;
  } ;
  __I  uint32_t  RESERVED19[97];

  union {
    __IO uint32_t DOEP0CTL;                    /*!< (@ 0x00000300) device endpoint-0 control register                         */

    struct {
      __I  uint32_t MPL        : 2;            /*!< [1..0] Maximum packet length                                              */
            uint32_t            : 13;
      __I  uint32_t EPACT      : 1;            /*!< [15..15] Endpoint active                                                  */
            uint32_t            : 1;
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __I  uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
      __IO uint32_t SNOOP      : 1;            /*!< [20..20] Snoop mode                                                       */
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
            uint32_t            : 4;
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
            uint32_t            : 2;
      __I  uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DOEP0CTL_b;
  } ;
  __I  uint32_t  RESERVED20;

  union {
    __IO uint32_t DOEP0INTF;                   /*!< (@ 0x00000308) device out endpoint-0 interrupt flag  register             */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint disabled                                                  */
            uint32_t            : 1;
      __IO uint32_t STPF       : 1;            /*!< [3..3] Setup phase finished                                               */
      __IO uint32_t EPRXFOVR   : 1;            /*!< [4..4] Endpoint Rx FIFO overrun                                           */
            uint32_t            : 1;
      __IO uint32_t BTBSTP     : 1;            /*!< [6..6] Back-to-back SETUP packets                                         */
            uint32_t            : 25;
    } DOEP0INTF_b;
  } ;
  __I  uint32_t  RESERVED21;

  union {
    __IO uint32_t DOEP0LEN;                    /*!< (@ 0x00000310) device OUT endpoint-0 transfer length register             */

    struct {
      __IO uint32_t TLEN       : 7;            /*!< [6..0] Transfer length                                                    */
            uint32_t            : 12;
      __IO uint32_t PCNT       : 1;            /*!< [19..19] Packet count                                                     */
            uint32_t            : 9;
      __IO uint32_t STPCNT     : 2;            /*!< [30..29] SETUP packet count                                               */
            uint32_t            : 1;
    } DOEP0LEN_b;
  } ;
  __I  uint32_t  RESERVED22[3];

  union {
    __IO uint32_t DOEP1CTL;                    /*!< (@ 0x00000320) device endpoint-1 control register                         */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] maximum packet length                                             */
            uint32_t            : 4;
      __IO uint32_t EPACT      : 1;            /*!< [15..15] Endpoint active                                                  */
      __I  uint32_t EOFRM_DPID : 1;            /*!< [16..16] EOFRM/DPID                                                       */
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
      __IO uint32_t SNOOP      : 1;            /*!< [20..20] Snoop mode                                                       */
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
            uint32_t            : 4;
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
      __O  uint32_t SD0PID_SEVENFRM : 1;       /*!< [28..28] SD0PID/SEVENFRM                                                  */
      __O  uint32_t SD1PID_SODDFRM : 1;        /*!< [29..29] SD1PID/SODDFRM                                                   */
      __IO uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DOEP1CTL_b;
  } ;
  __I  uint32_t  RESERVED23;

  union {
    __IO uint32_t DOEP1INTF;                   /*!< (@ 0x00000328) device out endpoint-1 interrupt flag  register             */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint disabled                                                  */
            uint32_t            : 1;
      __IO uint32_t STPF       : 1;            /*!< [3..3] Setup phase finished                                               */
      __IO uint32_t EPRXFOVR   : 1;            /*!< [4..4] Endpoint Rx FIFO overrun                                           */
            uint32_t            : 1;
      __IO uint32_t BTBSTP     : 1;            /*!< [6..6] Back-to-back SETUP packets                                         */
            uint32_t            : 25;
    } DOEP1INTF_b;
  } ;
  __I  uint32_t  RESERVED24;

  union {
    __IO uint32_t DOEP1LEN;                    /*!< (@ 0x00000330) device OUT endpoint-1 transfer length register             */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t STPCNT_RXDPID : 2;         /*!< [30..29] SETUP packet count/Received data PID                             */
            uint32_t            : 1;
    } DOEP1LEN_b;
  } ;
  __I  uint32_t  RESERVED25[3];

  union {
    __IO uint32_t DOEP2CTL;                    /*!< (@ 0x00000340) device endpoint-2 control register                         */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] maximum packet length                                             */
            uint32_t            : 4;
      __IO uint32_t EPACT      : 1;            /*!< [15..15] Endpoint active                                                  */
      __I  uint32_t EOFRM_DPID : 1;            /*!< [16..16] EOFRM/DPID                                                       */
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
      __IO uint32_t SNOOP      : 1;            /*!< [20..20] Snoop mode                                                       */
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
            uint32_t            : 4;
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
      __O  uint32_t SD0PID_SEVENFRM : 1;       /*!< [28..28] SD0PID/SEVENFRM                                                  */
      __O  uint32_t SD1PID_SODDFRM : 1;        /*!< [29..29] SD1PID/SODDFRM                                                   */
      __IO uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DOEP2CTL_b;
  } ;
  __I  uint32_t  RESERVED26;

  union {
    __IO uint32_t DOEP2INTF;                   /*!< (@ 0x00000348) device out endpoint-2 interrupt flag  register             */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint disabled                                                  */
            uint32_t            : 1;
      __IO uint32_t STPF       : 1;            /*!< [3..3] Setup phase finished                                               */
      __IO uint32_t EPRXFOVR   : 1;            /*!< [4..4] Endpoint Rx FIFO overrun                                           */
            uint32_t            : 1;
      __IO uint32_t BTBSTP     : 1;            /*!< [6..6] Back-to-back SETUP packets                                         */
            uint32_t            : 25;
    } DOEP2INTF_b;
  } ;
  __I  uint32_t  RESERVED27;

  union {
    __IO uint32_t DOEP2LEN;                    /*!< (@ 0x00000350) device OUT endpoint-2 transfer length register             */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t STPCNT_RXDPID : 2;         /*!< [30..29] SETUP packet count/Received data PID                             */
            uint32_t            : 1;
    } DOEP2LEN_b;
  } ;
  __I  uint32_t  RESERVED28[3];

  union {
    __IO uint32_t DOEP3CTL;                    /*!< (@ 0x00000360) device endpoint-3 control register                         */

    struct {
      __IO uint32_t MPL        : 11;           /*!< [10..0] maximum packet length                                             */
            uint32_t            : 4;
      __IO uint32_t EPACT      : 1;            /*!< [15..15] Endpoint active                                                  */
      __I  uint32_t EOFRM_DPID : 1;            /*!< [16..16] EOFRM/DPID                                                       */
      __I  uint32_t NAKS       : 1;            /*!< [17..17] NAK status                                                       */
      __IO uint32_t EPTYPE     : 2;            /*!< [19..18] Endpoint type                                                    */
      __IO uint32_t SNOOP      : 1;            /*!< [20..20] Snoop mode                                                       */
      __IO uint32_t STALL      : 1;            /*!< [21..21] STALL handshake                                                  */
            uint32_t            : 4;
      __O  uint32_t CNAK       : 1;            /*!< [26..26] Clear NAK                                                        */
      __O  uint32_t SNAK       : 1;            /*!< [27..27] Set NAK                                                          */
      __O  uint32_t SD0PID_SEVENFRM : 1;       /*!< [28..28] SD0PID/SEVENFRM                                                  */
      __O  uint32_t SD1PID_SODDFRM : 1;        /*!< [29..29] SD1PID/SODDFRM                                                   */
      __IO uint32_t EPD        : 1;            /*!< [30..30] Endpoint disable                                                 */
      __IO uint32_t EPEN       : 1;            /*!< [31..31] Endpoint enable                                                  */
    } DOEP3CTL_b;
  } ;
  __I  uint32_t  RESERVED29;

  union {
    __IO uint32_t DOEP3INTF;                   /*!< (@ 0x00000368) device out endpoint-3 interrupt flag  register             */

    struct {
      __IO uint32_t TF         : 1;            /*!< [0..0] Transfer finished                                                  */
      __IO uint32_t EPDIS      : 1;            /*!< [1..1] Endpoint disabled                                                  */
            uint32_t            : 1;
      __IO uint32_t STPF       : 1;            /*!< [3..3] Setup phase finished                                               */
      __IO uint32_t EPRXFOVR   : 1;            /*!< [4..4] Endpoint Rx FIFO overrun                                           */
            uint32_t            : 1;
      __IO uint32_t BTBSTP     : 1;            /*!< [6..6] Back-to-back SETUP packets                                         */
            uint32_t            : 25;
    } DOEP3INTF_b;
  } ;
  __I  uint32_t  RESERVED30;

  union {
    __IO uint32_t DOEP3LEN;                    /*!< (@ 0x00000370) device OUT endpoint-3 transfer length register             */

    struct {
      __IO uint32_t TLEN       : 19;           /*!< [18..0] Transfer length                                                   */
      __IO uint32_t PCNT       : 10;           /*!< [28..19] Packet count                                                     */
      __IO uint32_t STPCNT_RXDPID : 2;         /*!< [30..29] SETUP packet count/Received data PID                             */
            uint32_t            : 1;
    } DOEP3LEN_b;
  } ;
} USBFS_DEVICE_Type;                            /*!< Size = 884 (0x374)                                                        */



/* =========================================================================================================================== */
/* ================                                       USBFS_PWRCLK                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief USB on the go full speed (USBFS_PWRCLK)
  */

typedef struct {                                /*!< (@ 0x50000E00) USBFS_PWRCLK Structure                                     */

  union {
    __IO uint32_t PWRCLKCTL;                   /*!< (@ 0x00000000) power and clock gating control register (PWRCLKCTL)        */

    struct {
      __IO uint32_t SUCLK      : 1;            /*!< [0..0] Stop the USB clock                                                 */
      __IO uint32_t SHCLK      : 1;            /*!< [1..1] Stop HCLK                                                          */
            uint32_t            : 30;
    } PWRCLKCTL_b;
  } ;
} USBFS_PWRCLK_Type;                            /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                           WWDGT                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Window watchdog timer (WWDGT)
  */

typedef struct {                                /*!< (@ 0x40002C00) WWDGT Structure                                            */

  union {
    __IO uint32_t CTL;                         /*!< (@ 0x00000000) Control register                                           */

    struct {
      __IO uint32_t CNT        : 7;            /*!< [6..0] 7-bit counter                                                      */
      __IO uint32_t WDGTEN     : 1;            /*!< [7..7] Activation bit                                                     */
            uint32_t            : 24;
    } CTL_b;
  } ;

  union {
    __IO uint32_t CFG;                         /*!< (@ 0x00000004) Configuration register                                     */

    struct {
      __IO uint32_t WIN        : 7;            /*!< [6..0] 7-bit window value                                                 */
      __IO uint32_t PSC        : 2;            /*!< [8..7] Prescaler                                                          */
      __IO uint32_t EWIE       : 1;            /*!< [9..9] Early wakeup interrupt                                             */
            uint32_t            : 22;
    } CFG_b;
  } ;

  union {
    __IO uint32_t STAT;                        /*!< (@ 0x00000008) Status register                                            */

    struct {
      __IO uint32_t EWIF       : 1;            /*!< [0..0] Early wakeup interrupt flag                                        */
            uint32_t            : 31;
    } STAT_b;
  } ;
} WWDGT_Type;                                   /*!< Size = 12 (0xc)                                                           */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

//#define ADC0_BASE                   0x40012400UL
//#define ADC1_BASE                   0x40012800UL
//#define AFIO_BASE                   0x40010000UL
//#define BKP_BASE                    0x40006C00UL
//#define CAN0_BASE                   0x40006400UL
//#define CAN1_BASE                   0x40006800UL
//#define CRC_BASE                    0x40023000UL
//#define DAC_BASE                    0x40007400UL
//#define DBG_BASE                    0xE0042000UL
//#define DMA0_BASE                   0x40020000UL
//#define DMA1_BASE                   0x40020400UL
//#define EXMC_BASE                   0xA0000000UL
//#define EXTI_BASE                   0x40010400UL
//#define FMC_BASE                    0x40022000UL
//#define FWDGT_BASE                  0x40003000UL
//#define GPIOA_BASE                  0x40010800UL
//#define GPIOB_BASE                  0x40010C00UL
//#define GPIOC_BASE                  0x40011000UL
//#define GPIOD_BASE                  0x40011400UL
//#define GPIOE_BASE                  0x40011800UL
//#define I2C0_BASE                   0x40005400UL
//#define I2C1_BASE                   0x40005800UL
//#define ECLIC_BASE                  0xD2000000UL
//#define PMU_BASE                    0x40007000UL
//#define RCU_BASE                    0x40021000UL
//#define RTC_BASE                    0x40002800UL
//#define SPI0_BASE                   0x40013000UL
//#define SPI1_BASE                   0x40003800UL
//#define SPI2_BASE                   0x40003C00UL
#define TIMER0_BASE                 0x40012C00UL
#define TIMER1_BASE                 0x40000000UL
#define TIMER2_BASE                 0x40000400UL
#define TIMER3_BASE                 0x40000800UL
#define TIMER4_BASE                 0x40000C00UL
#define TIMER5_BASE                 0x40001000UL
#define TIMER6_BASE                 0x40001400UL
#define USART0_BASE                 0x40013800UL
#define USART1_BASE                 0x40004400UL
#define USART2_BASE                 0x40004800UL
//#define UART3_BASE                  0x40004C00UL
//#define UART4_BASE                  0x40005000UL
//#define USBFS_GLOBAL_BASE           0x50000000UL
//#define USBFS_HOST_BASE             0x50000400UL
//#define USBFS_DEVICE_BASE           0x50000800UL
//#define USBFS_PWRCLK_BASE           0x50000E00UL
//#define WWDGT_BASE                  0x40002C00UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define ADC0                        ((ADC0_Type*)              ADC0_BASE)
#define ADC1                        ((ADC1_Type*)              ADC1_BASE)
#define AFIO                        ((AFIO_Type*)              AFIO_BASE)
#define BKP                         ((BKP_Type*)               BKP_BASE)
#define CAN0                        ((CAN0_Type*)              CAN0_BASE)
#define CAN1                        ((CAN0_Type*)              CAN1_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)
#define DAC                         ((DAC_Type*)               DAC_BASE)
#define DBG                         ((DBG_Type*)               DBG_BASE)
#define DMA0                        ((DMA0_Type*)              DMA0_BASE)
#define DMA1                        ((DMA1_Type*)              DMA1_BASE)
#define EXMC                        ((EXMC_Type*)              EXMC_BASE)
#define EXTI                        ((EXTI_Type*)              EXTI_BASE)
#define FMC                         ((FMC_Type*)               FMC_BASE)
#define FWDGT                       ((FWDGT_Type*)             FWDGT_BASE)
#define GPIOA                       ((GPIO_Type*)              GPIOA_BASE)
#define GPIOB                       ((GPIO_Type*)              GPIOB_BASE)
#define GPIOC                       ((GPIO_Type*)              GPIOC_BASE)
#define GPIOD                       ((GPIO_Type*)              GPIOD_BASE)
#define GPIOE                       ((GPIO_Type*)              GPIOE_BASE)
#define I2C0                        ((I2C_Type*)               I2C0_BASE)
#define I2C1                        ((I2C_Type*)               I2C1_BASE)
#define ECLIC                       ((ECLIC_Type*)             ECLIC_BASE)
#define PMU                         ((PMU_Type*)               PMU_BASE)
#define RCU                         ((RCU_Type*)               RCU_BASE)
#define RTC                         ((RTC_Type*)               RTC_BASE)
#define SPI0                        ((SPI_Type*)              SPI0_BASE)
#define SPI1                        ((SPI_Type*)              SPI1_BASE)
#define SPI2                        ((SPI_Type*)              SPI2_BASE)
#define TIMER0                      ((TIMER_Type*)            TIMER0_BASE)
#define TIMER1                      ((TIMER_Type*)            TIMER1_BASE)
#define TIMER2                      ((TIMER_Type*)            TIMER2_BASE)
#define TIMER3                      ((TIMER_Type*)            TIMER3_BASE)
#define TIMER4                      ((TIMER_Type*)            TIMER4_BASE)
#define TIMER5                      ((TIMER_Type*)            TIMER5_BASE)
#define TIMER6                      ((TIMER_Type*)            TIMER6_BASE)
#define USART0                      ((USART_Type*)             USART0_BASE)
#define USART1                      ((USART_Type*)             USART1_BASE)
#define USART2                      ((USART_Type*)             USART2_BASE)
#define UART3                       ((UART_Type*)              UART3_BASE)
#define UART4                       ((UART_Type*)              UART4_BASE)
#define USBFS_GLOBAL                ((USBFS_GLOBAL_Type*)      USBFS_GLOBAL_BASE)
#define USBFS_HOST                  ((USBFS_HOST_Type*)        USBFS_HOST_BASE)
#define USBFS_DEVICE                ((USBFS_DEVICE_Type*)      USBFS_DEVICE_BASE)
#define USBFS_PWRCLK                ((USBFS_PWRCLK_Type*)      USBFS_PWRCLK_BASE)
#define WWDGT                       ((WWDGT_Type*)             WWDGT_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           ADC0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  STAT  ========================================================== */
#define ADC0_STAT_STRC_Pos                (4UL)                     /*!< STRC (Bit 4)                                          */
#define ADC0_STAT_STRC_Msk                (0x10UL)                  /*!< STRC (Bitfield-Mask: 0x01)                            */
#define ADC0_STAT_STIC_Pos                (3UL)                     /*!< STIC (Bit 3)                                          */
#define ADC0_STAT_STIC_Msk                (0x8UL)                   /*!< STIC (Bitfield-Mask: 0x01)                            */
#define ADC0_STAT_EOIC_Pos                (2UL)                     /*!< EOIC (Bit 2)                                          */
#define ADC0_STAT_EOIC_Msk                (0x4UL)                   /*!< EOIC (Bitfield-Mask: 0x01)                            */
#define ADC0_STAT_EOC_Pos                 (1UL)                     /*!< EOC (Bit 1)                                           */
#define ADC0_STAT_EOC_Msk                 (0x2UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
#define ADC0_STAT_WDE_Pos                 (0UL)                     /*!< WDE (Bit 0)                                           */
#define ADC0_STAT_WDE_Msk                 (0x1UL)                   /*!< WDE (Bitfield-Mask: 0x01)                             */
/* =========================================================  CTL0  ========================================================== */
#define ADC0_CTL0_RWDEN_Pos               (23UL)                    /*!< RWDEN (Bit 23)                                        */
#define ADC0_CTL0_RWDEN_Msk               (0x800000UL)              /*!< RWDEN (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL0_IWDEN_Pos               (22UL)                    /*!< IWDEN (Bit 22)                                        */
#define ADC0_CTL0_IWDEN_Msk               (0x400000UL)              /*!< IWDEN (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL0_SYNCM_Pos               (16UL)                    /*!< SYNCM (Bit 16)                                        */
#define ADC0_CTL0_SYNCM_Msk               (0xf0000UL)               /*!< SYNCM (Bitfield-Mask: 0x0f)                           */
#define ADC0_CTL0_DISNUM_Pos              (13UL)                    /*!< DISNUM (Bit 13)                                       */
#define ADC0_CTL0_DISNUM_Msk              (0xe000UL)                /*!< DISNUM (Bitfield-Mask: 0x07)                          */
#define ADC0_CTL0_DISIC_Pos               (12UL)                    /*!< DISIC (Bit 12)                                        */
#define ADC0_CTL0_DISIC_Msk               (0x1000UL)                /*!< DISIC (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL0_DISRC_Pos               (11UL)                    /*!< DISRC (Bit 11)                                        */
#define ADC0_CTL0_DISRC_Msk               (0x800UL)                 /*!< DISRC (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL0_ICA_Pos                 (10UL)                    /*!< ICA (Bit 10)                                          */
#define ADC0_CTL0_ICA_Msk                 (0x400UL)                 /*!< ICA (Bitfield-Mask: 0x01)                             */
#define ADC0_CTL0_WDSC_Pos                (9UL)                     /*!< WDSC (Bit 9)                                          */
#define ADC0_CTL0_WDSC_Msk                (0x200UL)                 /*!< WDSC (Bitfield-Mask: 0x01)                            */
#define ADC0_CTL0_SM_Pos                  (8UL)                     /*!< SM (Bit 8)                                            */
#define ADC0_CTL0_SM_Msk                  (0x100UL)                 /*!< SM (Bitfield-Mask: 0x01)                              */
#define ADC0_CTL0_EOICIE_Pos              (7UL)                     /*!< EOICIE (Bit 7)                                        */
#define ADC0_CTL0_EOICIE_Msk              (0x80UL)                  /*!< EOICIE (Bitfield-Mask: 0x01)                          */
#define ADC0_CTL0_WDEIE_Pos               (6UL)                     /*!< WDEIE (Bit 6)                                         */
#define ADC0_CTL0_WDEIE_Msk               (0x40UL)                  /*!< WDEIE (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL0_EOCIE_Pos               (5UL)                     /*!< EOCIE (Bit 5)                                         */
#define ADC0_CTL0_EOCIE_Msk               (0x20UL)                  /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL0_WDCHSEL_Pos             (0UL)                     /*!< WDCHSEL (Bit 0)                                       */
#define ADC0_CTL0_WDCHSEL_Msk             (0x1fUL)                  /*!< WDCHSEL (Bitfield-Mask: 0x1f)                         */
/* =========================================================  CTL1  ========================================================== */
#define ADC0_CTL1_TSVREN_Pos              (23UL)                    /*!< TSVREN (Bit 23)                                       */
#define ADC0_CTL1_TSVREN_Msk              (0x800000UL)              /*!< TSVREN (Bitfield-Mask: 0x01)                          */
#define ADC0_CTL1_SWRCST_Pos              (22UL)                    /*!< SWRCST (Bit 22)                                       */
#define ADC0_CTL1_SWRCST_Msk              (0x400000UL)              /*!< SWRCST (Bitfield-Mask: 0x01)                          */
#define ADC0_CTL1_SWICST_Pos              (21UL)                    /*!< SWICST (Bit 21)                                       */
#define ADC0_CTL1_SWICST_Msk              (0x200000UL)              /*!< SWICST (Bitfield-Mask: 0x01)                          */
#define ADC0_CTL1_ETERC_Pos               (20UL)                    /*!< ETERC (Bit 20)                                        */
#define ADC0_CTL1_ETERC_Msk               (0x100000UL)              /*!< ETERC (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL1_ETSRC_Pos               (17UL)                    /*!< ETSRC (Bit 17)                                        */
#define ADC0_CTL1_ETSRC_Msk               (0xe0000UL)               /*!< ETSRC (Bitfield-Mask: 0x07)                           */
#define ADC0_CTL1_ETEIC_Pos               (15UL)                    /*!< ETEIC (Bit 15)                                        */
#define ADC0_CTL1_ETEIC_Msk               (0x8000UL)                /*!< ETEIC (Bitfield-Mask: 0x01)                           */
#define ADC0_CTL1_ETSIC_Pos               (12UL)                    /*!< ETSIC (Bit 12)                                        */
#define ADC0_CTL1_ETSIC_Msk               (0x7000UL)                /*!< ETSIC (Bitfield-Mask: 0x07)                           */
#define ADC0_CTL1_DAL_Pos                 (11UL)                    /*!< DAL (Bit 11)                                          */
#define ADC0_CTL1_DAL_Msk                 (0x800UL)                 /*!< DAL (Bitfield-Mask: 0x01)                             */
#define ADC0_CTL1_DMA_Pos                 (8UL)                     /*!< DMA (Bit 8)                                           */
#define ADC0_CTL1_DMA_Msk                 (0x100UL)                 /*!< DMA (Bitfield-Mask: 0x01)                             */
#define ADC0_CTL1_RSTCLB_Pos              (3UL)                     /*!< RSTCLB (Bit 3)                                        */
#define ADC0_CTL1_RSTCLB_Msk              (0x8UL)                   /*!< RSTCLB (Bitfield-Mask: 0x01)                          */
#define ADC0_CTL1_CLB_Pos                 (2UL)                     /*!< CLB (Bit 2)                                           */
#define ADC0_CTL1_CLB_Msk                 (0x4UL)                   /*!< CLB (Bitfield-Mask: 0x01)                             */
#define ADC0_CTL1_CTN_Pos                 (1UL)                     /*!< CTN (Bit 1)                                           */
#define ADC0_CTL1_CTN_Msk                 (0x2UL)                   /*!< CTN (Bitfield-Mask: 0x01)                             */
#define ADC0_CTL1_ADCON_Pos               (0UL)                     /*!< ADCON (Bit 0)                                         */
#define ADC0_CTL1_ADCON_Msk               (0x1UL)                   /*!< ADCON (Bitfield-Mask: 0x01)                           */
/* ========================================================  SAMPT0  ========================================================= */
#define ADC0_SAMPT0_SPT10_Pos             (0UL)                     /*!< SPT10 (Bit 0)                                         */
#define ADC0_SAMPT0_SPT10_Msk             (0x7UL)                   /*!< SPT10 (Bitfield-Mask: 0x07)                           */
#define ADC0_SAMPT0_SPT11_Pos             (3UL)                     /*!< SPT11 (Bit 3)                                         */
#define ADC0_SAMPT0_SPT11_Msk             (0x38UL)                  /*!< SPT11 (Bitfield-Mask: 0x07)                           */
#define ADC0_SAMPT0_SPT12_Pos             (6UL)                     /*!< SPT12 (Bit 6)                                         */
#define ADC0_SAMPT0_SPT12_Msk             (0x1c0UL)                 /*!< SPT12 (Bitfield-Mask: 0x07)                           */
#define ADC0_SAMPT0_SPT13_Pos             (9UL)                     /*!< SPT13 (Bit 9)                                         */
#define ADC0_SAMPT0_SPT13_Msk             (0xe00UL)                 /*!< SPT13 (Bitfield-Mask: 0x07)                           */
#define ADC0_SAMPT0_SPT14_Pos             (12UL)                    /*!< SPT14 (Bit 12)                                        */
#define ADC0_SAMPT0_SPT14_Msk             (0x7000UL)                /*!< SPT14 (Bitfield-Mask: 0x07)                           */
#define ADC0_SAMPT0_SPT15_Pos             (15UL)                    /*!< SPT15 (Bit 15)                                        */
#define ADC0_SAMPT0_SPT15_Msk             (0x38000UL)               /*!< SPT15 (Bitfield-Mask: 0x07)                           */
#define ADC0_SAMPT0_SPT16_Pos             (18UL)                    /*!< SPT16 (Bit 18)                                        */
#define ADC0_SAMPT0_SPT16_Msk             (0x1c0000UL)              /*!< SPT16 (Bitfield-Mask: 0x07)                           */
#define ADC0_SAMPT0_SPT17_Pos             (21UL)                    /*!< SPT17 (Bit 21)                                        */
#define ADC0_SAMPT0_SPT17_Msk             (0xe00000UL)              /*!< SPT17 (Bitfield-Mask: 0x07)                           */
/* ========================================================  SAMPT1  ========================================================= */
#define ADC0_SAMPT1_SPT0_Pos              (0UL)                     /*!< SPT0 (Bit 0)                                          */
#define ADC0_SAMPT1_SPT0_Msk              (0x7UL)                   /*!< SPT0 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT1_Pos              (3UL)                     /*!< SPT1 (Bit 3)                                          */
#define ADC0_SAMPT1_SPT1_Msk              (0x38UL)                  /*!< SPT1 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT2_Pos              (6UL)                     /*!< SPT2 (Bit 6)                                          */
#define ADC0_SAMPT1_SPT2_Msk              (0x1c0UL)                 /*!< SPT2 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT3_Pos              (9UL)                     /*!< SPT3 (Bit 9)                                          */
#define ADC0_SAMPT1_SPT3_Msk              (0xe00UL)                 /*!< SPT3 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT4_Pos              (12UL)                    /*!< SPT4 (Bit 12)                                         */
#define ADC0_SAMPT1_SPT4_Msk              (0x7000UL)                /*!< SPT4 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT5_Pos              (15UL)                    /*!< SPT5 (Bit 15)                                         */
#define ADC0_SAMPT1_SPT5_Msk              (0x38000UL)               /*!< SPT5 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT6_Pos              (18UL)                    /*!< SPT6 (Bit 18)                                         */
#define ADC0_SAMPT1_SPT6_Msk              (0x1c0000UL)              /*!< SPT6 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT7_Pos              (21UL)                    /*!< SPT7 (Bit 21)                                         */
#define ADC0_SAMPT1_SPT7_Msk              (0xe00000UL)              /*!< SPT7 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT8_Pos              (24UL)                    /*!< SPT8 (Bit 24)                                         */
#define ADC0_SAMPT1_SPT8_Msk              (0x7000000UL)             /*!< SPT8 (Bitfield-Mask: 0x07)                            */
#define ADC0_SAMPT1_SPT9_Pos              (27UL)                    /*!< SPT9 (Bit 27)                                         */
#define ADC0_SAMPT1_SPT9_Msk              (0x38000000UL)            /*!< SPT9 (Bitfield-Mask: 0x07)                            */
/* =========================================================  IOFF0  ========================================================= */
#define ADC0_IOFF0_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC0_IOFF0_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  IOFF1  ========================================================= */
#define ADC0_IOFF1_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC0_IOFF1_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  IOFF2  ========================================================= */
#define ADC0_IOFF2_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC0_IOFF2_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  IOFF3  ========================================================= */
#define ADC0_IOFF3_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC0_IOFF3_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  WDHT  ========================================================== */
#define ADC0_WDHT_WDHT_Pos                (0UL)                     /*!< WDHT (Bit 0)                                          */
#define ADC0_WDHT_WDHT_Msk                (0xfffUL)                 /*!< WDHT (Bitfield-Mask: 0xfff)                           */
/* =========================================================  WDLT  ========================================================== */
#define ADC0_WDLT_WDLT_Pos                (0UL)                     /*!< WDLT (Bit 0)                                          */
#define ADC0_WDLT_WDLT_Msk                (0xfffUL)                 /*!< WDLT (Bitfield-Mask: 0xfff)                           */
/* =========================================================  RSQ0  ========================================================== */
#define ADC0_RSQ0_RL_Pos                  (20UL)                    /*!< RL (Bit 20)                                           */
#define ADC0_RSQ0_RL_Msk                  (0xf00000UL)              /*!< RL (Bitfield-Mask: 0x0f)                              */
#define ADC0_RSQ0_RSQ15_Pos               (15UL)                    /*!< RSQ15 (Bit 15)                                        */
#define ADC0_RSQ0_RSQ15_Msk               (0xf8000UL)               /*!< RSQ15 (Bitfield-Mask: 0x1f)                           */
#define ADC0_RSQ0_RSQ14_Pos               (10UL)                    /*!< RSQ14 (Bit 10)                                        */
#define ADC0_RSQ0_RSQ14_Msk               (0x7c00UL)                /*!< RSQ14 (Bitfield-Mask: 0x1f)                           */
#define ADC0_RSQ0_RSQ13_Pos               (5UL)                     /*!< RSQ13 (Bit 5)                                         */
#define ADC0_RSQ0_RSQ13_Msk               (0x3e0UL)                 /*!< RSQ13 (Bitfield-Mask: 0x1f)                           */
#define ADC0_RSQ0_RSQ12_Pos               (0UL)                     /*!< RSQ12 (Bit 0)                                         */
#define ADC0_RSQ0_RSQ12_Msk               (0x1fUL)                  /*!< RSQ12 (Bitfield-Mask: 0x1f)                           */
/* =========================================================  RSQ1  ========================================================== */
#define ADC0_RSQ1_RSQ11_Pos               (25UL)                    /*!< RSQ11 (Bit 25)                                        */
#define ADC0_RSQ1_RSQ11_Msk               (0x3e000000UL)            /*!< RSQ11 (Bitfield-Mask: 0x1f)                           */
#define ADC0_RSQ1_RSQ10_Pos               (20UL)                    /*!< RSQ10 (Bit 20)                                        */
#define ADC0_RSQ1_RSQ10_Msk               (0x1f00000UL)             /*!< RSQ10 (Bitfield-Mask: 0x1f)                           */
#define ADC0_RSQ1_RSQ9_Pos                (15UL)                    /*!< RSQ9 (Bit 15)                                         */
#define ADC0_RSQ1_RSQ9_Msk                (0xf8000UL)               /*!< RSQ9 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ1_RSQ8_Pos                (10UL)                    /*!< RSQ8 (Bit 10)                                         */
#define ADC0_RSQ1_RSQ8_Msk                (0x7c00UL)                /*!< RSQ8 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ1_RSQ7_Pos                (5UL)                     /*!< RSQ7 (Bit 5)                                          */
#define ADC0_RSQ1_RSQ7_Msk                (0x3e0UL)                 /*!< RSQ7 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ1_RSQ6_Pos                (0UL)                     /*!< RSQ6 (Bit 0)                                          */
#define ADC0_RSQ1_RSQ6_Msk                (0x1fUL)                  /*!< RSQ6 (Bitfield-Mask: 0x1f)                            */
/* =========================================================  RSQ2  ========================================================== */
#define ADC0_RSQ2_RSQ5_Pos                (25UL)                    /*!< RSQ5 (Bit 25)                                         */
#define ADC0_RSQ2_RSQ5_Msk                (0x3e000000UL)            /*!< RSQ5 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ2_RSQ4_Pos                (20UL)                    /*!< RSQ4 (Bit 20)                                         */
#define ADC0_RSQ2_RSQ4_Msk                (0x1f00000UL)             /*!< RSQ4 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ2_RSQ3_Pos                (15UL)                    /*!< RSQ3 (Bit 15)                                         */
#define ADC0_RSQ2_RSQ3_Msk                (0xf8000UL)               /*!< RSQ3 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ2_RSQ2_Pos                (10UL)                    /*!< RSQ2 (Bit 10)                                         */
#define ADC0_RSQ2_RSQ2_Msk                (0x7c00UL)                /*!< RSQ2 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ2_RSQ1_Pos                (5UL)                     /*!< RSQ1 (Bit 5)                                          */
#define ADC0_RSQ2_RSQ1_Msk                (0x3e0UL)                 /*!< RSQ1 (Bitfield-Mask: 0x1f)                            */
#define ADC0_RSQ2_RSQ0_Pos                (0UL)                     /*!< RSQ0 (Bit 0)                                          */
#define ADC0_RSQ2_RSQ0_Msk                (0x1fUL)                  /*!< RSQ0 (Bitfield-Mask: 0x1f)                            */
/* ==========================================================  ISQ  ========================================================== */
#define ADC0_ISQ_IL_Pos                   (20UL)                    /*!< IL (Bit 20)                                           */
#define ADC0_ISQ_IL_Msk                   (0x300000UL)              /*!< IL (Bitfield-Mask: 0x03)                              */
#define ADC0_ISQ_ISQ3_Pos                 (15UL)                    /*!< ISQ3 (Bit 15)                                         */
#define ADC0_ISQ_ISQ3_Msk                 (0xf8000UL)               /*!< ISQ3 (Bitfield-Mask: 0x1f)                            */
#define ADC0_ISQ_ISQ2_Pos                 (10UL)                    /*!< ISQ2 (Bit 10)                                         */
#define ADC0_ISQ_ISQ2_Msk                 (0x7c00UL)                /*!< ISQ2 (Bitfield-Mask: 0x1f)                            */
#define ADC0_ISQ_ISQ1_Pos                 (5UL)                     /*!< ISQ1 (Bit 5)                                          */
#define ADC0_ISQ_ISQ1_Msk                 (0x3e0UL)                 /*!< ISQ1 (Bitfield-Mask: 0x1f)                            */
#define ADC0_ISQ_ISQ0_Pos                 (0UL)                     /*!< ISQ0 (Bit 0)                                          */
#define ADC0_ISQ_ISQ0_Msk                 (0x1fUL)                  /*!< ISQ0 (Bitfield-Mask: 0x1f)                            */
/* ========================================================  IDATA0  ========================================================= */
#define ADC0_IDATA0_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC0_IDATA0_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* ========================================================  IDATA1  ========================================================= */
#define ADC0_IDATA1_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC0_IDATA1_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* ========================================================  IDATA2  ========================================================= */
#define ADC0_IDATA2_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC0_IDATA2_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* ========================================================  IDATA3  ========================================================= */
#define ADC0_IDATA3_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC0_IDATA3_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* =========================================================  RDATA  ========================================================= */
#define ADC0_RDATA_ADC1RDTR_Pos           (16UL)                    /*!< ADC1RDTR (Bit 16)                                     */
#define ADC0_RDATA_ADC1RDTR_Msk           (0xffff0000UL)            /*!< ADC1RDTR (Bitfield-Mask: 0xffff)                      */
#define ADC0_RDATA_RDATA_Pos              (0UL)                     /*!< RDATA (Bit 0)                                         */
#define ADC0_RDATA_RDATA_Msk              (0xffffUL)                /*!< RDATA (Bitfield-Mask: 0xffff)                         */
/* =======================================================  OVSAMPCTL  ======================================================= */
#define ADC0_OVSAMPCTL_DRES_Pos           (12UL)                    /*!< DRES (Bit 12)                                         */
#define ADC0_OVSAMPCTL_DRES_Msk           (0x3000UL)                /*!< DRES (Bitfield-Mask: 0x03)                            */
#define ADC0_OVSAMPCTL_TOVS_Pos           (9UL)                     /*!< TOVS (Bit 9)                                          */
#define ADC0_OVSAMPCTL_TOVS_Msk           (0x200UL)                 /*!< TOVS (Bitfield-Mask: 0x01)                            */
#define ADC0_OVSAMPCTL_OVSS_Pos           (5UL)                     /*!< OVSS (Bit 5)                                          */
#define ADC0_OVSAMPCTL_OVSS_Msk           (0x1e0UL)                 /*!< OVSS (Bitfield-Mask: 0x0f)                            */
#define ADC0_OVSAMPCTL_OVSR_Pos           (2UL)                     /*!< OVSR (Bit 2)                                          */
#define ADC0_OVSAMPCTL_OVSR_Msk           (0x1cUL)                  /*!< OVSR (Bitfield-Mask: 0x07)                            */
#define ADC0_OVSAMPCTL_OVSEN_Pos          (0UL)                     /*!< OVSEN (Bit 0)                                         */
#define ADC0_OVSAMPCTL_OVSEN_Msk          (0x1UL)                   /*!< OVSEN (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                           ADC1                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  STAT  ========================================================== */
#define ADC1_STAT_STRC_Pos                (4UL)                     /*!< STRC (Bit 4)                                          */
#define ADC1_STAT_STRC_Msk                (0x10UL)                  /*!< STRC (Bitfield-Mask: 0x01)                            */
#define ADC1_STAT_STIC_Pos                (3UL)                     /*!< STIC (Bit 3)                                          */
#define ADC1_STAT_STIC_Msk                (0x8UL)                   /*!< STIC (Bitfield-Mask: 0x01)                            */
#define ADC1_STAT_EOIC_Pos                (2UL)                     /*!< EOIC (Bit 2)                                          */
#define ADC1_STAT_EOIC_Msk                (0x4UL)                   /*!< EOIC (Bitfield-Mask: 0x01)                            */
#define ADC1_STAT_EOC_Pos                 (1UL)                     /*!< EOC (Bit 1)                                           */
#define ADC1_STAT_EOC_Msk                 (0x2UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
#define ADC1_STAT_WDE_Pos                 (0UL)                     /*!< WDE (Bit 0)                                           */
#define ADC1_STAT_WDE_Msk                 (0x1UL)                   /*!< WDE (Bitfield-Mask: 0x01)                             */
/* =========================================================  CTL0  ========================================================== */
#define ADC1_CTL0_RWDEN_Pos               (23UL)                    /*!< RWDEN (Bit 23)                                        */
#define ADC1_CTL0_RWDEN_Msk               (0x800000UL)              /*!< RWDEN (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL0_IWDEN_Pos               (22UL)                    /*!< IWDEN (Bit 22)                                        */
#define ADC1_CTL0_IWDEN_Msk               (0x400000UL)              /*!< IWDEN (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL0_DISNUM_Pos              (13UL)                    /*!< DISNUM (Bit 13)                                       */
#define ADC1_CTL0_DISNUM_Msk              (0xe000UL)                /*!< DISNUM (Bitfield-Mask: 0x07)                          */
#define ADC1_CTL0_DISIC_Pos               (12UL)                    /*!< DISIC (Bit 12)                                        */
#define ADC1_CTL0_DISIC_Msk               (0x1000UL)                /*!< DISIC (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL0_DISRC_Pos               (11UL)                    /*!< DISRC (Bit 11)                                        */
#define ADC1_CTL0_DISRC_Msk               (0x800UL)                 /*!< DISRC (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL0_ICA_Pos                 (10UL)                    /*!< ICA (Bit 10)                                          */
#define ADC1_CTL0_ICA_Msk                 (0x400UL)                 /*!< ICA (Bitfield-Mask: 0x01)                             */
#define ADC1_CTL0_WDSC_Pos                (9UL)                     /*!< WDSC (Bit 9)                                          */
#define ADC1_CTL0_WDSC_Msk                (0x200UL)                 /*!< WDSC (Bitfield-Mask: 0x01)                            */
#define ADC1_CTL0_SM_Pos                  (8UL)                     /*!< SM (Bit 8)                                            */
#define ADC1_CTL0_SM_Msk                  (0x100UL)                 /*!< SM (Bitfield-Mask: 0x01)                              */
#define ADC1_CTL0_EOICIE_Pos              (7UL)                     /*!< EOICIE (Bit 7)                                        */
#define ADC1_CTL0_EOICIE_Msk              (0x80UL)                  /*!< EOICIE (Bitfield-Mask: 0x01)                          */
#define ADC1_CTL0_WDEIE_Pos               (6UL)                     /*!< WDEIE (Bit 6)                                         */
#define ADC1_CTL0_WDEIE_Msk               (0x40UL)                  /*!< WDEIE (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL0_EOCIE_Pos               (5UL)                     /*!< EOCIE (Bit 5)                                         */
#define ADC1_CTL0_EOCIE_Msk               (0x20UL)                  /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL0_WDCHSEL_Pos             (0UL)                     /*!< WDCHSEL (Bit 0)                                       */
#define ADC1_CTL0_WDCHSEL_Msk             (0x1fUL)                  /*!< WDCHSEL (Bitfield-Mask: 0x1f)                         */
/* =========================================================  CTL1  ========================================================== */
#define ADC1_CTL1_SWRCST_Pos              (22UL)                    /*!< SWRCST (Bit 22)                                       */
#define ADC1_CTL1_SWRCST_Msk              (0x400000UL)              /*!< SWRCST (Bitfield-Mask: 0x01)                          */
#define ADC1_CTL1_SWICST_Pos              (21UL)                    /*!< SWICST (Bit 21)                                       */
#define ADC1_CTL1_SWICST_Msk              (0x200000UL)              /*!< SWICST (Bitfield-Mask: 0x01)                          */
#define ADC1_CTL1_ETERC_Pos               (20UL)                    /*!< ETERC (Bit 20)                                        */
#define ADC1_CTL1_ETERC_Msk               (0x100000UL)              /*!< ETERC (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL1_ETSRC_Pos               (17UL)                    /*!< ETSRC (Bit 17)                                        */
#define ADC1_CTL1_ETSRC_Msk               (0xe0000UL)               /*!< ETSRC (Bitfield-Mask: 0x07)                           */
#define ADC1_CTL1_ETEIC_Pos               (15UL)                    /*!< ETEIC (Bit 15)                                        */
#define ADC1_CTL1_ETEIC_Msk               (0x8000UL)                /*!< ETEIC (Bitfield-Mask: 0x01)                           */
#define ADC1_CTL1_ETSIC_Pos               (12UL)                    /*!< ETSIC (Bit 12)                                        */
#define ADC1_CTL1_ETSIC_Msk               (0x7000UL)                /*!< ETSIC (Bitfield-Mask: 0x07)                           */
#define ADC1_CTL1_DAL_Pos                 (11UL)                    /*!< DAL (Bit 11)                                          */
#define ADC1_CTL1_DAL_Msk                 (0x800UL)                 /*!< DAL (Bitfield-Mask: 0x01)                             */
#define ADC1_CTL1_DMA_Pos                 (8UL)                     /*!< DMA (Bit 8)                                           */
#define ADC1_CTL1_DMA_Msk                 (0x100UL)                 /*!< DMA (Bitfield-Mask: 0x01)                             */
#define ADC1_CTL1_RSTCLB_Pos              (3UL)                     /*!< RSTCLB (Bit 3)                                        */
#define ADC1_CTL1_RSTCLB_Msk              (0x8UL)                   /*!< RSTCLB (Bitfield-Mask: 0x01)                          */
#define ADC1_CTL1_CLB_Pos                 (2UL)                     /*!< CLB (Bit 2)                                           */
#define ADC1_CTL1_CLB_Msk                 (0x4UL)                   /*!< CLB (Bitfield-Mask: 0x01)                             */
#define ADC1_CTL1_CTN_Pos                 (1UL)                     /*!< CTN (Bit 1)                                           */
#define ADC1_CTL1_CTN_Msk                 (0x2UL)                   /*!< CTN (Bitfield-Mask: 0x01)                             */
#define ADC1_CTL1_ADCON_Pos               (0UL)                     /*!< ADCON (Bit 0)                                         */
#define ADC1_CTL1_ADCON_Msk               (0x1UL)                   /*!< ADCON (Bitfield-Mask: 0x01)                           */
/* ========================================================  SAMPT0  ========================================================= */
#define ADC1_SAMPT0_SPT10_Pos             (0UL)                     /*!< SPT10 (Bit 0)                                         */
#define ADC1_SAMPT0_SPT10_Msk             (0x7UL)                   /*!< SPT10 (Bitfield-Mask: 0x07)                           */
#define ADC1_SAMPT0_SPT11_Pos             (3UL)                     /*!< SPT11 (Bit 3)                                         */
#define ADC1_SAMPT0_SPT11_Msk             (0x38UL)                  /*!< SPT11 (Bitfield-Mask: 0x07)                           */
#define ADC1_SAMPT0_SPT12_Pos             (6UL)                     /*!< SPT12 (Bit 6)                                         */
#define ADC1_SAMPT0_SPT12_Msk             (0x1c0UL)                 /*!< SPT12 (Bitfield-Mask: 0x07)                           */
#define ADC1_SAMPT0_SPT13_Pos             (9UL)                     /*!< SPT13 (Bit 9)                                         */
#define ADC1_SAMPT0_SPT13_Msk             (0xe00UL)                 /*!< SPT13 (Bitfield-Mask: 0x07)                           */
#define ADC1_SAMPT0_SPT14_Pos             (12UL)                    /*!< SPT14 (Bit 12)                                        */
#define ADC1_SAMPT0_SPT14_Msk             (0x7000UL)                /*!< SPT14 (Bitfield-Mask: 0x07)                           */
#define ADC1_SAMPT0_SPT15_Pos             (15UL)                    /*!< SPT15 (Bit 15)                                        */
#define ADC1_SAMPT0_SPT15_Msk             (0x38000UL)               /*!< SPT15 (Bitfield-Mask: 0x07)                           */
#define ADC1_SAMPT0_SPT16_Pos             (18UL)                    /*!< SPT16 (Bit 18)                                        */
#define ADC1_SAMPT0_SPT16_Msk             (0x1c0000UL)              /*!< SPT16 (Bitfield-Mask: 0x07)                           */
#define ADC1_SAMPT0_SPT17_Pos             (21UL)                    /*!< SPT17 (Bit 21)                                        */
#define ADC1_SAMPT0_SPT17_Msk             (0xe00000UL)              /*!< SPT17 (Bitfield-Mask: 0x07)                           */
/* ========================================================  SAMPT1  ========================================================= */
#define ADC1_SAMPT1_SPT0_Pos              (0UL)                     /*!< SPT0 (Bit 0)                                          */
#define ADC1_SAMPT1_SPT0_Msk              (0x7UL)                   /*!< SPT0 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT1_Pos              (3UL)                     /*!< SPT1 (Bit 3)                                          */
#define ADC1_SAMPT1_SPT1_Msk              (0x38UL)                  /*!< SPT1 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT2_Pos              (6UL)                     /*!< SPT2 (Bit 6)                                          */
#define ADC1_SAMPT1_SPT2_Msk              (0x1c0UL)                 /*!< SPT2 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT3_Pos              (9UL)                     /*!< SPT3 (Bit 9)                                          */
#define ADC1_SAMPT1_SPT3_Msk              (0xe00UL)                 /*!< SPT3 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT4_Pos              (12UL)                    /*!< SPT4 (Bit 12)                                         */
#define ADC1_SAMPT1_SPT4_Msk              (0x7000UL)                /*!< SPT4 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT5_Pos              (15UL)                    /*!< SPT5 (Bit 15)                                         */
#define ADC1_SAMPT1_SPT5_Msk              (0x38000UL)               /*!< SPT5 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT6_Pos              (18UL)                    /*!< SPT6 (Bit 18)                                         */
#define ADC1_SAMPT1_SPT6_Msk              (0x1c0000UL)              /*!< SPT6 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT7_Pos              (21UL)                    /*!< SPT7 (Bit 21)                                         */
#define ADC1_SAMPT1_SPT7_Msk              (0xe00000UL)              /*!< SPT7 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT8_Pos              (24UL)                    /*!< SPT8 (Bit 24)                                         */
#define ADC1_SAMPT1_SPT8_Msk              (0x7000000UL)             /*!< SPT8 (Bitfield-Mask: 0x07)                            */
#define ADC1_SAMPT1_SPT9_Pos              (27UL)                    /*!< SPT9 (Bit 27)                                         */
#define ADC1_SAMPT1_SPT9_Msk              (0x38000000UL)            /*!< SPT9 (Bitfield-Mask: 0x07)                            */
/* =========================================================  IOFF0  ========================================================= */
#define ADC1_IOFF0_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC1_IOFF0_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  IOFF1  ========================================================= */
#define ADC1_IOFF1_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC1_IOFF1_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  IOFF2  ========================================================= */
#define ADC1_IOFF2_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC1_IOFF2_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  IOFF3  ========================================================= */
#define ADC1_IOFF3_IOFF_Pos               (0UL)                     /*!< IOFF (Bit 0)                                          */
#define ADC1_IOFF3_IOFF_Msk               (0xfffUL)                 /*!< IOFF (Bitfield-Mask: 0xfff)                           */
/* =========================================================  WDHT  ========================================================== */
#define ADC1_WDHT_WDHT_Pos                (0UL)                     /*!< WDHT (Bit 0)                                          */
#define ADC1_WDHT_WDHT_Msk                (0xfffUL)                 /*!< WDHT (Bitfield-Mask: 0xfff)                           */
/* =========================================================  WDLT  ========================================================== */
#define ADC1_WDLT_WDLT_Pos                (0UL)                     /*!< WDLT (Bit 0)                                          */
#define ADC1_WDLT_WDLT_Msk                (0xfffUL)                 /*!< WDLT (Bitfield-Mask: 0xfff)                           */
/* =========================================================  RSQ0  ========================================================== */
#define ADC1_RSQ0_RL_Pos                  (20UL)                    /*!< RL (Bit 20)                                           */
#define ADC1_RSQ0_RL_Msk                  (0xf00000UL)              /*!< RL (Bitfield-Mask: 0x0f)                              */
#define ADC1_RSQ0_RSQ15_Pos               (15UL)                    /*!< RSQ15 (Bit 15)                                        */
#define ADC1_RSQ0_RSQ15_Msk               (0xf8000UL)               /*!< RSQ15 (Bitfield-Mask: 0x1f)                           */
#define ADC1_RSQ0_RSQ14_Pos               (10UL)                    /*!< RSQ14 (Bit 10)                                        */
#define ADC1_RSQ0_RSQ14_Msk               (0x7c00UL)                /*!< RSQ14 (Bitfield-Mask: 0x1f)                           */
#define ADC1_RSQ0_RSQ13_Pos               (5UL)                     /*!< RSQ13 (Bit 5)                                         */
#define ADC1_RSQ0_RSQ13_Msk               (0x3e0UL)                 /*!< RSQ13 (Bitfield-Mask: 0x1f)                           */
#define ADC1_RSQ0_RSQ12_Pos               (0UL)                     /*!< RSQ12 (Bit 0)                                         */
#define ADC1_RSQ0_RSQ12_Msk               (0x1fUL)                  /*!< RSQ12 (Bitfield-Mask: 0x1f)                           */
/* =========================================================  RSQ1  ========================================================== */
#define ADC1_RSQ1_RSQ11_Pos               (25UL)                    /*!< RSQ11 (Bit 25)                                        */
#define ADC1_RSQ1_RSQ11_Msk               (0x3e000000UL)            /*!< RSQ11 (Bitfield-Mask: 0x1f)                           */
#define ADC1_RSQ1_RSQ10_Pos               (20UL)                    /*!< RSQ10 (Bit 20)                                        */
#define ADC1_RSQ1_RSQ10_Msk               (0x1f00000UL)             /*!< RSQ10 (Bitfield-Mask: 0x1f)                           */
#define ADC1_RSQ1_RSQ9_Pos                (15UL)                    /*!< RSQ9 (Bit 15)                                         */
#define ADC1_RSQ1_RSQ9_Msk                (0xf8000UL)               /*!< RSQ9 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ1_RSQ8_Pos                (10UL)                    /*!< RSQ8 (Bit 10)                                         */
#define ADC1_RSQ1_RSQ8_Msk                (0x7c00UL)                /*!< RSQ8 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ1_RSQ7_Pos                (5UL)                     /*!< RSQ7 (Bit 5)                                          */
#define ADC1_RSQ1_RSQ7_Msk                (0x3e0UL)                 /*!< RSQ7 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ1_RSQ6_Pos                (0UL)                     /*!< RSQ6 (Bit 0)                                          */
#define ADC1_RSQ1_RSQ6_Msk                (0x1fUL)                  /*!< RSQ6 (Bitfield-Mask: 0x1f)                            */
/* =========================================================  RSQ2  ========================================================== */
#define ADC1_RSQ2_RSQ5_Pos                (25UL)                    /*!< RSQ5 (Bit 25)                                         */
#define ADC1_RSQ2_RSQ5_Msk                (0x3e000000UL)            /*!< RSQ5 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ2_RSQ4_Pos                (20UL)                    /*!< RSQ4 (Bit 20)                                         */
#define ADC1_RSQ2_RSQ4_Msk                (0x1f00000UL)             /*!< RSQ4 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ2_RSQ3_Pos                (15UL)                    /*!< RSQ3 (Bit 15)                                         */
#define ADC1_RSQ2_RSQ3_Msk                (0xf8000UL)               /*!< RSQ3 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ2_RSQ2_Pos                (10UL)                    /*!< RSQ2 (Bit 10)                                         */
#define ADC1_RSQ2_RSQ2_Msk                (0x7c00UL)                /*!< RSQ2 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ2_RSQ1_Pos                (5UL)                     /*!< RSQ1 (Bit 5)                                          */
#define ADC1_RSQ2_RSQ1_Msk                (0x3e0UL)                 /*!< RSQ1 (Bitfield-Mask: 0x1f)                            */
#define ADC1_RSQ2_RSQ0_Pos                (0UL)                     /*!< RSQ0 (Bit 0)                                          */
#define ADC1_RSQ2_RSQ0_Msk                (0x1fUL)                  /*!< RSQ0 (Bitfield-Mask: 0x1f)                            */
/* ==========================================================  ISQ  ========================================================== */
#define ADC1_ISQ_IL_Pos                   (20UL)                    /*!< IL (Bit 20)                                           */
#define ADC1_ISQ_IL_Msk                   (0x300000UL)              /*!< IL (Bitfield-Mask: 0x03)                              */
#define ADC1_ISQ_ISQ3_Pos                 (15UL)                    /*!< ISQ3 (Bit 15)                                         */
#define ADC1_ISQ_ISQ3_Msk                 (0xf8000UL)               /*!< ISQ3 (Bitfield-Mask: 0x1f)                            */
#define ADC1_ISQ_ISQ2_Pos                 (10UL)                    /*!< ISQ2 (Bit 10)                                         */
#define ADC1_ISQ_ISQ2_Msk                 (0x7c00UL)                /*!< ISQ2 (Bitfield-Mask: 0x1f)                            */
#define ADC1_ISQ_ISQ1_Pos                 (5UL)                     /*!< ISQ1 (Bit 5)                                          */
#define ADC1_ISQ_ISQ1_Msk                 (0x3e0UL)                 /*!< ISQ1 (Bitfield-Mask: 0x1f)                            */
#define ADC1_ISQ_ISQ0_Pos                 (0UL)                     /*!< ISQ0 (Bit 0)                                          */
#define ADC1_ISQ_ISQ0_Msk                 (0x1fUL)                  /*!< ISQ0 (Bitfield-Mask: 0x1f)                            */
/* ========================================================  IDATA0  ========================================================= */
#define ADC1_IDATA0_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC1_IDATA0_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* ========================================================  IDATA1  ========================================================= */
#define ADC1_IDATA1_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC1_IDATA1_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* ========================================================  IDATA2  ========================================================= */
#define ADC1_IDATA2_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC1_IDATA2_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* ========================================================  IDATA3  ========================================================= */
#define ADC1_IDATA3_IDATAn_Pos            (0UL)                     /*!< IDATAn (Bit 0)                                        */
#define ADC1_IDATA3_IDATAn_Msk            (0xffffUL)                /*!< IDATAn (Bitfield-Mask: 0xffff)                        */
/* =========================================================  RDATA  ========================================================= */
#define ADC1_RDATA_RDATA_Pos              (0UL)                     /*!< RDATA (Bit 0)                                         */
#define ADC1_RDATA_RDATA_Msk              (0xffffUL)                /*!< RDATA (Bitfield-Mask: 0xffff)                         */


/* =========================================================================================================================== */
/* ================                                           AFIO                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  EC  =========================================================== */
#define AFIO_EC_EOE_Pos                   (7UL)                     /*!< EOE (Bit 7)                                           */
#define AFIO_EC_EOE_Msk                   (0x80UL)                  /*!< EOE (Bitfield-Mask: 0x01)                             */
#define AFIO_EC_PORT_Pos                  (4UL)                     /*!< PORT (Bit 4)                                          */
#define AFIO_EC_PORT_Msk                  (0x70UL)                  /*!< PORT (Bitfield-Mask: 0x07)                            */
#define AFIO_EC_PIN_Pos                   (0UL)                     /*!< PIN (Bit 0)                                           */
#define AFIO_EC_PIN_Msk                   (0xfUL)                   /*!< PIN (Bitfield-Mask: 0x0f)                             */
/* =========================================================  PCF0  ========================================================== */
#define AFIO_PCF0_TIMER1ITI1_REMAP_Pos    (29UL)                    /*!< TIMER1ITI1_REMAP (Bit 29)                             */
#define AFIO_PCF0_TIMER1ITI1_REMAP_Msk    (0x20000000UL)            /*!< TIMER1ITI1_REMAP (Bitfield-Mask: 0x01)                */
#define AFIO_PCF0_SPI2_REMAP_Pos          (28UL)                    /*!< SPI2_REMAP (Bit 28)                                   */
#define AFIO_PCF0_SPI2_REMAP_Msk          (0x10000000UL)            /*!< SPI2_REMAP (Bitfield-Mask: 0x01)                      */
#define AFIO_PCF0_SWJ_CFG_Pos             (24UL)                    /*!< SWJ_CFG (Bit 24)                                      */
#define AFIO_PCF0_SWJ_CFG_Msk             (0x7000000UL)             /*!< SWJ_CFG (Bitfield-Mask: 0x07)                         */
#define AFIO_PCF0_CAN1_REMAP_Pos          (22UL)                    /*!< CAN1_REMAP (Bit 22)                                   */
#define AFIO_PCF0_CAN1_REMAP_Msk          (0x400000UL)              /*!< CAN1_REMAP (Bitfield-Mask: 0x01)                      */
#define AFIO_PCF0_TIMER4CH3_IREMAP_Pos    (16UL)                    /*!< TIMER4CH3_IREMAP (Bit 16)                             */
#define AFIO_PCF0_TIMER4CH3_IREMAP_Msk    (0x10000UL)               /*!< TIMER4CH3_IREMAP (Bitfield-Mask: 0x01)                */
#define AFIO_PCF0_PD01_REMAP_Pos          (15UL)                    /*!< PD01_REMAP (Bit 15)                                   */
#define AFIO_PCF0_PD01_REMAP_Msk          (0x8000UL)                /*!< PD01_REMAP (Bitfield-Mask: 0x01)                      */
#define AFIO_PCF0_CAN0_REMAP_Pos          (13UL)                    /*!< CAN0_REMAP (Bit 13)                                   */
#define AFIO_PCF0_CAN0_REMAP_Msk          (0x6000UL)                /*!< CAN0_REMAP (Bitfield-Mask: 0x03)                      */
#define AFIO_PCF0_TIMER3_REMAP_Pos        (12UL)                    /*!< TIMER3_REMAP (Bit 12)                                 */
#define AFIO_PCF0_TIMER3_REMAP_Msk        (0x1000UL)                /*!< TIMER3_REMAP (Bitfield-Mask: 0x01)                    */
#define AFIO_PCF0_TIMER2_REMAP_Pos        (10UL)                    /*!< TIMER2_REMAP (Bit 10)                                 */
#define AFIO_PCF0_TIMER2_REMAP_Msk        (0xc00UL)                 /*!< TIMER2_REMAP (Bitfield-Mask: 0x03)                    */
#define AFIO_PCF0_TIMER1_REMAP_Pos        (8UL)                     /*!< TIMER1_REMAP (Bit 8)                                  */
#define AFIO_PCF0_TIMER1_REMAP_Msk        (0x300UL)                 /*!< TIMER1_REMAP (Bitfield-Mask: 0x03)                    */
#define AFIO_PCF0_TIMER0_REMAP_Pos        (6UL)                     /*!< TIMER0_REMAP (Bit 6)                                  */
#define AFIO_PCF0_TIMER0_REMAP_Msk        (0xc0UL)                  /*!< TIMER0_REMAP (Bitfield-Mask: 0x03)                    */
#define AFIO_PCF0_USART2_REMAP_Pos        (4UL)                     /*!< USART2_REMAP (Bit 4)                                  */
#define AFIO_PCF0_USART2_REMAP_Msk        (0x30UL)                  /*!< USART2_REMAP (Bitfield-Mask: 0x03)                    */
#define AFIO_PCF0_USART1_REMAP_Pos        (3UL)                     /*!< USART1_REMAP (Bit 3)                                  */
#define AFIO_PCF0_USART1_REMAP_Msk        (0x8UL)                   /*!< USART1_REMAP (Bitfield-Mask: 0x01)                    */
#define AFIO_PCF0_USART0_REMAP_Pos        (2UL)                     /*!< USART0_REMAP (Bit 2)                                  */
#define AFIO_PCF0_USART0_REMAP_Msk        (0x4UL)                   /*!< USART0_REMAP (Bitfield-Mask: 0x01)                    */
#define AFIO_PCF0_I2C0_REMAP_Pos          (1UL)                     /*!< I2C0_REMAP (Bit 1)                                    */
#define AFIO_PCF0_I2C0_REMAP_Msk          (0x2UL)                   /*!< I2C0_REMAP (Bitfield-Mask: 0x01)                      */
#define AFIO_PCF0_SPI0_REMAP_Pos          (0UL)                     /*!< SPI0_REMAP (Bit 0)                                    */
#define AFIO_PCF0_SPI0_REMAP_Msk          (0x1UL)                   /*!< SPI0_REMAP (Bitfield-Mask: 0x01)                      */
/* ========================================================  EXTISS0  ======================================================== */
#define AFIO_EXTISS0_EXTI3_SS_Pos         (12UL)                    /*!< EXTI3_SS (Bit 12)                                     */
#define AFIO_EXTISS0_EXTI3_SS_Msk         (0xf000UL)                /*!< EXTI3_SS (Bitfield-Mask: 0x0f)                        */
#define AFIO_EXTISS0_EXTI2_SS_Pos         (8UL)                     /*!< EXTI2_SS (Bit 8)                                      */
#define AFIO_EXTISS0_EXTI2_SS_Msk         (0xf00UL)                 /*!< EXTI2_SS (Bitfield-Mask: 0x0f)                        */
#define AFIO_EXTISS0_EXTI1_SS_Pos         (4UL)                     /*!< EXTI1_SS (Bit 4)                                      */
#define AFIO_EXTISS0_EXTI1_SS_Msk         (0xf0UL)                  /*!< EXTI1_SS (Bitfield-Mask: 0x0f)                        */
#define AFIO_EXTISS0_EXTI0_SS_Pos         (0UL)                     /*!< EXTI0_SS (Bit 0)                                      */
#define AFIO_EXTISS0_EXTI0_SS_Msk         (0xfUL)                   /*!< EXTI0_SS (Bitfield-Mask: 0x0f)                        */
/* ========================================================  EXTISS1  ======================================================== */
#define AFIO_EXTISS1_EXTI7_SS_Pos         (12UL)                    /*!< EXTI7_SS (Bit 12)                                     */
#define AFIO_EXTISS1_EXTI7_SS_Msk         (0xf000UL)                /*!< EXTI7_SS (Bitfield-Mask: 0x0f)                        */
#define AFIO_EXTISS1_EXTI6_SS_Pos         (8UL)                     /*!< EXTI6_SS (Bit 8)                                      */
#define AFIO_EXTISS1_EXTI6_SS_Msk         (0xf00UL)                 /*!< EXTI6_SS (Bitfield-Mask: 0x0f)                        */
#define AFIO_EXTISS1_EXTI5_SS_Pos         (4UL)                     /*!< EXTI5_SS (Bit 4)                                      */
#define AFIO_EXTISS1_EXTI5_SS_Msk         (0xf0UL)                  /*!< EXTI5_SS (Bitfield-Mask: 0x0f)                        */
#define AFIO_EXTISS1_EXTI4_SS_Pos         (0UL)                     /*!< EXTI4_SS (Bit 0)                                      */
#define AFIO_EXTISS1_EXTI4_SS_Msk         (0xfUL)                   /*!< EXTI4_SS (Bitfield-Mask: 0x0f)                        */
/* ========================================================  EXTISS2  ======================================================== */
#define AFIO_EXTISS2_EXTI11_SS_Pos        (12UL)                    /*!< EXTI11_SS (Bit 12)                                    */
#define AFIO_EXTISS2_EXTI11_SS_Msk        (0xf000UL)                /*!< EXTI11_SS (Bitfield-Mask: 0x0f)                       */
#define AFIO_EXTISS2_EXTI10_SS_Pos        (8UL)                     /*!< EXTI10_SS (Bit 8)                                     */
#define AFIO_EXTISS2_EXTI10_SS_Msk        (0xf00UL)                 /*!< EXTI10_SS (Bitfield-Mask: 0x0f)                       */
#define AFIO_EXTISS2_EXTI9_SS_Pos         (4UL)                     /*!< EXTI9_SS (Bit 4)                                      */
#define AFIO_EXTISS2_EXTI9_SS_Msk         (0xf0UL)                  /*!< EXTI9_SS (Bitfield-Mask: 0x0f)                        */
#define AFIO_EXTISS2_EXTI8_SS_Pos         (0UL)                     /*!< EXTI8_SS (Bit 0)                                      */
#define AFIO_EXTISS2_EXTI8_SS_Msk         (0xfUL)                   /*!< EXTI8_SS (Bitfield-Mask: 0x0f)                        */
/* ========================================================  EXTISS3  ======================================================== */
#define AFIO_EXTISS3_EXTI15_SS_Pos        (12UL)                    /*!< EXTI15_SS (Bit 12)                                    */
#define AFIO_EXTISS3_EXTI15_SS_Msk        (0xf000UL)                /*!< EXTI15_SS (Bitfield-Mask: 0x0f)                       */
#define AFIO_EXTISS3_EXTI14_SS_Pos        (8UL)                     /*!< EXTI14_SS (Bit 8)                                     */
#define AFIO_EXTISS3_EXTI14_SS_Msk        (0xf00UL)                 /*!< EXTI14_SS (Bitfield-Mask: 0x0f)                       */
#define AFIO_EXTISS3_EXTI13_SS_Pos        (4UL)                     /*!< EXTI13_SS (Bit 4)                                     */
#define AFIO_EXTISS3_EXTI13_SS_Msk        (0xf0UL)                  /*!< EXTI13_SS (Bitfield-Mask: 0x0f)                       */
#define AFIO_EXTISS3_EXTI12_SS_Pos        (0UL)                     /*!< EXTI12_SS (Bit 0)                                     */
#define AFIO_EXTISS3_EXTI12_SS_Msk        (0xfUL)                   /*!< EXTI12_SS (Bitfield-Mask: 0x0f)                       */
/* =========================================================  PCF1  ========================================================== */
#define AFIO_PCF1_EXMC_NADV_Pos           (10UL)                    /*!< EXMC_NADV (Bit 10)                                    */
#define AFIO_PCF1_EXMC_NADV_Msk           (0x400UL)                 /*!< EXMC_NADV (Bitfield-Mask: 0x01)                       */


/* =========================================================================================================================== */
/* ================                                            BKP                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  DATA0  ========================================================= */
#define BKP_DATA0_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA0_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA1  ========================================================= */
#define BKP_DATA1_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA1_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA2  ========================================================= */
#define BKP_DATA2_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA2_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA3  ========================================================= */
#define BKP_DATA3_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA3_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA4  ========================================================= */
#define BKP_DATA4_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA4_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA5  ========================================================= */
#define BKP_DATA5_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA5_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA6  ========================================================= */
#define BKP_DATA6_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA6_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA7  ========================================================= */
#define BKP_DATA7_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA7_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA8  ========================================================= */
#define BKP_DATA8_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA8_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DATA9  ========================================================= */
#define BKP_DATA9_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA9_DATA_Msk                (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA10  ========================================================= */
#define BKP_DATA10_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA10_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA11  ========================================================= */
#define BKP_DATA11_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA11_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA12  ========================================================= */
#define BKP_DATA12_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA12_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA13  ========================================================= */
#define BKP_DATA13_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA13_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA14  ========================================================= */
#define BKP_DATA14_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA14_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA15  ========================================================= */
#define BKP_DATA15_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA15_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA16  ========================================================= */
#define BKP_DATA16_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA16_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA17  ========================================================= */
#define BKP_DATA17_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA17_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA18  ========================================================= */
#define BKP_DATA18_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA18_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA19  ========================================================= */
#define BKP_DATA19_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA19_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA20  ========================================================= */
#define BKP_DATA20_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA20_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA21  ========================================================= */
#define BKP_DATA21_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA21_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA22  ========================================================= */
#define BKP_DATA22_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA22_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA23  ========================================================= */
#define BKP_DATA23_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA23_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA24  ========================================================= */
#define BKP_DATA24_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA24_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA25  ========================================================= */
#define BKP_DATA25_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA25_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA26  ========================================================= */
#define BKP_DATA26_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA26_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA27  ========================================================= */
#define BKP_DATA27_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA27_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA28  ========================================================= */
#define BKP_DATA28_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA28_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA29  ========================================================= */
#define BKP_DATA29_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA29_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA30  ========================================================= */
#define BKP_DATA30_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA30_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA31  ========================================================= */
#define BKP_DATA31_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA31_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA32  ========================================================= */
#define BKP_DATA32_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA32_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA33  ========================================================= */
#define BKP_DATA33_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA33_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA34  ========================================================= */
#define BKP_DATA34_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA34_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA35  ========================================================= */
#define BKP_DATA35_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA35_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA36  ========================================================= */
#define BKP_DATA36_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA36_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA37  ========================================================= */
#define BKP_DATA37_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA37_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA38  ========================================================= */
#define BKP_DATA38_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA38_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA39  ========================================================= */
#define BKP_DATA39_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA39_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA40  ========================================================= */
#define BKP_DATA40_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA40_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATA41  ========================================================= */
#define BKP_DATA41_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define BKP_DATA41_DATA_Msk               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  OCTL  ========================================================== */
#define BKP_OCTL_ROSEL_Pos                (9UL)                     /*!< ROSEL (Bit 9)                                         */
#define BKP_OCTL_ROSEL_Msk                (0x200UL)                 /*!< ROSEL (Bitfield-Mask: 0x01)                           */
#define BKP_OCTL_ASOEN_Pos                (8UL)                     /*!< ASOEN (Bit 8)                                         */
#define BKP_OCTL_ASOEN_Msk                (0x100UL)                 /*!< ASOEN (Bitfield-Mask: 0x01)                           */
#define BKP_OCTL_COEN_Pos                 (7UL)                     /*!< COEN (Bit 7)                                          */
#define BKP_OCTL_COEN_Msk                 (0x80UL)                  /*!< COEN (Bitfield-Mask: 0x01)                            */
#define BKP_OCTL_RCCV_Pos                 (0UL)                     /*!< RCCV (Bit 0)                                          */
#define BKP_OCTL_RCCV_Msk                 (0x7fUL)                  /*!< RCCV (Bitfield-Mask: 0x7f)                            */
/* =========================================================  TPCTL  ========================================================= */
#define BKP_TPCTL_TPAL_Pos                (1UL)                     /*!< TPAL (Bit 1)                                          */
#define BKP_TPCTL_TPAL_Msk                (0x2UL)                   /*!< TPAL (Bitfield-Mask: 0x01)                            */
#define BKP_TPCTL_TPEN_Pos                (0UL)                     /*!< TPEN (Bit 0)                                          */
#define BKP_TPCTL_TPEN_Msk                (0x1UL)                   /*!< TPEN (Bitfield-Mask: 0x01)                            */
/* =========================================================  TPCS  ========================================================== */
#define BKP_TPCS_TIF_Pos                  (9UL)                     /*!< TIF (Bit 9)                                           */
#define BKP_TPCS_TIF_Msk                  (0x200UL)                 /*!< TIF (Bitfield-Mask: 0x01)                             */
#define BKP_TPCS_TEF_Pos                  (8UL)                     /*!< TEF (Bit 8)                                           */
#define BKP_TPCS_TEF_Msk                  (0x100UL)                 /*!< TEF (Bitfield-Mask: 0x01)                             */
#define BKP_TPCS_TPIE_Pos                 (2UL)                     /*!< TPIE (Bit 2)                                          */
#define BKP_TPCS_TPIE_Msk                 (0x4UL)                   /*!< TPIE (Bitfield-Mask: 0x01)                            */
#define BKP_TPCS_TIR_Pos                  (1UL)                     /*!< TIR (Bit 1)                                           */
#define BKP_TPCS_TIR_Msk                  (0x2UL)                   /*!< TIR (Bitfield-Mask: 0x01)                             */
#define BKP_TPCS_TER_Pos                  (0UL)                     /*!< TER (Bit 0)                                           */
#define BKP_TPCS_TER_Msk                  (0x1UL)                   /*!< TER (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                           CAN0                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CTL  ========================================================== */
#define CAN0_CTL_DFZ_Pos                  (16UL)                    /*!< DFZ (Bit 16)                                          */
#define CAN0_CTL_DFZ_Msk                  (0x10000UL)               /*!< DFZ (Bitfield-Mask: 0x01)                             */
#define CAN0_CTL_SWRST_Pos                (15UL)                    /*!< SWRST (Bit 15)                                        */
#define CAN0_CTL_SWRST_Msk                (0x8000UL)                /*!< SWRST (Bitfield-Mask: 0x01)                           */
#define CAN0_CTL_TTC_Pos                  (7UL)                     /*!< TTC (Bit 7)                                           */
#define CAN0_CTL_TTC_Msk                  (0x80UL)                  /*!< TTC (Bitfield-Mask: 0x01)                             */
#define CAN0_CTL_ABOR_Pos                 (6UL)                     /*!< ABOR (Bit 6)                                          */
#define CAN0_CTL_ABOR_Msk                 (0x40UL)                  /*!< ABOR (Bitfield-Mask: 0x01)                            */
#define CAN0_CTL_AWU_Pos                  (5UL)                     /*!< AWU (Bit 5)                                           */
#define CAN0_CTL_AWU_Msk                  (0x20UL)                  /*!< AWU (Bitfield-Mask: 0x01)                             */
#define CAN0_CTL_ARD_Pos                  (4UL)                     /*!< ARD (Bit 4)                                           */
#define CAN0_CTL_ARD_Msk                  (0x10UL)                  /*!< ARD (Bitfield-Mask: 0x01)                             */
#define CAN0_CTL_RFOD_Pos                 (3UL)                     /*!< RFOD (Bit 3)                                          */
#define CAN0_CTL_RFOD_Msk                 (0x8UL)                   /*!< RFOD (Bitfield-Mask: 0x01)                            */
#define CAN0_CTL_TFO_Pos                  (2UL)                     /*!< TFO (Bit 2)                                           */
#define CAN0_CTL_TFO_Msk                  (0x4UL)                   /*!< TFO (Bitfield-Mask: 0x01)                             */
#define CAN0_CTL_SLPWMOD_Pos              (1UL)                     /*!< SLPWMOD (Bit 1)                                       */
#define CAN0_CTL_SLPWMOD_Msk              (0x2UL)                   /*!< SLPWMOD (Bitfield-Mask: 0x01)                         */
#define CAN0_CTL_IWMOD_Pos                (0UL)                     /*!< IWMOD (Bit 0)                                         */
#define CAN0_CTL_IWMOD_Msk                (0x1UL)                   /*!< IWMOD (Bitfield-Mask: 0x01)                           */
/* =========================================================  STAT  ========================================================== */
#define CAN0_STAT_RXL_Pos                 (11UL)                    /*!< RXL (Bit 11)                                          */
#define CAN0_STAT_RXL_Msk                 (0x800UL)                 /*!< RXL (Bitfield-Mask: 0x01)                             */
#define CAN0_STAT_LASTRX_Pos              (10UL)                    /*!< LASTRX (Bit 10)                                       */
#define CAN0_STAT_LASTRX_Msk              (0x400UL)                 /*!< LASTRX (Bitfield-Mask: 0x01)                          */
#define CAN0_STAT_RS_Pos                  (9UL)                     /*!< RS (Bit 9)                                            */
#define CAN0_STAT_RS_Msk                  (0x200UL)                 /*!< RS (Bitfield-Mask: 0x01)                              */
#define CAN0_STAT_TS_Pos                  (8UL)                     /*!< TS (Bit 8)                                            */
#define CAN0_STAT_TS_Msk                  (0x100UL)                 /*!< TS (Bitfield-Mask: 0x01)                              */
#define CAN0_STAT_SLPIF_Pos               (4UL)                     /*!< SLPIF (Bit 4)                                         */
#define CAN0_STAT_SLPIF_Msk               (0x10UL)                  /*!< SLPIF (Bitfield-Mask: 0x01)                           */
#define CAN0_STAT_WUIF_Pos                (3UL)                     /*!< WUIF (Bit 3)                                          */
#define CAN0_STAT_WUIF_Msk                (0x8UL)                   /*!< WUIF (Bitfield-Mask: 0x01)                            */
#define CAN0_STAT_ERRIF_Pos               (2UL)                     /*!< ERRIF (Bit 2)                                         */
#define CAN0_STAT_ERRIF_Msk               (0x4UL)                   /*!< ERRIF (Bitfield-Mask: 0x01)                           */
#define CAN0_STAT_SLPWS_Pos               (1UL)                     /*!< SLPWS (Bit 1)                                         */
#define CAN0_STAT_SLPWS_Msk               (0x2UL)                   /*!< SLPWS (Bitfield-Mask: 0x01)                           */
#define CAN0_STAT_IWS_Pos                 (0UL)                     /*!< IWS (Bit 0)                                           */
#define CAN0_STAT_IWS_Msk                 (0x1UL)                   /*!< IWS (Bitfield-Mask: 0x01)                             */
/* =========================================================  TSTAT  ========================================================= */
#define CAN0_TSTAT_TMLS2_Pos              (31UL)                    /*!< TMLS2 (Bit 31)                                        */
#define CAN0_TSTAT_TMLS2_Msk              (0x80000000UL)            /*!< TMLS2 (Bitfield-Mask: 0x01)                           */
#define CAN0_TSTAT_TMLS1_Pos              (30UL)                    /*!< TMLS1 (Bit 30)                                        */
#define CAN0_TSTAT_TMLS1_Msk              (0x40000000UL)            /*!< TMLS1 (Bitfield-Mask: 0x01)                           */
#define CAN0_TSTAT_TMLS0_Pos              (29UL)                    /*!< TMLS0 (Bit 29)                                        */
#define CAN0_TSTAT_TMLS0_Msk              (0x20000000UL)            /*!< TMLS0 (Bitfield-Mask: 0x01)                           */
#define CAN0_TSTAT_TME2_Pos               (28UL)                    /*!< TME2 (Bit 28)                                         */
#define CAN0_TSTAT_TME2_Msk               (0x10000000UL)            /*!< TME2 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_TME1_Pos               (27UL)                    /*!< TME1 (Bit 27)                                         */
#define CAN0_TSTAT_TME1_Msk               (0x8000000UL)             /*!< TME1 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_TME0_Pos               (26UL)                    /*!< TME0 (Bit 26)                                         */
#define CAN0_TSTAT_TME0_Msk               (0x4000000UL)             /*!< TME0 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_NUM_Pos                (24UL)                    /*!< NUM (Bit 24)                                          */
#define CAN0_TSTAT_NUM_Msk                (0x3000000UL)             /*!< NUM (Bitfield-Mask: 0x03)                             */
#define CAN0_TSTAT_MST2_Pos               (23UL)                    /*!< MST2 (Bit 23)                                         */
#define CAN0_TSTAT_MST2_Msk               (0x800000UL)              /*!< MST2 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MTE2_Pos               (19UL)                    /*!< MTE2 (Bit 19)                                         */
#define CAN0_TSTAT_MTE2_Msk               (0x80000UL)               /*!< MTE2 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MAL2_Pos               (18UL)                    /*!< MAL2 (Bit 18)                                         */
#define CAN0_TSTAT_MAL2_Msk               (0x40000UL)               /*!< MAL2 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MTFNERR2_Pos           (17UL)                    /*!< MTFNERR2 (Bit 17)                                     */
#define CAN0_TSTAT_MTFNERR2_Msk           (0x20000UL)               /*!< MTFNERR2 (Bitfield-Mask: 0x01)                        */
#define CAN0_TSTAT_MTF2_Pos               (16UL)                    /*!< MTF2 (Bit 16)                                         */
#define CAN0_TSTAT_MTF2_Msk               (0x10000UL)               /*!< MTF2 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MST1_Pos               (15UL)                    /*!< MST1 (Bit 15)                                         */
#define CAN0_TSTAT_MST1_Msk               (0x8000UL)                /*!< MST1 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MTE1_Pos               (11UL)                    /*!< MTE1 (Bit 11)                                         */
#define CAN0_TSTAT_MTE1_Msk               (0x800UL)                 /*!< MTE1 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MAL1_Pos               (10UL)                    /*!< MAL1 (Bit 10)                                         */
#define CAN0_TSTAT_MAL1_Msk               (0x400UL)                 /*!< MAL1 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MTFNERR1_Pos           (9UL)                     /*!< MTFNERR1 (Bit 9)                                      */
#define CAN0_TSTAT_MTFNERR1_Msk           (0x200UL)                 /*!< MTFNERR1 (Bitfield-Mask: 0x01)                        */
#define CAN0_TSTAT_MTF1_Pos               (8UL)                     /*!< MTF1 (Bit 8)                                          */
#define CAN0_TSTAT_MTF1_Msk               (0x100UL)                 /*!< MTF1 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MST0_Pos               (7UL)                     /*!< MST0 (Bit 7)                                          */
#define CAN0_TSTAT_MST0_Msk               (0x80UL)                  /*!< MST0 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MTE0_Pos               (3UL)                     /*!< MTE0 (Bit 3)                                          */
#define CAN0_TSTAT_MTE0_Msk               (0x8UL)                   /*!< MTE0 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MAL0_Pos               (2UL)                     /*!< MAL0 (Bit 2)                                          */
#define CAN0_TSTAT_MAL0_Msk               (0x4UL)                   /*!< MAL0 (Bitfield-Mask: 0x01)                            */
#define CAN0_TSTAT_MTFNERR0_Pos           (1UL)                     /*!< MTFNERR0 (Bit 1)                                      */
#define CAN0_TSTAT_MTFNERR0_Msk           (0x2UL)                   /*!< MTFNERR0 (Bitfield-Mask: 0x01)                        */
#define CAN0_TSTAT_MTF0_Pos               (0UL)                     /*!< MTF0 (Bit 0)                                          */
#define CAN0_TSTAT_MTF0_Msk               (0x1UL)                   /*!< MTF0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  RFIFO0  ========================================================= */
#define CAN0_RFIFO0_RFD0_Pos              (5UL)                     /*!< RFD0 (Bit 5)                                          */
#define CAN0_RFIFO0_RFD0_Msk              (0x20UL)                  /*!< RFD0 (Bitfield-Mask: 0x01)                            */
#define CAN0_RFIFO0_RFO0_Pos              (4UL)                     /*!< RFO0 (Bit 4)                                          */
#define CAN0_RFIFO0_RFO0_Msk              (0x10UL)                  /*!< RFO0 (Bitfield-Mask: 0x01)                            */
#define CAN0_RFIFO0_RFF0_Pos              (3UL)                     /*!< RFF0 (Bit 3)                                          */
#define CAN0_RFIFO0_RFF0_Msk              (0x8UL)                   /*!< RFF0 (Bitfield-Mask: 0x01)                            */
#define CAN0_RFIFO0_RFL0_Pos              (0UL)                     /*!< RFL0 (Bit 0)                                          */
#define CAN0_RFIFO0_RFL0_Msk              (0x3UL)                   /*!< RFL0 (Bitfield-Mask: 0x03)                            */
/* ========================================================  RFIFO1  ========================================================= */
#define CAN0_RFIFO1_RFD1_Pos              (5UL)                     /*!< RFD1 (Bit 5)                                          */
#define CAN0_RFIFO1_RFD1_Msk              (0x20UL)                  /*!< RFD1 (Bitfield-Mask: 0x01)                            */
#define CAN0_RFIFO1_RFO1_Pos              (4UL)                     /*!< RFO1 (Bit 4)                                          */
#define CAN0_RFIFO1_RFO1_Msk              (0x10UL)                  /*!< RFO1 (Bitfield-Mask: 0x01)                            */
#define CAN0_RFIFO1_RFF1_Pos              (3UL)                     /*!< RFF1 (Bit 3)                                          */
#define CAN0_RFIFO1_RFF1_Msk              (0x8UL)                   /*!< RFF1 (Bitfield-Mask: 0x01)                            */
#define CAN0_RFIFO1_RFL1_Pos              (0UL)                     /*!< RFL1 (Bit 0)                                          */
#define CAN0_RFIFO1_RFL1_Msk              (0x3UL)                   /*!< RFL1 (Bitfield-Mask: 0x03)                            */
/* =========================================================  INTEN  ========================================================= */
#define CAN0_INTEN_SLPWIE_Pos             (17UL)                    /*!< SLPWIE (Bit 17)                                       */
#define CAN0_INTEN_SLPWIE_Msk             (0x20000UL)               /*!< SLPWIE (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_WIE_Pos                (16UL)                    /*!< WIE (Bit 16)                                          */
#define CAN0_INTEN_WIE_Msk                (0x10000UL)               /*!< WIE (Bitfield-Mask: 0x01)                             */
#define CAN0_INTEN_ERRIE_Pos              (15UL)                    /*!< ERRIE (Bit 15)                                        */
#define CAN0_INTEN_ERRIE_Msk              (0x8000UL)                /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define CAN0_INTEN_ERRNIE_Pos             (11UL)                    /*!< ERRNIE (Bit 11)                                       */
#define CAN0_INTEN_ERRNIE_Msk             (0x800UL)                 /*!< ERRNIE (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_BOIE_Pos               (10UL)                    /*!< BOIE (Bit 10)                                         */
#define CAN0_INTEN_BOIE_Msk               (0x400UL)                 /*!< BOIE (Bitfield-Mask: 0x01)                            */
#define CAN0_INTEN_PERRIE_Pos             (9UL)                     /*!< PERRIE (Bit 9)                                        */
#define CAN0_INTEN_PERRIE_Msk             (0x200UL)                 /*!< PERRIE (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_WERRIE_Pos             (8UL)                     /*!< WERRIE (Bit 8)                                        */
#define CAN0_INTEN_WERRIE_Msk             (0x100UL)                 /*!< WERRIE (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_RFOIE1_Pos             (6UL)                     /*!< RFOIE1 (Bit 6)                                        */
#define CAN0_INTEN_RFOIE1_Msk             (0x40UL)                  /*!< RFOIE1 (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_RFFIE1_Pos             (5UL)                     /*!< RFFIE1 (Bit 5)                                        */
#define CAN0_INTEN_RFFIE1_Msk             (0x20UL)                  /*!< RFFIE1 (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_RFNEIE1_Pos            (4UL)                     /*!< RFNEIE1 (Bit 4)                                       */
#define CAN0_INTEN_RFNEIE1_Msk            (0x10UL)                  /*!< RFNEIE1 (Bitfield-Mask: 0x01)                         */
#define CAN0_INTEN_RFOIE0_Pos             (3UL)                     /*!< RFOIE0 (Bit 3)                                        */
#define CAN0_INTEN_RFOIE0_Msk             (0x8UL)                   /*!< RFOIE0 (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_RFFIE0_Pos             (2UL)                     /*!< RFFIE0 (Bit 2)                                        */
#define CAN0_INTEN_RFFIE0_Msk             (0x4UL)                   /*!< RFFIE0 (Bitfield-Mask: 0x01)                          */
#define CAN0_INTEN_RFNEIE0_Pos            (1UL)                     /*!< RFNEIE0 (Bit 1)                                       */
#define CAN0_INTEN_RFNEIE0_Msk            (0x2UL)                   /*!< RFNEIE0 (Bitfield-Mask: 0x01)                         */
#define CAN0_INTEN_TMEIE_Pos              (0UL)                     /*!< TMEIE (Bit 0)                                         */
#define CAN0_INTEN_TMEIE_Msk              (0x1UL)                   /*!< TMEIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ERR  ========================================================== */
#define CAN0_ERR_RECNT_Pos                (24UL)                    /*!< RECNT (Bit 24)                                        */
#define CAN0_ERR_RECNT_Msk                (0xff000000UL)            /*!< RECNT (Bitfield-Mask: 0xff)                           */
#define CAN0_ERR_TECNT_Pos                (16UL)                    /*!< TECNT (Bit 16)                                        */
#define CAN0_ERR_TECNT_Msk                (0xff0000UL)              /*!< TECNT (Bitfield-Mask: 0xff)                           */
#define CAN0_ERR_ERRN_Pos                 (4UL)                     /*!< ERRN (Bit 4)                                          */
#define CAN0_ERR_ERRN_Msk                 (0x70UL)                  /*!< ERRN (Bitfield-Mask: 0x07)                            */
#define CAN0_ERR_BOERR_Pos                (2UL)                     /*!< BOERR (Bit 2)                                         */
#define CAN0_ERR_BOERR_Msk                (0x4UL)                   /*!< BOERR (Bitfield-Mask: 0x01)                           */
#define CAN0_ERR_PERR_Pos                 (1UL)                     /*!< PERR (Bit 1)                                          */
#define CAN0_ERR_PERR_Msk                 (0x2UL)                   /*!< PERR (Bitfield-Mask: 0x01)                            */
#define CAN0_ERR_WERR_Pos                 (0UL)                     /*!< WERR (Bit 0)                                          */
#define CAN0_ERR_WERR_Msk                 (0x1UL)                   /*!< WERR (Bitfield-Mask: 0x01)                            */
/* ==========================================================  BT  =========================================================== */
#define CAN0_BT_SCMOD_Pos                 (31UL)                    /*!< SCMOD (Bit 31)                                        */
#define CAN0_BT_SCMOD_Msk                 (0x80000000UL)            /*!< SCMOD (Bitfield-Mask: 0x01)                           */
#define CAN0_BT_LCMOD_Pos                 (30UL)                    /*!< LCMOD (Bit 30)                                        */
#define CAN0_BT_LCMOD_Msk                 (0x40000000UL)            /*!< LCMOD (Bitfield-Mask: 0x01)                           */
#define CAN0_BT_SJW_Pos                   (24UL)                    /*!< SJW (Bit 24)                                          */
#define CAN0_BT_SJW_Msk                   (0x3000000UL)             /*!< SJW (Bitfield-Mask: 0x03)                             */
#define CAN0_BT_BS2_Pos                   (20UL)                    /*!< BS2 (Bit 20)                                          */
#define CAN0_BT_BS2_Msk                   (0x700000UL)              /*!< BS2 (Bitfield-Mask: 0x07)                             */
#define CAN0_BT_BS1_Pos                   (16UL)                    /*!< BS1 (Bit 16)                                          */
#define CAN0_BT_BS1_Msk                   (0xf0000UL)               /*!< BS1 (Bitfield-Mask: 0x0f)                             */
#define CAN0_BT_BAUDPSC_Pos               (0UL)                     /*!< BAUDPSC (Bit 0)                                       */
#define CAN0_BT_BAUDPSC_Msk               (0x3ffUL)                 /*!< BAUDPSC (Bitfield-Mask: 0x3ff)                        */
/* =========================================================  TMI0  ========================================================== */
#define CAN0_TMI0_SFID_EFID_Pos           (21UL)                    /*!< SFID_EFID (Bit 21)                                    */
#define CAN0_TMI0_SFID_EFID_Msk           (0xffe00000UL)            /*!< SFID_EFID (Bitfield-Mask: 0x7ff)                      */
#define CAN0_TMI0_EFID_Pos                (3UL)                     /*!< EFID (Bit 3)                                          */
#define CAN0_TMI0_EFID_Msk                (0x1ffff8UL)              /*!< EFID (Bitfield-Mask: 0x3ffff)                         */
#define CAN0_TMI0_FF_Pos                  (2UL)                     /*!< FF (Bit 2)                                            */
#define CAN0_TMI0_FF_Msk                  (0x4UL)                   /*!< FF (Bitfield-Mask: 0x01)                              */
#define CAN0_TMI0_FT_Pos                  (1UL)                     /*!< FT (Bit 1)                                            */
#define CAN0_TMI0_FT_Msk                  (0x2UL)                   /*!< FT (Bitfield-Mask: 0x01)                              */
#define CAN0_TMI0_TEN_Pos                 (0UL)                     /*!< TEN (Bit 0)                                           */
#define CAN0_TMI0_TEN_Msk                 (0x1UL)                   /*!< TEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  TMP0  ========================================================== */
#define CAN0_TMP0_TS_Pos                  (16UL)                    /*!< TS (Bit 16)                                           */
#define CAN0_TMP0_TS_Msk                  (0xffff0000UL)            /*!< TS (Bitfield-Mask: 0xffff)                            */
#define CAN0_TMP0_TSEN_Pos                (8UL)                     /*!< TSEN (Bit 8)                                          */
#define CAN0_TMP0_TSEN_Msk                (0x100UL)                 /*!< TSEN (Bitfield-Mask: 0x01)                            */
#define CAN0_TMP0_DLENC_Pos               (0UL)                     /*!< DLENC (Bit 0)                                         */
#define CAN0_TMP0_DLENC_Msk               (0xfUL)                   /*!< DLENC (Bitfield-Mask: 0x0f)                           */
/* =======================================================  TMDATA00  ======================================================== */
#define CAN0_TMDATA00_DB3_Pos             (24UL)                    /*!< DB3 (Bit 24)                                          */
#define CAN0_TMDATA00_DB3_Msk             (0xff000000UL)            /*!< DB3 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA00_DB2_Pos             (16UL)                    /*!< DB2 (Bit 16)                                          */
#define CAN0_TMDATA00_DB2_Msk             (0xff0000UL)              /*!< DB2 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA00_DB1_Pos             (8UL)                     /*!< DB1 (Bit 8)                                           */
#define CAN0_TMDATA00_DB1_Msk             (0xff00UL)                /*!< DB1 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA00_DB0_Pos             (0UL)                     /*!< DB0 (Bit 0)                                           */
#define CAN0_TMDATA00_DB0_Msk             (0xffUL)                  /*!< DB0 (Bitfield-Mask: 0xff)                             */
/* =======================================================  TMDATA10  ======================================================== */
#define CAN0_TMDATA10_DB7_Pos             (24UL)                    /*!< DB7 (Bit 24)                                          */
#define CAN0_TMDATA10_DB7_Msk             (0xff000000UL)            /*!< DB7 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA10_DB6_Pos             (16UL)                    /*!< DB6 (Bit 16)                                          */
#define CAN0_TMDATA10_DB6_Msk             (0xff0000UL)              /*!< DB6 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA10_DB5_Pos             (8UL)                     /*!< DB5 (Bit 8)                                           */
#define CAN0_TMDATA10_DB5_Msk             (0xff00UL)                /*!< DB5 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA10_DB4_Pos             (0UL)                     /*!< DB4 (Bit 0)                                           */
#define CAN0_TMDATA10_DB4_Msk             (0xffUL)                  /*!< DB4 (Bitfield-Mask: 0xff)                             */
/* =========================================================  TMI1  ========================================================== */
#define CAN0_TMI1_SFID_EFID_Pos           (21UL)                    /*!< SFID_EFID (Bit 21)                                    */
#define CAN0_TMI1_SFID_EFID_Msk           (0xffe00000UL)            /*!< SFID_EFID (Bitfield-Mask: 0x7ff)                      */
#define CAN0_TMI1_EFID_Pos                (3UL)                     /*!< EFID (Bit 3)                                          */
#define CAN0_TMI1_EFID_Msk                (0x1ffff8UL)              /*!< EFID (Bitfield-Mask: 0x3ffff)                         */
#define CAN0_TMI1_FF_Pos                  (2UL)                     /*!< FF (Bit 2)                                            */
#define CAN0_TMI1_FF_Msk                  (0x4UL)                   /*!< FF (Bitfield-Mask: 0x01)                              */
#define CAN0_TMI1_FT_Pos                  (1UL)                     /*!< FT (Bit 1)                                            */
#define CAN0_TMI1_FT_Msk                  (0x2UL)                   /*!< FT (Bitfield-Mask: 0x01)                              */
#define CAN0_TMI1_TEN_Pos                 (0UL)                     /*!< TEN (Bit 0)                                           */
#define CAN0_TMI1_TEN_Msk                 (0x1UL)                   /*!< TEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  TMP1  ========================================================== */
#define CAN0_TMP1_TS_Pos                  (16UL)                    /*!< TS (Bit 16)                                           */
#define CAN0_TMP1_TS_Msk                  (0xffff0000UL)            /*!< TS (Bitfield-Mask: 0xffff)                            */
#define CAN0_TMP1_TSEN_Pos                (8UL)                     /*!< TSEN (Bit 8)                                          */
#define CAN0_TMP1_TSEN_Msk                (0x100UL)                 /*!< TSEN (Bitfield-Mask: 0x01)                            */
#define CAN0_TMP1_DLENC_Pos               (0UL)                     /*!< DLENC (Bit 0)                                         */
#define CAN0_TMP1_DLENC_Msk               (0xfUL)                   /*!< DLENC (Bitfield-Mask: 0x0f)                           */
/* =======================================================  TMDATA01  ======================================================== */
#define CAN0_TMDATA01_DB3_Pos             (24UL)                    /*!< DB3 (Bit 24)                                          */
#define CAN0_TMDATA01_DB3_Msk             (0xff000000UL)            /*!< DB3 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA01_DB2_Pos             (16UL)                    /*!< DB2 (Bit 16)                                          */
#define CAN0_TMDATA01_DB2_Msk             (0xff0000UL)              /*!< DB2 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA01_DB1_Pos             (8UL)                     /*!< DB1 (Bit 8)                                           */
#define CAN0_TMDATA01_DB1_Msk             (0xff00UL)                /*!< DB1 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA01_DB0_Pos             (0UL)                     /*!< DB0 (Bit 0)                                           */
#define CAN0_TMDATA01_DB0_Msk             (0xffUL)                  /*!< DB0 (Bitfield-Mask: 0xff)                             */
/* =======================================================  TMDATA11  ======================================================== */
#define CAN0_TMDATA11_DB7_Pos             (24UL)                    /*!< DB7 (Bit 24)                                          */
#define CAN0_TMDATA11_DB7_Msk             (0xff000000UL)            /*!< DB7 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA11_DB6_Pos             (16UL)                    /*!< DB6 (Bit 16)                                          */
#define CAN0_TMDATA11_DB6_Msk             (0xff0000UL)              /*!< DB6 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA11_DB5_Pos             (8UL)                     /*!< DB5 (Bit 8)                                           */
#define CAN0_TMDATA11_DB5_Msk             (0xff00UL)                /*!< DB5 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA11_DB4_Pos             (0UL)                     /*!< DB4 (Bit 0)                                           */
#define CAN0_TMDATA11_DB4_Msk             (0xffUL)                  /*!< DB4 (Bitfield-Mask: 0xff)                             */
/* =========================================================  TMI2  ========================================================== */
#define CAN0_TMI2_SFID_EFID_Pos           (21UL)                    /*!< SFID_EFID (Bit 21)                                    */
#define CAN0_TMI2_SFID_EFID_Msk           (0xffe00000UL)            /*!< SFID_EFID (Bitfield-Mask: 0x7ff)                      */
#define CAN0_TMI2_EFID_Pos                (3UL)                     /*!< EFID (Bit 3)                                          */
#define CAN0_TMI2_EFID_Msk                (0x1ffff8UL)              /*!< EFID (Bitfield-Mask: 0x3ffff)                         */
#define CAN0_TMI2_FF_Pos                  (2UL)                     /*!< FF (Bit 2)                                            */
#define CAN0_TMI2_FF_Msk                  (0x4UL)                   /*!< FF (Bitfield-Mask: 0x01)                              */
#define CAN0_TMI2_FT_Pos                  (1UL)                     /*!< FT (Bit 1)                                            */
#define CAN0_TMI2_FT_Msk                  (0x2UL)                   /*!< FT (Bitfield-Mask: 0x01)                              */
#define CAN0_TMI2_TEN_Pos                 (0UL)                     /*!< TEN (Bit 0)                                           */
#define CAN0_TMI2_TEN_Msk                 (0x1UL)                   /*!< TEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  TMP2  ========================================================== */
#define CAN0_TMP2_TS_Pos                  (16UL)                    /*!< TS (Bit 16)                                           */
#define CAN0_TMP2_TS_Msk                  (0xffff0000UL)            /*!< TS (Bitfield-Mask: 0xffff)                            */
#define CAN0_TMP2_TSEN_Pos                (8UL)                     /*!< TSEN (Bit 8)                                          */
#define CAN0_TMP2_TSEN_Msk                (0x100UL)                 /*!< TSEN (Bitfield-Mask: 0x01)                            */
#define CAN0_TMP2_DLENC_Pos               (0UL)                     /*!< DLENC (Bit 0)                                         */
#define CAN0_TMP2_DLENC_Msk               (0xfUL)                   /*!< DLENC (Bitfield-Mask: 0x0f)                           */
/* =======================================================  TMDATA02  ======================================================== */
#define CAN0_TMDATA02_DB3_Pos             (24UL)                    /*!< DB3 (Bit 24)                                          */
#define CAN0_TMDATA02_DB3_Msk             (0xff000000UL)            /*!< DB3 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA02_DB2_Pos             (16UL)                    /*!< DB2 (Bit 16)                                          */
#define CAN0_TMDATA02_DB2_Msk             (0xff0000UL)              /*!< DB2 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA02_DB1_Pos             (8UL)                     /*!< DB1 (Bit 8)                                           */
#define CAN0_TMDATA02_DB1_Msk             (0xff00UL)                /*!< DB1 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA02_DB0_Pos             (0UL)                     /*!< DB0 (Bit 0)                                           */
#define CAN0_TMDATA02_DB0_Msk             (0xffUL)                  /*!< DB0 (Bitfield-Mask: 0xff)                             */
/* =======================================================  TMDATA12  ======================================================== */
#define CAN0_TMDATA12_DB7_Pos             (24UL)                    /*!< DB7 (Bit 24)                                          */
#define CAN0_TMDATA12_DB7_Msk             (0xff000000UL)            /*!< DB7 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA12_DB6_Pos             (16UL)                    /*!< DB6 (Bit 16)                                          */
#define CAN0_TMDATA12_DB6_Msk             (0xff0000UL)              /*!< DB6 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA12_DB5_Pos             (8UL)                     /*!< DB5 (Bit 8)                                           */
#define CAN0_TMDATA12_DB5_Msk             (0xff00UL)                /*!< DB5 (Bitfield-Mask: 0xff)                             */
#define CAN0_TMDATA12_DB4_Pos             (0UL)                     /*!< DB4 (Bit 0)                                           */
#define CAN0_TMDATA12_DB4_Msk             (0xffUL)                  /*!< DB4 (Bitfield-Mask: 0xff)                             */
/* =======================================================  RFIFOMI0  ======================================================== */
#define CAN0_RFIFOMI0_SFID_EFID_Pos       (21UL)                    /*!< SFID_EFID (Bit 21)                                    */
#define CAN0_RFIFOMI0_SFID_EFID_Msk       (0xffe00000UL)            /*!< SFID_EFID (Bitfield-Mask: 0x7ff)                      */
#define CAN0_RFIFOMI0_EFID_Pos            (3UL)                     /*!< EFID (Bit 3)                                          */
#define CAN0_RFIFOMI0_EFID_Msk            (0x1ffff8UL)              /*!< EFID (Bitfield-Mask: 0x3ffff)                         */
#define CAN0_RFIFOMI0_FF_Pos              (2UL)                     /*!< FF (Bit 2)                                            */
#define CAN0_RFIFOMI0_FF_Msk              (0x4UL)                   /*!< FF (Bitfield-Mask: 0x01)                              */
#define CAN0_RFIFOMI0_FT_Pos              (1UL)                     /*!< FT (Bit 1)                                            */
#define CAN0_RFIFOMI0_FT_Msk              (0x2UL)                   /*!< FT (Bitfield-Mask: 0x01)                              */
/* =======================================================  RFIFOMP0  ======================================================== */
#define CAN0_RFIFOMP0_TS_Pos              (16UL)                    /*!< TS (Bit 16)                                           */
#define CAN0_RFIFOMP0_TS_Msk              (0xffff0000UL)            /*!< TS (Bitfield-Mask: 0xffff)                            */
#define CAN0_RFIFOMP0_FI_Pos              (8UL)                     /*!< FI (Bit 8)                                            */
#define CAN0_RFIFOMP0_FI_Msk              (0xff00UL)                /*!< FI (Bitfield-Mask: 0xff)                              */
#define CAN0_RFIFOMP0_DLENC_Pos           (0UL)                     /*!< DLENC (Bit 0)                                         */
#define CAN0_RFIFOMP0_DLENC_Msk           (0xfUL)                   /*!< DLENC (Bitfield-Mask: 0x0f)                           */
/* =====================================================  RFIFOMDATA00  ====================================================== */
#define CAN0_RFIFOMDATA00_DB3_Pos         (24UL)                    /*!< DB3 (Bit 24)                                          */
#define CAN0_RFIFOMDATA00_DB3_Msk         (0xff000000UL)            /*!< DB3 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA00_DB2_Pos         (16UL)                    /*!< DB2 (Bit 16)                                          */
#define CAN0_RFIFOMDATA00_DB2_Msk         (0xff0000UL)              /*!< DB2 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA00_DB1_Pos         (8UL)                     /*!< DB1 (Bit 8)                                           */
#define CAN0_RFIFOMDATA00_DB1_Msk         (0xff00UL)                /*!< DB1 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA00_DB0_Pos         (0UL)                     /*!< DB0 (Bit 0)                                           */
#define CAN0_RFIFOMDATA00_DB0_Msk         (0xffUL)                  /*!< DB0 (Bitfield-Mask: 0xff)                             */
/* =====================================================  RFIFOMDATA10  ====================================================== */
#define CAN0_RFIFOMDATA10_DB7_Pos         (24UL)                    /*!< DB7 (Bit 24)                                          */
#define CAN0_RFIFOMDATA10_DB7_Msk         (0xff000000UL)            /*!< DB7 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA10_DB6_Pos         (16UL)                    /*!< DB6 (Bit 16)                                          */
#define CAN0_RFIFOMDATA10_DB6_Msk         (0xff0000UL)              /*!< DB6 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA10_DB5_Pos         (8UL)                     /*!< DB5 (Bit 8)                                           */
#define CAN0_RFIFOMDATA10_DB5_Msk         (0xff00UL)                /*!< DB5 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA10_DB4_Pos         (0UL)                     /*!< DB4 (Bit 0)                                           */
#define CAN0_RFIFOMDATA10_DB4_Msk         (0xffUL)                  /*!< DB4 (Bitfield-Mask: 0xff)                             */
/* =======================================================  RFIFOMI1  ======================================================== */
#define CAN0_RFIFOMI1_SFID_EFID_Pos       (21UL)                    /*!< SFID_EFID (Bit 21)                                    */
#define CAN0_RFIFOMI1_SFID_EFID_Msk       (0xffe00000UL)            /*!< SFID_EFID (Bitfield-Mask: 0x7ff)                      */
#define CAN0_RFIFOMI1_EFID_Pos            (3UL)                     /*!< EFID (Bit 3)                                          */
#define CAN0_RFIFOMI1_EFID_Msk            (0x1ffff8UL)              /*!< EFID (Bitfield-Mask: 0x3ffff)                         */
#define CAN0_RFIFOMI1_FF_Pos              (2UL)                     /*!< FF (Bit 2)                                            */
#define CAN0_RFIFOMI1_FF_Msk              (0x4UL)                   /*!< FF (Bitfield-Mask: 0x01)                              */
#define CAN0_RFIFOMI1_FT_Pos              (1UL)                     /*!< FT (Bit 1)                                            */
#define CAN0_RFIFOMI1_FT_Msk              (0x2UL)                   /*!< FT (Bitfield-Mask: 0x01)                              */
/* =======================================================  RFIFOMP1  ======================================================== */
#define CAN0_RFIFOMP1_TS_Pos              (16UL)                    /*!< TS (Bit 16)                                           */
#define CAN0_RFIFOMP1_TS_Msk              (0xffff0000UL)            /*!< TS (Bitfield-Mask: 0xffff)                            */
#define CAN0_RFIFOMP1_FI_Pos              (8UL)                     /*!< FI (Bit 8)                                            */
#define CAN0_RFIFOMP1_FI_Msk              (0xff00UL)                /*!< FI (Bitfield-Mask: 0xff)                              */
#define CAN0_RFIFOMP1_DLENC_Pos           (0UL)                     /*!< DLENC (Bit 0)                                         */
#define CAN0_RFIFOMP1_DLENC_Msk           (0xfUL)                   /*!< DLENC (Bitfield-Mask: 0x0f)                           */
/* =====================================================  RFIFOMDATA01  ====================================================== */
#define CAN0_RFIFOMDATA01_DB3_Pos         (24UL)                    /*!< DB3 (Bit 24)                                          */
#define CAN0_RFIFOMDATA01_DB3_Msk         (0xff000000UL)            /*!< DB3 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA01_DB2_Pos         (16UL)                    /*!< DB2 (Bit 16)                                          */
#define CAN0_RFIFOMDATA01_DB2_Msk         (0xff0000UL)              /*!< DB2 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA01_DB1_Pos         (8UL)                     /*!< DB1 (Bit 8)                                           */
#define CAN0_RFIFOMDATA01_DB1_Msk         (0xff00UL)                /*!< DB1 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA01_DB0_Pos         (0UL)                     /*!< DB0 (Bit 0)                                           */
#define CAN0_RFIFOMDATA01_DB0_Msk         (0xffUL)                  /*!< DB0 (Bitfield-Mask: 0xff)                             */
/* =====================================================  RFIFOMDATA11  ====================================================== */
#define CAN0_RFIFOMDATA11_DB7_Pos         (24UL)                    /*!< DB7 (Bit 24)                                          */
#define CAN0_RFIFOMDATA11_DB7_Msk         (0xff000000UL)            /*!< DB7 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA11_DB6_Pos         (16UL)                    /*!< DB6 (Bit 16)                                          */
#define CAN0_RFIFOMDATA11_DB6_Msk         (0xff0000UL)              /*!< DB6 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA11_DB5_Pos         (8UL)                     /*!< DB5 (Bit 8)                                           */
#define CAN0_RFIFOMDATA11_DB5_Msk         (0xff00UL)                /*!< DB5 (Bitfield-Mask: 0xff)                             */
#define CAN0_RFIFOMDATA11_DB4_Pos         (0UL)                     /*!< DB4 (Bit 0)                                           */
#define CAN0_RFIFOMDATA11_DB4_Msk         (0xffUL)                  /*!< DB4 (Bitfield-Mask: 0xff)                             */
/* =========================================================  FCTL  ========================================================== */
#define CAN0_FCTL_HBC1F_Pos               (8UL)                     /*!< HBC1F (Bit 8)                                         */
#define CAN0_FCTL_HBC1F_Msk               (0x3f00UL)                /*!< HBC1F (Bitfield-Mask: 0x3f)                           */
#define CAN0_FCTL_FLD_Pos                 (0UL)                     /*!< FLD (Bit 0)                                           */
#define CAN0_FCTL_FLD_Msk                 (0x1UL)                   /*!< FLD (Bitfield-Mask: 0x01)                             */
/* =========================================================  FMCFG  ========================================================= */
#define CAN0_FMCFG_FMOD27_Pos             (27UL)                    /*!< FMOD27 (Bit 27)                                       */
#define CAN0_FMCFG_FMOD27_Msk             (0x8000000UL)             /*!< FMOD27 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD26_Pos             (26UL)                    /*!< FMOD26 (Bit 26)                                       */
#define CAN0_FMCFG_FMOD26_Msk             (0x4000000UL)             /*!< FMOD26 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD25_Pos             (25UL)                    /*!< FMOD25 (Bit 25)                                       */
#define CAN0_FMCFG_FMOD25_Msk             (0x2000000UL)             /*!< FMOD25 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD24_Pos             (24UL)                    /*!< FMOD24 (Bit 24)                                       */
#define CAN0_FMCFG_FMOD24_Msk             (0x1000000UL)             /*!< FMOD24 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD23_Pos             (23UL)                    /*!< FMOD23 (Bit 23)                                       */
#define CAN0_FMCFG_FMOD23_Msk             (0x800000UL)              /*!< FMOD23 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD22_Pos             (22UL)                    /*!< FMOD22 (Bit 22)                                       */
#define CAN0_FMCFG_FMOD22_Msk             (0x400000UL)              /*!< FMOD22 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD21_Pos             (21UL)                    /*!< FMOD21 (Bit 21)                                       */
#define CAN0_FMCFG_FMOD21_Msk             (0x200000UL)              /*!< FMOD21 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD20_Pos             (20UL)                    /*!< FMOD20 (Bit 20)                                       */
#define CAN0_FMCFG_FMOD20_Msk             (0x100000UL)              /*!< FMOD20 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD19_Pos             (19UL)                    /*!< FMOD19 (Bit 19)                                       */
#define CAN0_FMCFG_FMOD19_Msk             (0x80000UL)               /*!< FMOD19 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD18_Pos             (18UL)                    /*!< FMOD18 (Bit 18)                                       */
#define CAN0_FMCFG_FMOD18_Msk             (0x40000UL)               /*!< FMOD18 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD17_Pos             (17UL)                    /*!< FMOD17 (Bit 17)                                       */
#define CAN0_FMCFG_FMOD17_Msk             (0x20000UL)               /*!< FMOD17 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD16_Pos             (16UL)                    /*!< FMOD16 (Bit 16)                                       */
#define CAN0_FMCFG_FMOD16_Msk             (0x10000UL)               /*!< FMOD16 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD15_Pos             (15UL)                    /*!< FMOD15 (Bit 15)                                       */
#define CAN0_FMCFG_FMOD15_Msk             (0x8000UL)                /*!< FMOD15 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD14_Pos             (14UL)                    /*!< FMOD14 (Bit 14)                                       */
#define CAN0_FMCFG_FMOD14_Msk             (0x4000UL)                /*!< FMOD14 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD13_Pos             (13UL)                    /*!< FMOD13 (Bit 13)                                       */
#define CAN0_FMCFG_FMOD13_Msk             (0x2000UL)                /*!< FMOD13 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD12_Pos             (12UL)                    /*!< FMOD12 (Bit 12)                                       */
#define CAN0_FMCFG_FMOD12_Msk             (0x1000UL)                /*!< FMOD12 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD11_Pos             (11UL)                    /*!< FMOD11 (Bit 11)                                       */
#define CAN0_FMCFG_FMOD11_Msk             (0x800UL)                 /*!< FMOD11 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD10_Pos             (10UL)                    /*!< FMOD10 (Bit 10)                                       */
#define CAN0_FMCFG_FMOD10_Msk             (0x400UL)                 /*!< FMOD10 (Bitfield-Mask: 0x01)                          */
#define CAN0_FMCFG_FMOD9_Pos              (9UL)                     /*!< FMOD9 (Bit 9)                                         */
#define CAN0_FMCFG_FMOD9_Msk              (0x200UL)                 /*!< FMOD9 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD8_Pos              (8UL)                     /*!< FMOD8 (Bit 8)                                         */
#define CAN0_FMCFG_FMOD8_Msk              (0x100UL)                 /*!< FMOD8 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD7_Pos              (7UL)                     /*!< FMOD7 (Bit 7)                                         */
#define CAN0_FMCFG_FMOD7_Msk              (0x80UL)                  /*!< FMOD7 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD6_Pos              (6UL)                     /*!< FMOD6 (Bit 6)                                         */
#define CAN0_FMCFG_FMOD6_Msk              (0x40UL)                  /*!< FMOD6 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD5_Pos              (5UL)                     /*!< FMOD5 (Bit 5)                                         */
#define CAN0_FMCFG_FMOD5_Msk              (0x20UL)                  /*!< FMOD5 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD4_Pos              (4UL)                     /*!< FMOD4 (Bit 4)                                         */
#define CAN0_FMCFG_FMOD4_Msk              (0x10UL)                  /*!< FMOD4 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD3_Pos              (3UL)                     /*!< FMOD3 (Bit 3)                                         */
#define CAN0_FMCFG_FMOD3_Msk              (0x8UL)                   /*!< FMOD3 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD2_Pos              (2UL)                     /*!< FMOD2 (Bit 2)                                         */
#define CAN0_FMCFG_FMOD2_Msk              (0x4UL)                   /*!< FMOD2 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD1_Pos              (1UL)                     /*!< FMOD1 (Bit 1)                                         */
#define CAN0_FMCFG_FMOD1_Msk              (0x2UL)                   /*!< FMOD1 (Bitfield-Mask: 0x01)                           */
#define CAN0_FMCFG_FMOD0_Pos              (0UL)                     /*!< FMOD0 (Bit 0)                                         */
#define CAN0_FMCFG_FMOD0_Msk              (0x1UL)                   /*!< FMOD0 (Bitfield-Mask: 0x01)                           */
/* =========================================================  FSCFG  ========================================================= */
#define CAN0_FSCFG_FS0_Pos                (0UL)                     /*!< FS0 (Bit 0)                                           */
#define CAN0_FSCFG_FS0_Msk                (0x1UL)                   /*!< FS0 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS1_Pos                (1UL)                     /*!< FS1 (Bit 1)                                           */
#define CAN0_FSCFG_FS1_Msk                (0x2UL)                   /*!< FS1 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS2_Pos                (2UL)                     /*!< FS2 (Bit 2)                                           */
#define CAN0_FSCFG_FS2_Msk                (0x4UL)                   /*!< FS2 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS3_Pos                (3UL)                     /*!< FS3 (Bit 3)                                           */
#define CAN0_FSCFG_FS3_Msk                (0x8UL)                   /*!< FS3 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS4_Pos                (4UL)                     /*!< FS4 (Bit 4)                                           */
#define CAN0_FSCFG_FS4_Msk                (0x10UL)                  /*!< FS4 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS5_Pos                (5UL)                     /*!< FS5 (Bit 5)                                           */
#define CAN0_FSCFG_FS5_Msk                (0x20UL)                  /*!< FS5 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS6_Pos                (6UL)                     /*!< FS6 (Bit 6)                                           */
#define CAN0_FSCFG_FS6_Msk                (0x40UL)                  /*!< FS6 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS7_Pos                (7UL)                     /*!< FS7 (Bit 7)                                           */
#define CAN0_FSCFG_FS7_Msk                (0x80UL)                  /*!< FS7 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS8_Pos                (8UL)                     /*!< FS8 (Bit 8)                                           */
#define CAN0_FSCFG_FS8_Msk                (0x100UL)                 /*!< FS8 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS9_Pos                (9UL)                     /*!< FS9 (Bit 9)                                           */
#define CAN0_FSCFG_FS9_Msk                (0x200UL)                 /*!< FS9 (Bitfield-Mask: 0x01)                             */
#define CAN0_FSCFG_FS10_Pos               (10UL)                    /*!< FS10 (Bit 10)                                         */
#define CAN0_FSCFG_FS10_Msk               (0x400UL)                 /*!< FS10 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS11_Pos               (11UL)                    /*!< FS11 (Bit 11)                                         */
#define CAN0_FSCFG_FS11_Msk               (0x800UL)                 /*!< FS11 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS12_Pos               (12UL)                    /*!< FS12 (Bit 12)                                         */
#define CAN0_FSCFG_FS12_Msk               (0x1000UL)                /*!< FS12 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS13_Pos               (13UL)                    /*!< FS13 (Bit 13)                                         */
#define CAN0_FSCFG_FS13_Msk               (0x2000UL)                /*!< FS13 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS14_Pos               (14UL)                    /*!< FS14 (Bit 14)                                         */
#define CAN0_FSCFG_FS14_Msk               (0x4000UL)                /*!< FS14 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS15_Pos               (15UL)                    /*!< FS15 (Bit 15)                                         */
#define CAN0_FSCFG_FS15_Msk               (0x8000UL)                /*!< FS15 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS16_Pos               (16UL)                    /*!< FS16 (Bit 16)                                         */
#define CAN0_FSCFG_FS16_Msk               (0x10000UL)               /*!< FS16 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS17_Pos               (17UL)                    /*!< FS17 (Bit 17)                                         */
#define CAN0_FSCFG_FS17_Msk               (0x20000UL)               /*!< FS17 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS18_Pos               (18UL)                    /*!< FS18 (Bit 18)                                         */
#define CAN0_FSCFG_FS18_Msk               (0x40000UL)               /*!< FS18 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS19_Pos               (19UL)                    /*!< FS19 (Bit 19)                                         */
#define CAN0_FSCFG_FS19_Msk               (0x80000UL)               /*!< FS19 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS20_Pos               (20UL)                    /*!< FS20 (Bit 20)                                         */
#define CAN0_FSCFG_FS20_Msk               (0x100000UL)              /*!< FS20 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS21_Pos               (21UL)                    /*!< FS21 (Bit 21)                                         */
#define CAN0_FSCFG_FS21_Msk               (0x200000UL)              /*!< FS21 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS22_Pos               (22UL)                    /*!< FS22 (Bit 22)                                         */
#define CAN0_FSCFG_FS22_Msk               (0x400000UL)              /*!< FS22 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS23_Pos               (23UL)                    /*!< FS23 (Bit 23)                                         */
#define CAN0_FSCFG_FS23_Msk               (0x800000UL)              /*!< FS23 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS24_Pos               (24UL)                    /*!< FS24 (Bit 24)                                         */
#define CAN0_FSCFG_FS24_Msk               (0x1000000UL)             /*!< FS24 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS25_Pos               (25UL)                    /*!< FS25 (Bit 25)                                         */
#define CAN0_FSCFG_FS25_Msk               (0x2000000UL)             /*!< FS25 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS26_Pos               (26UL)                    /*!< FS26 (Bit 26)                                         */
#define CAN0_FSCFG_FS26_Msk               (0x4000000UL)             /*!< FS26 (Bitfield-Mask: 0x01)                            */
#define CAN0_FSCFG_FS27_Pos               (27UL)                    /*!< FS27 (Bit 27)                                         */
#define CAN0_FSCFG_FS27_Msk               (0x8000000UL)             /*!< FS27 (Bitfield-Mask: 0x01)                            */
/* ========================================================  FAFIFO  ========================================================= */
#define CAN0_FAFIFO_FAF0_Pos              (0UL)                     /*!< FAF0 (Bit 0)                                          */
#define CAN0_FAFIFO_FAF0_Msk              (0x1UL)                   /*!< FAF0 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF1_Pos              (1UL)                     /*!< FAF1 (Bit 1)                                          */
#define CAN0_FAFIFO_FAF1_Msk              (0x2UL)                   /*!< FAF1 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF2_Pos              (2UL)                     /*!< FAF2 (Bit 2)                                          */
#define CAN0_FAFIFO_FAF2_Msk              (0x4UL)                   /*!< FAF2 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF3_Pos              (3UL)                     /*!< FAF3 (Bit 3)                                          */
#define CAN0_FAFIFO_FAF3_Msk              (0x8UL)                   /*!< FAF3 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF4_Pos              (4UL)                     /*!< FAF4 (Bit 4)                                          */
#define CAN0_FAFIFO_FAF4_Msk              (0x10UL)                  /*!< FAF4 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF5_Pos              (5UL)                     /*!< FAF5 (Bit 5)                                          */
#define CAN0_FAFIFO_FAF5_Msk              (0x20UL)                  /*!< FAF5 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF6_Pos              (6UL)                     /*!< FAF6 (Bit 6)                                          */
#define CAN0_FAFIFO_FAF6_Msk              (0x40UL)                  /*!< FAF6 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF7_Pos              (7UL)                     /*!< FAF7 (Bit 7)                                          */
#define CAN0_FAFIFO_FAF7_Msk              (0x80UL)                  /*!< FAF7 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF8_Pos              (8UL)                     /*!< FAF8 (Bit 8)                                          */
#define CAN0_FAFIFO_FAF8_Msk              (0x100UL)                 /*!< FAF8 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF9_Pos              (9UL)                     /*!< FAF9 (Bit 9)                                          */
#define CAN0_FAFIFO_FAF9_Msk              (0x200UL)                 /*!< FAF9 (Bitfield-Mask: 0x01)                            */
#define CAN0_FAFIFO_FAF10_Pos             (10UL)                    /*!< FAF10 (Bit 10)                                        */
#define CAN0_FAFIFO_FAF10_Msk             (0x400UL)                 /*!< FAF10 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF11_Pos             (11UL)                    /*!< FAF11 (Bit 11)                                        */
#define CAN0_FAFIFO_FAF11_Msk             (0x800UL)                 /*!< FAF11 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF12_Pos             (12UL)                    /*!< FAF12 (Bit 12)                                        */
#define CAN0_FAFIFO_FAF12_Msk             (0x1000UL)                /*!< FAF12 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF13_Pos             (13UL)                    /*!< FAF13 (Bit 13)                                        */
#define CAN0_FAFIFO_FAF13_Msk             (0x2000UL)                /*!< FAF13 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF14_Pos             (14UL)                    /*!< FAF14 (Bit 14)                                        */
#define CAN0_FAFIFO_FAF14_Msk             (0x4000UL)                /*!< FAF14 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF15_Pos             (15UL)                    /*!< FAF15 (Bit 15)                                        */
#define CAN0_FAFIFO_FAF15_Msk             (0x8000UL)                /*!< FAF15 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF16_Pos             (16UL)                    /*!< FAF16 (Bit 16)                                        */
#define CAN0_FAFIFO_FAF16_Msk             (0x10000UL)               /*!< FAF16 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF17_Pos             (17UL)                    /*!< FAF17 (Bit 17)                                        */
#define CAN0_FAFIFO_FAF17_Msk             (0x20000UL)               /*!< FAF17 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF18_Pos             (18UL)                    /*!< FAF18 (Bit 18)                                        */
#define CAN0_FAFIFO_FAF18_Msk             (0x40000UL)               /*!< FAF18 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF19_Pos             (19UL)                    /*!< FAF19 (Bit 19)                                        */
#define CAN0_FAFIFO_FAF19_Msk             (0x80000UL)               /*!< FAF19 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF20_Pos             (20UL)                    /*!< FAF20 (Bit 20)                                        */
#define CAN0_FAFIFO_FAF20_Msk             (0x100000UL)              /*!< FAF20 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF21_Pos             (21UL)                    /*!< FAF21 (Bit 21)                                        */
#define CAN0_FAFIFO_FAF21_Msk             (0x200000UL)              /*!< FAF21 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF22_Pos             (22UL)                    /*!< FAF22 (Bit 22)                                        */
#define CAN0_FAFIFO_FAF22_Msk             (0x400000UL)              /*!< FAF22 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF23_Pos             (23UL)                    /*!< FAF23 (Bit 23)                                        */
#define CAN0_FAFIFO_FAF23_Msk             (0x800000UL)              /*!< FAF23 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF24_Pos             (24UL)                    /*!< FAF24 (Bit 24)                                        */
#define CAN0_FAFIFO_FAF24_Msk             (0x1000000UL)             /*!< FAF24 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF25_Pos             (25UL)                    /*!< FAF25 (Bit 25)                                        */
#define CAN0_FAFIFO_FAF25_Msk             (0x2000000UL)             /*!< FAF25 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF26_Pos             (26UL)                    /*!< FAF26 (Bit 26)                                        */
#define CAN0_FAFIFO_FAF26_Msk             (0x4000000UL)             /*!< FAF26 (Bitfield-Mask: 0x01)                           */
#define CAN0_FAFIFO_FAF27_Pos             (27UL)                    /*!< FAF27 (Bit 27)                                        */
#define CAN0_FAFIFO_FAF27_Msk             (0x8000000UL)             /*!< FAF27 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  FW  =========================================================== */
#define CAN0_FW_FW0_Pos                   (0UL)                     /*!< FW0 (Bit 0)                                           */
#define CAN0_FW_FW0_Msk                   (0x1UL)                   /*!< FW0 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW1_Pos                   (1UL)                     /*!< FW1 (Bit 1)                                           */
#define CAN0_FW_FW1_Msk                   (0x2UL)                   /*!< FW1 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW2_Pos                   (2UL)                     /*!< FW2 (Bit 2)                                           */
#define CAN0_FW_FW2_Msk                   (0x4UL)                   /*!< FW2 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW3_Pos                   (3UL)                     /*!< FW3 (Bit 3)                                           */
#define CAN0_FW_FW3_Msk                   (0x8UL)                   /*!< FW3 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW4_Pos                   (4UL)                     /*!< FW4 (Bit 4)                                           */
#define CAN0_FW_FW4_Msk                   (0x10UL)                  /*!< FW4 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW5_Pos                   (5UL)                     /*!< FW5 (Bit 5)                                           */
#define CAN0_FW_FW5_Msk                   (0x20UL)                  /*!< FW5 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW6_Pos                   (6UL)                     /*!< FW6 (Bit 6)                                           */
#define CAN0_FW_FW6_Msk                   (0x40UL)                  /*!< FW6 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW7_Pos                   (7UL)                     /*!< FW7 (Bit 7)                                           */
#define CAN0_FW_FW7_Msk                   (0x80UL)                  /*!< FW7 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW8_Pos                   (8UL)                     /*!< FW8 (Bit 8)                                           */
#define CAN0_FW_FW8_Msk                   (0x100UL)                 /*!< FW8 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW9_Pos                   (9UL)                     /*!< FW9 (Bit 9)                                           */
#define CAN0_FW_FW9_Msk                   (0x200UL)                 /*!< FW9 (Bitfield-Mask: 0x01)                             */
#define CAN0_FW_FW10_Pos                  (10UL)                    /*!< FW10 (Bit 10)                                         */
#define CAN0_FW_FW10_Msk                  (0x400UL)                 /*!< FW10 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW11_Pos                  (11UL)                    /*!< FW11 (Bit 11)                                         */
#define CAN0_FW_FW11_Msk                  (0x800UL)                 /*!< FW11 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW12_Pos                  (12UL)                    /*!< FW12 (Bit 12)                                         */
#define CAN0_FW_FW12_Msk                  (0x1000UL)                /*!< FW12 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW13_Pos                  (13UL)                    /*!< FW13 (Bit 13)                                         */
#define CAN0_FW_FW13_Msk                  (0x2000UL)                /*!< FW13 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW14_Pos                  (14UL)                    /*!< FW14 (Bit 14)                                         */
#define CAN0_FW_FW14_Msk                  (0x4000UL)                /*!< FW14 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW15_Pos                  (15UL)                    /*!< FW15 (Bit 15)                                         */
#define CAN0_FW_FW15_Msk                  (0x8000UL)                /*!< FW15 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW16_Pos                  (16UL)                    /*!< FW16 (Bit 16)                                         */
#define CAN0_FW_FW16_Msk                  (0x10000UL)               /*!< FW16 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW17_Pos                  (17UL)                    /*!< FW17 (Bit 17)                                         */
#define CAN0_FW_FW17_Msk                  (0x20000UL)               /*!< FW17 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW18_Pos                  (18UL)                    /*!< FW18 (Bit 18)                                         */
#define CAN0_FW_FW18_Msk                  (0x40000UL)               /*!< FW18 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW19_Pos                  (19UL)                    /*!< FW19 (Bit 19)                                         */
#define CAN0_FW_FW19_Msk                  (0x80000UL)               /*!< FW19 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW20_Pos                  (20UL)                    /*!< FW20 (Bit 20)                                         */
#define CAN0_FW_FW20_Msk                  (0x100000UL)              /*!< FW20 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW21_Pos                  (21UL)                    /*!< FW21 (Bit 21)                                         */
#define CAN0_FW_FW21_Msk                  (0x200000UL)              /*!< FW21 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW22_Pos                  (22UL)                    /*!< FW22 (Bit 22)                                         */
#define CAN0_FW_FW22_Msk                  (0x400000UL)              /*!< FW22 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW23_Pos                  (23UL)                    /*!< FW23 (Bit 23)                                         */
#define CAN0_FW_FW23_Msk                  (0x800000UL)              /*!< FW23 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW24_Pos                  (24UL)                    /*!< FW24 (Bit 24)                                         */
#define CAN0_FW_FW24_Msk                  (0x1000000UL)             /*!< FW24 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW25_Pos                  (25UL)                    /*!< FW25 (Bit 25)                                         */
#define CAN0_FW_FW25_Msk                  (0x2000000UL)             /*!< FW25 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW26_Pos                  (26UL)                    /*!< FW26 (Bit 26)                                         */
#define CAN0_FW_FW26_Msk                  (0x4000000UL)             /*!< FW26 (Bitfield-Mask: 0x01)                            */
#define CAN0_FW_FW27_Pos                  (27UL)                    /*!< FW27 (Bit 27)                                         */
#define CAN0_FW_FW27_Msk                  (0x8000000UL)             /*!< FW27 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F0DATA0  ======================================================== */
#define CAN0_F0DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F0DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F0DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F0DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F0DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F0DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F0DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F0DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F0DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F0DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F0DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F0DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F0DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F0DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F0DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F0DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F0DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F0DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F0DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F0DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F0DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F0DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F0DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F0DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F0DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F0DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F0DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F0DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F0DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F0DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F0DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F0DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F0DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F0DATA1  ======================================================== */
#define CAN0_F0DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F0DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F0DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F0DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F0DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F0DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F0DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F0DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F0DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F0DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F0DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F0DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F0DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F0DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F0DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F0DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F0DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F0DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F0DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F0DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F0DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F0DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F0DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F0DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F0DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F0DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F0DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F0DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F0DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F0DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F0DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F0DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F0DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F0DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F0DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F1DATA0  ======================================================== */
#define CAN0_F1DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F1DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F1DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F1DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F1DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F1DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F1DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F1DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F1DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F1DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F1DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F1DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F1DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F1DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F1DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F1DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F1DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F1DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F1DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F1DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F1DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F1DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F1DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F1DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F1DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F1DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F1DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F1DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F1DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F1DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F1DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F1DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F1DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F1DATA1  ======================================================== */
#define CAN0_F1DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F1DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F1DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F1DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F1DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F1DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F1DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F1DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F1DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F1DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F1DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F1DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F1DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F1DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F1DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F1DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F1DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F1DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F1DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F1DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F1DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F1DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F1DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F1DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F1DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F1DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F1DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F1DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F1DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F1DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F1DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F1DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F1DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F1DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F1DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F2DATA0  ======================================================== */
#define CAN0_F2DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F2DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F2DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F2DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F2DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F2DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F2DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F2DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F2DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F2DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F2DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F2DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F2DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F2DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F2DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F2DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F2DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F2DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F2DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F2DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F2DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F2DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F2DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F2DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F2DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F2DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F2DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F2DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F2DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F2DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F2DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F2DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F2DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F2DATA1  ======================================================== */
#define CAN0_F2DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F2DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F2DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F2DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F2DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F2DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F2DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F2DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F2DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F2DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F2DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F2DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F2DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F2DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F2DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F2DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F2DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F2DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F2DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F2DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F2DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F2DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F2DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F2DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F2DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F2DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F2DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F2DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F2DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F2DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F2DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F2DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F2DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F2DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F2DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F3DATA0  ======================================================== */
#define CAN0_F3DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F3DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F3DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F3DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F3DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F3DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F3DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F3DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F3DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F3DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F3DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F3DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F3DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F3DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F3DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F3DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F3DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F3DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F3DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F3DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F3DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F3DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F3DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F3DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F3DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F3DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F3DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F3DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F3DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F3DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F3DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F3DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F3DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F3DATA1  ======================================================== */
#define CAN0_F3DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F3DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F3DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F3DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F3DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F3DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F3DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F3DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F3DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F3DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F3DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F3DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F3DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F3DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F3DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F3DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F3DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F3DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F3DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F3DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F3DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F3DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F3DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F3DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F3DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F3DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F3DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F3DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F3DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F3DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F3DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F3DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F3DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F3DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F3DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F4DATA0  ======================================================== */
#define CAN0_F4DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F4DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F4DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F4DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F4DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F4DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F4DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F4DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F4DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F4DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F4DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F4DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F4DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F4DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F4DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F4DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F4DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F4DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F4DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F4DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F4DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F4DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F4DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F4DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F4DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F4DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F4DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F4DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F4DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F4DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F4DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F4DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F4DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F4DATA1  ======================================================== */
#define CAN0_F4DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F4DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F4DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F4DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F4DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F4DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F4DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F4DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F4DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F4DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F4DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F4DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F4DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F4DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F4DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F4DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F4DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F4DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F4DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F4DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F4DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F4DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F4DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F4DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F4DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F4DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F4DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F4DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F4DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F4DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F4DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F4DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F4DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F4DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F4DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F5DATA0  ======================================================== */
#define CAN0_F5DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F5DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F5DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F5DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F5DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F5DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F5DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F5DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F5DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F5DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F5DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F5DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F5DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F5DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F5DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F5DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F5DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F5DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F5DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F5DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F5DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F5DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F5DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F5DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F5DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F5DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F5DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F5DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F5DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F5DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F5DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F5DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F5DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F5DATA1  ======================================================== */
#define CAN0_F5DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F5DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F5DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F5DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F5DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F5DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F5DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F5DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F5DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F5DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F5DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F5DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F5DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F5DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F5DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F5DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F5DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F5DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F5DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F5DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F5DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F5DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F5DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F5DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F5DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F5DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F5DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F5DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F5DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F5DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F5DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F5DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F5DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F5DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F5DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F6DATA0  ======================================================== */
#define CAN0_F6DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F6DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F6DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F6DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F6DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F6DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F6DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F6DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F6DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F6DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F6DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F6DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F6DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F6DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F6DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F6DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F6DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F6DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F6DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F6DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F6DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F6DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F6DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F6DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F6DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F6DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F6DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F6DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F6DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F6DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F6DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F6DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F6DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F6DATA1  ======================================================== */
#define CAN0_F6DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F6DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F6DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F6DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F6DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F6DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F6DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F6DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F6DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F6DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F6DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F6DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F6DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F6DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F6DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F6DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F6DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F6DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F6DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F6DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F6DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F6DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F6DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F6DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F6DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F6DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F6DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F6DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F6DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F6DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F6DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F6DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F6DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F6DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F6DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F7DATA0  ======================================================== */
#define CAN0_F7DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F7DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F7DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F7DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F7DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F7DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F7DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F7DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F7DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F7DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F7DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F7DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F7DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F7DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F7DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F7DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F7DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F7DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F7DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F7DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F7DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F7DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F7DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F7DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F7DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F7DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F7DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F7DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F7DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F7DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F7DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F7DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F7DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F7DATA1  ======================================================== */
#define CAN0_F7DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F7DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F7DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F7DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F7DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F7DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F7DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F7DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F7DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F7DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F7DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F7DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F7DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F7DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F7DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F7DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F7DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F7DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F7DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F7DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F7DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F7DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F7DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F7DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F7DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F7DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F7DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F7DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F7DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F7DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F7DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F7DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F7DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F7DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F7DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F8DATA0  ======================================================== */
#define CAN0_F8DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F8DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F8DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F8DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F8DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F8DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F8DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F8DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F8DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F8DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F8DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F8DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F8DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F8DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F8DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F8DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F8DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F8DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F8DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F8DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F8DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F8DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F8DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F8DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F8DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F8DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F8DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F8DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F8DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F8DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F8DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F8DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F8DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F8DATA1  ======================================================== */
#define CAN0_F8DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F8DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F8DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F8DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F8DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F8DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F8DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F8DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F8DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F8DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F8DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F8DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F8DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F8DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F8DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F8DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F8DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F8DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F8DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F8DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F8DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F8DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F8DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F8DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F8DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F8DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F8DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F8DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F8DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F8DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F8DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F8DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F8DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F8DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F8DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F9DATA0  ======================================================== */
#define CAN0_F9DATA0_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F9DATA0_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F9DATA0_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F9DATA0_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F9DATA0_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F9DATA0_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F9DATA0_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F9DATA0_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F9DATA0_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F9DATA0_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F9DATA0_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA0_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F9DATA0_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F9DATA0_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F9DATA0_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F9DATA0_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F9DATA0_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F9DATA0_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F9DATA0_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F9DATA0_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F9DATA0_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F9DATA0_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F9DATA0_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F9DATA0_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F9DATA0_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F9DATA0_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F9DATA0_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F9DATA0_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F9DATA0_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F9DATA0_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F9DATA0_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F9DATA0_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F9DATA0_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA0_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F9DATA0_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* ========================================================  F9DATA1  ======================================================== */
#define CAN0_F9DATA1_FD0_Pos              (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F9DATA1_FD0_Msk              (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD1_Pos              (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F9DATA1_FD1_Msk              (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD2_Pos              (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F9DATA1_FD2_Msk              (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD3_Pos              (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F9DATA1_FD3_Msk              (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD4_Pos              (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F9DATA1_FD4_Msk              (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD5_Pos              (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F9DATA1_FD5_Msk              (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD6_Pos              (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F9DATA1_FD6_Msk              (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD7_Pos              (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F9DATA1_FD7_Msk              (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD8_Pos              (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F9DATA1_FD8_Msk              (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD9_Pos              (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F9DATA1_FD9_Msk              (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F9DATA1_FD10_Pos             (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F9DATA1_FD10_Msk             (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD11_Pos             (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F9DATA1_FD11_Msk             (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD12_Pos             (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F9DATA1_FD12_Msk             (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD13_Pos             (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F9DATA1_FD13_Msk             (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD14_Pos             (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F9DATA1_FD14_Msk             (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD15_Pos             (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F9DATA1_FD15_Msk             (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD16_Pos             (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F9DATA1_FD16_Msk             (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD17_Pos             (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F9DATA1_FD17_Msk             (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD18_Pos             (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F9DATA1_FD18_Msk             (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD19_Pos             (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F9DATA1_FD19_Msk             (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD20_Pos             (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F9DATA1_FD20_Msk             (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD21_Pos             (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F9DATA1_FD21_Msk             (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD22_Pos             (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F9DATA1_FD22_Msk             (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD23_Pos             (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F9DATA1_FD23_Msk             (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD24_Pos             (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F9DATA1_FD24_Msk             (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD25_Pos             (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F9DATA1_FD25_Msk             (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD26_Pos             (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F9DATA1_FD26_Msk             (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD27_Pos             (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F9DATA1_FD27_Msk             (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD28_Pos             (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F9DATA1_FD28_Msk             (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD29_Pos             (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F9DATA1_FD29_Msk             (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD30_Pos             (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F9DATA1_FD30_Msk             (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F9DATA1_FD31_Pos             (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F9DATA1_FD31_Msk             (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F10DATA0  ======================================================== */
#define CAN0_F10DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F10DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F10DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F10DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F10DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F10DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F10DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F10DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F10DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F10DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F10DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F10DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F10DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F10DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F10DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F10DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F10DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F10DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F10DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F10DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F10DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F10DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F10DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F10DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F10DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F10DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F10DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F10DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F10DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F10DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F10DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F10DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F10DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F10DATA1  ======================================================== */
#define CAN0_F10DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F10DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F10DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F10DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F10DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F10DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F10DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F10DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F10DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F10DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F10DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F10DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F10DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F10DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F10DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F10DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F10DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F10DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F10DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F10DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F10DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F10DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F10DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F10DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F10DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F10DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F10DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F10DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F10DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F10DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F10DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F10DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F10DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F10DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F10DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F11DATA0  ======================================================== */
#define CAN0_F11DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F11DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F11DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F11DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F11DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F11DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F11DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F11DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F11DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F11DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F11DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F11DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F11DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F11DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F11DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F11DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F11DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F11DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F11DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F11DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F11DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F11DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F11DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F11DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F11DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F11DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F11DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F11DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F11DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F11DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F11DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F11DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F11DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F11DATA1  ======================================================== */
#define CAN0_F11DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F11DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F11DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F11DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F11DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F11DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F11DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F11DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F11DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F11DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F11DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F11DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F11DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F11DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F11DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F11DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F11DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F11DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F11DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F11DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F11DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F11DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F11DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F11DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F11DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F11DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F11DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F11DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F11DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F11DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F11DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F11DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F11DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F11DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F11DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F12DATA0  ======================================================== */
#define CAN0_F12DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F12DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F12DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F12DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F12DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F12DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F12DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F12DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F12DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F12DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F12DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F12DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F12DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F12DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F12DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F12DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F12DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F12DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F12DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F12DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F12DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F12DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F12DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F12DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F12DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F12DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F12DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F12DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F12DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F12DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F12DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F12DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F12DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F12DATA1  ======================================================== */
#define CAN0_F12DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F12DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F12DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F12DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F12DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F12DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F12DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F12DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F12DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F12DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F12DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F12DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F12DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F12DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F12DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F12DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F12DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F12DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F12DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F12DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F12DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F12DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F12DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F12DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F12DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F12DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F12DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F12DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F12DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F12DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F12DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F12DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F12DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F12DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F12DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F13DATA0  ======================================================== */
#define CAN0_F13DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F13DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F13DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F13DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F13DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F13DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F13DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F13DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F13DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F13DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F13DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F13DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F13DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F13DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F13DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F13DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F13DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F13DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F13DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F13DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F13DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F13DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F13DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F13DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F13DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F13DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F13DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F13DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F13DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F13DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F13DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F13DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F13DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F13DATA1  ======================================================== */
#define CAN0_F13DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F13DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F13DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F13DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F13DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F13DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F13DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F13DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F13DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F13DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F13DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F13DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F13DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F13DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F13DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F13DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F13DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F13DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F13DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F13DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F13DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F13DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F13DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F13DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F13DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F13DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F13DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F13DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F13DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F13DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F13DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F13DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F13DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F13DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F13DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F14DATA0  ======================================================== */
#define CAN0_F14DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F14DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F14DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F14DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F14DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F14DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F14DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F14DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F14DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F14DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F14DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F14DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F14DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F14DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F14DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F14DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F14DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F14DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F14DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F14DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F14DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F14DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F14DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F14DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F14DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F14DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F14DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F14DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F14DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F14DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F14DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F14DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F14DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F14DATA1  ======================================================== */
#define CAN0_F14DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F14DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F14DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F14DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F14DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F14DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F14DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F14DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F14DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F14DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F14DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F14DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F14DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F14DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F14DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F14DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F14DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F14DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F14DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F14DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F14DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F14DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F14DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F14DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F14DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F14DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F14DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F14DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F14DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F14DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F14DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F14DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F14DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F14DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F14DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F15DATA0  ======================================================== */
#define CAN0_F15DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F15DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F15DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F15DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F15DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F15DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F15DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F15DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F15DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F15DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F15DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F15DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F15DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F15DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F15DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F15DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F15DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F15DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F15DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F15DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F15DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F15DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F15DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F15DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F15DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F15DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F15DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F15DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F15DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F15DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F15DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F15DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F15DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F15DATA1  ======================================================== */
#define CAN0_F15DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F15DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F15DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F15DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F15DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F15DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F15DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F15DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F15DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F15DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F15DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F15DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F15DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F15DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F15DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F15DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F15DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F15DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F15DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F15DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F15DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F15DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F15DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F15DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F15DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F15DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F15DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F15DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F15DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F15DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F15DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F15DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F15DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F15DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F15DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F16DATA0  ======================================================== */
#define CAN0_F16DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F16DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F16DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F16DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F16DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F16DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F16DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F16DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F16DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F16DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F16DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F16DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F16DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F16DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F16DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F16DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F16DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F16DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F16DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F16DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F16DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F16DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F16DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F16DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F16DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F16DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F16DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F16DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F16DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F16DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F16DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F16DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F16DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F16DATA1  ======================================================== */
#define CAN0_F16DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F16DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F16DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F16DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F16DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F16DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F16DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F16DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F16DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F16DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F16DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F16DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F16DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F16DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F16DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F16DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F16DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F16DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F16DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F16DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F16DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F16DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F16DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F16DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F16DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F16DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F16DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F16DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F16DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F16DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F16DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F16DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F16DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F16DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F16DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F17DATA0  ======================================================== */
#define CAN0_F17DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F17DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F17DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F17DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F17DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F17DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F17DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F17DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F17DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F17DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F17DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F17DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F17DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F17DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F17DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F17DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F17DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F17DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F17DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F17DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F17DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F17DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F17DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F17DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F17DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F17DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F17DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F17DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F17DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F17DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F17DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F17DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F17DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F17DATA1  ======================================================== */
#define CAN0_F17DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F17DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F17DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F17DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F17DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F17DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F17DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F17DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F17DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F17DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F17DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F17DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F17DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F17DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F17DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F17DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F17DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F17DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F17DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F17DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F17DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F17DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F17DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F17DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F17DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F17DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F17DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F17DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F17DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F17DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F17DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F17DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F17DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F17DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F17DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F18DATA0  ======================================================== */
#define CAN0_F18DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F18DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F18DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F18DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F18DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F18DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F18DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F18DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F18DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F18DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F18DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F18DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F18DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F18DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F18DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F18DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F18DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F18DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F18DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F18DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F18DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F18DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F18DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F18DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F18DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F18DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F18DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F18DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F18DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F18DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F18DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F18DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F18DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F18DATA1  ======================================================== */
#define CAN0_F18DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F18DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F18DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F18DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F18DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F18DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F18DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F18DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F18DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F18DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F18DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F18DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F18DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F18DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F18DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F18DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F18DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F18DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F18DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F18DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F18DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F18DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F18DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F18DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F18DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F18DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F18DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F18DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F18DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F18DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F18DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F18DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F18DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F18DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F18DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F19DATA0  ======================================================== */
#define CAN0_F19DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F19DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F19DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F19DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F19DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F19DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F19DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F19DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F19DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F19DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F19DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F19DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F19DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F19DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F19DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F19DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F19DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F19DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F19DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F19DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F19DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F19DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F19DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F19DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F19DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F19DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F19DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F19DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F19DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F19DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F19DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F19DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F19DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F19DATA1  ======================================================== */
#define CAN0_F19DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F19DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F19DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F19DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F19DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F19DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F19DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F19DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F19DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F19DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F19DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F19DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F19DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F19DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F19DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F19DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F19DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F19DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F19DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F19DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F19DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F19DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F19DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F19DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F19DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F19DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F19DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F19DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F19DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F19DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F19DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F19DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F19DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F19DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F19DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F20DATA0  ======================================================== */
#define CAN0_F20DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F20DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F20DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F20DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F20DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F20DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F20DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F20DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F20DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F20DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F20DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F20DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F20DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F20DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F20DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F20DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F20DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F20DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F20DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F20DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F20DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F20DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F20DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F20DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F20DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F20DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F20DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F20DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F20DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F20DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F20DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F20DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F20DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F20DATA1  ======================================================== */
#define CAN0_F20DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F20DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F20DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F20DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F20DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F20DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F20DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F20DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F20DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F20DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F20DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F20DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F20DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F20DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F20DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F20DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F20DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F20DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F20DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F20DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F20DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F20DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F20DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F20DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F20DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F20DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F20DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F20DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F20DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F20DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F20DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F20DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F20DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F20DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F20DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F21DATA0  ======================================================== */
#define CAN0_F21DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F21DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F21DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F21DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F21DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F21DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F21DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F21DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F21DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F21DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F21DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F21DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F21DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F21DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F21DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F21DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F21DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F21DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F21DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F21DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F21DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F21DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F21DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F21DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F21DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F21DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F21DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F21DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F21DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F21DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F21DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F21DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F21DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F21DATA1  ======================================================== */
#define CAN0_F21DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F21DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F21DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F21DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F21DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F21DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F21DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F21DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F21DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F21DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F21DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F21DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F21DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F21DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F21DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F21DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F21DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F21DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F21DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F21DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F21DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F21DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F21DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F21DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F21DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F21DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F21DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F21DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F21DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F21DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F21DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F21DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F21DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F21DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F21DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F22DATA0  ======================================================== */
#define CAN0_F22DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F22DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F22DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F22DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F22DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F22DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F22DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F22DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F22DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F22DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F22DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F22DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F22DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F22DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F22DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F22DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F22DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F22DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F22DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F22DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F22DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F22DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F22DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F22DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F22DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F22DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F22DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F22DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F22DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F22DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F22DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F22DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F22DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F22DATA1  ======================================================== */
#define CAN0_F22DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F22DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F22DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F22DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F22DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F22DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F22DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F22DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F22DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F22DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F22DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F22DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F22DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F22DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F22DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F22DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F22DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F22DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F22DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F22DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F22DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F22DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F22DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F22DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F22DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F22DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F22DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F22DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F22DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F22DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F22DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F22DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F22DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F22DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F22DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F23DATA0  ======================================================== */
#define CAN0_F23DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F23DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F23DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F23DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F23DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F23DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F23DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F23DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F23DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F23DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F23DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F23DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F23DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F23DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F23DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F23DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F23DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F23DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F23DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F23DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F23DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F23DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F23DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F23DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F23DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F23DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F23DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F23DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F23DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F23DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F23DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F23DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F23DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F23DATA1  ======================================================== */
#define CAN0_F23DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F23DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F23DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F23DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F23DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F23DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F23DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F23DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F23DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F23DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F23DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F23DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F23DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F23DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F23DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F23DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F23DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F23DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F23DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F23DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F23DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F23DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F23DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F23DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F23DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F23DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F23DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F23DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F23DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F23DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F23DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F23DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F23DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F23DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F23DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F24DATA0  ======================================================== */
#define CAN0_F24DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F24DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F24DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F24DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F24DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F24DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F24DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F24DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F24DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F24DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F24DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F24DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F24DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F24DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F24DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F24DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F24DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F24DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F24DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F24DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F24DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F24DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F24DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F24DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F24DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F24DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F24DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F24DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F24DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F24DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F24DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F24DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F24DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F24DATA1  ======================================================== */
#define CAN0_F24DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F24DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F24DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F24DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F24DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F24DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F24DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F24DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F24DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F24DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F24DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F24DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F24DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F24DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F24DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F24DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F24DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F24DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F24DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F24DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F24DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F24DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F24DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F24DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F24DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F24DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F24DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F24DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F24DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F24DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F24DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F24DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F24DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F24DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F24DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F25DATA0  ======================================================== */
#define CAN0_F25DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F25DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F25DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F25DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F25DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F25DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F25DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F25DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F25DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F25DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F25DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F25DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F25DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F25DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F25DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F25DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F25DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F25DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F25DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F25DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F25DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F25DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F25DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F25DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F25DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F25DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F25DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F25DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F25DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F25DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F25DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F25DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F25DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F25DATA1  ======================================================== */
#define CAN0_F25DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F25DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F25DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F25DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F25DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F25DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F25DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F25DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F25DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F25DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F25DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F25DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F25DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F25DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F25DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F25DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F25DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F25DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F25DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F25DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F25DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F25DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F25DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F25DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F25DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F25DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F25DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F25DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F25DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F25DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F25DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F25DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F25DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F25DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F25DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F26DATA0  ======================================================== */
#define CAN0_F26DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F26DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F26DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F26DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F26DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F26DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F26DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F26DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F26DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F26DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F26DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F26DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F26DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F26DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F26DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F26DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F26DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F26DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F26DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F26DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F26DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F26DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F26DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F26DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F26DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F26DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F26DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F26DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F26DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F26DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F26DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F26DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F26DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F26DATA1  ======================================================== */
#define CAN0_F26DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F26DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F26DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F26DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F26DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F26DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F26DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F26DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F26DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F26DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F26DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F26DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F26DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F26DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F26DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F26DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F26DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F26DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F26DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F26DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F26DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F26DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F26DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F26DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F26DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F26DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F26DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F26DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F26DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F26DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F26DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F26DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F26DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F26DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F26DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F27DATA0  ======================================================== */
#define CAN0_F27DATA0_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F27DATA0_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F27DATA0_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F27DATA0_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F27DATA0_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F27DATA0_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F27DATA0_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F27DATA0_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F27DATA0_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F27DATA0_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F27DATA0_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA0_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F27DATA0_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F27DATA0_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F27DATA0_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F27DATA0_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F27DATA0_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F27DATA0_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F27DATA0_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F27DATA0_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F27DATA0_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F27DATA0_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F27DATA0_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F27DATA0_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F27DATA0_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F27DATA0_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F27DATA0_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F27DATA0_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F27DATA0_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F27DATA0_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F27DATA0_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F27DATA0_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F27DATA0_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA0_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F27DATA0_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */
/* =======================================================  F27DATA1  ======================================================== */
#define CAN0_F27DATA1_FD0_Pos             (0UL)                     /*!< FD0 (Bit 0)                                           */
#define CAN0_F27DATA1_FD0_Msk             (0x1UL)                   /*!< FD0 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD1_Pos             (1UL)                     /*!< FD1 (Bit 1)                                           */
#define CAN0_F27DATA1_FD1_Msk             (0x2UL)                   /*!< FD1 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD2_Pos             (2UL)                     /*!< FD2 (Bit 2)                                           */
#define CAN0_F27DATA1_FD2_Msk             (0x4UL)                   /*!< FD2 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD3_Pos             (3UL)                     /*!< FD3 (Bit 3)                                           */
#define CAN0_F27DATA1_FD3_Msk             (0x8UL)                   /*!< FD3 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD4_Pos             (4UL)                     /*!< FD4 (Bit 4)                                           */
#define CAN0_F27DATA1_FD4_Msk             (0x10UL)                  /*!< FD4 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD5_Pos             (5UL)                     /*!< FD5 (Bit 5)                                           */
#define CAN0_F27DATA1_FD5_Msk             (0x20UL)                  /*!< FD5 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD6_Pos             (6UL)                     /*!< FD6 (Bit 6)                                           */
#define CAN0_F27DATA1_FD6_Msk             (0x40UL)                  /*!< FD6 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD7_Pos             (7UL)                     /*!< FD7 (Bit 7)                                           */
#define CAN0_F27DATA1_FD7_Msk             (0x80UL)                  /*!< FD7 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD8_Pos             (8UL)                     /*!< FD8 (Bit 8)                                           */
#define CAN0_F27DATA1_FD8_Msk             (0x100UL)                 /*!< FD8 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD9_Pos             (9UL)                     /*!< FD9 (Bit 9)                                           */
#define CAN0_F27DATA1_FD9_Msk             (0x200UL)                 /*!< FD9 (Bitfield-Mask: 0x01)                             */
#define CAN0_F27DATA1_FD10_Pos            (10UL)                    /*!< FD10 (Bit 10)                                         */
#define CAN0_F27DATA1_FD10_Msk            (0x400UL)                 /*!< FD10 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD11_Pos            (11UL)                    /*!< FD11 (Bit 11)                                         */
#define CAN0_F27DATA1_FD11_Msk            (0x800UL)                 /*!< FD11 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD12_Pos            (12UL)                    /*!< FD12 (Bit 12)                                         */
#define CAN0_F27DATA1_FD12_Msk            (0x1000UL)                /*!< FD12 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD13_Pos            (13UL)                    /*!< FD13 (Bit 13)                                         */
#define CAN0_F27DATA1_FD13_Msk            (0x2000UL)                /*!< FD13 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD14_Pos            (14UL)                    /*!< FD14 (Bit 14)                                         */
#define CAN0_F27DATA1_FD14_Msk            (0x4000UL)                /*!< FD14 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD15_Pos            (15UL)                    /*!< FD15 (Bit 15)                                         */
#define CAN0_F27DATA1_FD15_Msk            (0x8000UL)                /*!< FD15 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD16_Pos            (16UL)                    /*!< FD16 (Bit 16)                                         */
#define CAN0_F27DATA1_FD16_Msk            (0x10000UL)               /*!< FD16 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD17_Pos            (17UL)                    /*!< FD17 (Bit 17)                                         */
#define CAN0_F27DATA1_FD17_Msk            (0x20000UL)               /*!< FD17 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD18_Pos            (18UL)                    /*!< FD18 (Bit 18)                                         */
#define CAN0_F27DATA1_FD18_Msk            (0x40000UL)               /*!< FD18 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD19_Pos            (19UL)                    /*!< FD19 (Bit 19)                                         */
#define CAN0_F27DATA1_FD19_Msk            (0x80000UL)               /*!< FD19 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD20_Pos            (20UL)                    /*!< FD20 (Bit 20)                                         */
#define CAN0_F27DATA1_FD20_Msk            (0x100000UL)              /*!< FD20 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD21_Pos            (21UL)                    /*!< FD21 (Bit 21)                                         */
#define CAN0_F27DATA1_FD21_Msk            (0x200000UL)              /*!< FD21 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD22_Pos            (22UL)                    /*!< FD22 (Bit 22)                                         */
#define CAN0_F27DATA1_FD22_Msk            (0x400000UL)              /*!< FD22 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD23_Pos            (23UL)                    /*!< FD23 (Bit 23)                                         */
#define CAN0_F27DATA1_FD23_Msk            (0x800000UL)              /*!< FD23 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD24_Pos            (24UL)                    /*!< FD24 (Bit 24)                                         */
#define CAN0_F27DATA1_FD24_Msk            (0x1000000UL)             /*!< FD24 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD25_Pos            (25UL)                    /*!< FD25 (Bit 25)                                         */
#define CAN0_F27DATA1_FD25_Msk            (0x2000000UL)             /*!< FD25 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD26_Pos            (26UL)                    /*!< FD26 (Bit 26)                                         */
#define CAN0_F27DATA1_FD26_Msk            (0x4000000UL)             /*!< FD26 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD27_Pos            (27UL)                    /*!< FD27 (Bit 27)                                         */
#define CAN0_F27DATA1_FD27_Msk            (0x8000000UL)             /*!< FD27 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD28_Pos            (28UL)                    /*!< FD28 (Bit 28)                                         */
#define CAN0_F27DATA1_FD28_Msk            (0x10000000UL)            /*!< FD28 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD29_Pos            (29UL)                    /*!< FD29 (Bit 29)                                         */
#define CAN0_F27DATA1_FD29_Msk            (0x20000000UL)            /*!< FD29 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD30_Pos            (30UL)                    /*!< FD30 (Bit 30)                                         */
#define CAN0_F27DATA1_FD30_Msk            (0x40000000UL)            /*!< FD30 (Bitfield-Mask: 0x01)                            */
#define CAN0_F27DATA1_FD31_Pos            (31UL)                    /*!< FD31 (Bit 31)                                         */
#define CAN0_F27DATA1_FD31_Msk            (0x80000000UL)            /*!< FD31 (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  DATA  ========================================================== */
#define CRC_DATA_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRC_DATA_DATA_Msk                 (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  FDATA  ========================================================= */
#define CRC_FDATA_FDATA_Pos               (0UL)                     /*!< FDATA (Bit 0)                                         */
#define CRC_FDATA_FDATA_Msk               (0xffUL)                  /*!< FDATA (Bitfield-Mask: 0xff)                           */
/* ==========================================================  CTL  ========================================================== */
#define CRC_CTL_RST_Pos                   (0UL)                     /*!< RST (Bit 0)                                           */
#define CRC_CTL_RST_Msk                   (0x1UL)                   /*!< RST (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            DAC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CTL  ========================================================== */
#define DAC_CTL_DEN0_Pos                  (0UL)                     /*!< DEN0 (Bit 0)                                          */
#define DAC_CTL_DEN0_Msk                  (0x1UL)                   /*!< DEN0 (Bitfield-Mask: 0x01)                            */
#define DAC_CTL_DBOFF0_Pos                (1UL)                     /*!< DBOFF0 (Bit 1)                                        */
#define DAC_CTL_DBOFF0_Msk                (0x2UL)                   /*!< DBOFF0 (Bitfield-Mask: 0x01)                          */
#define DAC_CTL_DTEN0_Pos                 (2UL)                     /*!< DTEN0 (Bit 2)                                         */
#define DAC_CTL_DTEN0_Msk                 (0x4UL)                   /*!< DTEN0 (Bitfield-Mask: 0x01)                           */
#define DAC_CTL_DTSEL0_Pos                (3UL)                     /*!< DTSEL0 (Bit 3)                                        */
#define DAC_CTL_DTSEL0_Msk                (0x38UL)                  /*!< DTSEL0 (Bitfield-Mask: 0x07)                          */
#define DAC_CTL_DWM0_Pos                  (6UL)                     /*!< DWM0 (Bit 6)                                          */
#define DAC_CTL_DWM0_Msk                  (0xc0UL)                  /*!< DWM0 (Bitfield-Mask: 0x03)                            */
#define DAC_CTL_DWBW0_Pos                 (8UL)                     /*!< DWBW0 (Bit 8)                                         */
#define DAC_CTL_DWBW0_Msk                 (0xf00UL)                 /*!< DWBW0 (Bitfield-Mask: 0x0f)                           */
#define DAC_CTL_DDMAEN0_Pos               (12UL)                    /*!< DDMAEN0 (Bit 12)                                      */
#define DAC_CTL_DDMAEN0_Msk               (0x1000UL)                /*!< DDMAEN0 (Bitfield-Mask: 0x01)                         */
#define DAC_CTL_DEN1_Pos                  (16UL)                    /*!< DEN1 (Bit 16)                                         */
#define DAC_CTL_DEN1_Msk                  (0x10000UL)               /*!< DEN1 (Bitfield-Mask: 0x01)                            */
#define DAC_CTL_DBOFF1_Pos                (17UL)                    /*!< DBOFF1 (Bit 17)                                       */
#define DAC_CTL_DBOFF1_Msk                (0x20000UL)               /*!< DBOFF1 (Bitfield-Mask: 0x01)                          */
#define DAC_CTL_DTEN1_Pos                 (18UL)                    /*!< DTEN1 (Bit 18)                                        */
#define DAC_CTL_DTEN1_Msk                 (0x40000UL)               /*!< DTEN1 (Bitfield-Mask: 0x01)                           */
#define DAC_CTL_DTSEL1_Pos                (19UL)                    /*!< DTSEL1 (Bit 19)                                       */
#define DAC_CTL_DTSEL1_Msk                (0x380000UL)              /*!< DTSEL1 (Bitfield-Mask: 0x07)                          */
#define DAC_CTL_DWM1_Pos                  (22UL)                    /*!< DWM1 (Bit 22)                                         */
#define DAC_CTL_DWM1_Msk                  (0xc00000UL)              /*!< DWM1 (Bitfield-Mask: 0x03)                            */
#define DAC_CTL_DWBW1_Pos                 (24UL)                    /*!< DWBW1 (Bit 24)                                        */
#define DAC_CTL_DWBW1_Msk                 (0xf000000UL)             /*!< DWBW1 (Bitfield-Mask: 0x0f)                           */
#define DAC_CTL_DDMAEN1_Pos               (28UL)                    /*!< DDMAEN1 (Bit 28)                                      */
#define DAC_CTL_DDMAEN1_Msk               (0x10000000UL)            /*!< DDMAEN1 (Bitfield-Mask: 0x01)                         */
/* ==========================================================  SWT  ========================================================== */
#define DAC_SWT_SWTR0_Pos                 (0UL)                     /*!< SWTR0 (Bit 0)                                         */
#define DAC_SWT_SWTR0_Msk                 (0x1UL)                   /*!< SWTR0 (Bitfield-Mask: 0x01)                           */
#define DAC_SWT_SWTR1_Pos                 (1UL)                     /*!< SWTR1 (Bit 1)                                         */
#define DAC_SWT_SWTR1_Msk                 (0x2UL)                   /*!< SWTR1 (Bitfield-Mask: 0x01)                           */
/* ======================================================  DAC0_R12DH  ======================================================= */
#define DAC_DAC0_R12DH_DAC0_DH_Pos        (0UL)                     /*!< DAC0_DH (Bit 0)                                       */
#define DAC_DAC0_R12DH_DAC0_DH_Msk        (0xfffUL)                 /*!< DAC0_DH (Bitfield-Mask: 0xfff)                        */
/* ======================================================  DAC0_L12DH  ======================================================= */
#define DAC_DAC0_L12DH_DAC0_DH_Pos        (4UL)                     /*!< DAC0_DH (Bit 4)                                       */
#define DAC_DAC0_L12DH_DAC0_DH_Msk        (0xfff0UL)                /*!< DAC0_DH (Bitfield-Mask: 0xfff)                        */
/* =======================================================  DAC0_R8DH  ======================================================= */
#define DAC_DAC0_R8DH_DAC0_DH_Pos         (0UL)                     /*!< DAC0_DH (Bit 0)                                       */
#define DAC_DAC0_R8DH_DAC0_DH_Msk         (0xffUL)                  /*!< DAC0_DH (Bitfield-Mask: 0xff)                         */
/* ======================================================  DAC1_R12DH  ======================================================= */
#define DAC_DAC1_R12DH_DAC1_DH_Pos        (0UL)                     /*!< DAC1_DH (Bit 0)                                       */
#define DAC_DAC1_R12DH_DAC1_DH_Msk        (0xfffUL)                 /*!< DAC1_DH (Bitfield-Mask: 0xfff)                        */
/* ======================================================  DAC1_L12DH  ======================================================= */
#define DAC_DAC1_L12DH_DAC1_DH_Pos        (4UL)                     /*!< DAC1_DH (Bit 4)                                       */
#define DAC_DAC1_L12DH_DAC1_DH_Msk        (0xfff0UL)                /*!< DAC1_DH (Bitfield-Mask: 0xfff)                        */
/* =======================================================  DAC1_R8DH  ======================================================= */
#define DAC_DAC1_R8DH_DAC1_DH_Pos         (0UL)                     /*!< DAC1_DH (Bit 0)                                       */
#define DAC_DAC1_R8DH_DAC1_DH_Msk         (0xffUL)                  /*!< DAC1_DH (Bitfield-Mask: 0xff)                         */
/* ======================================================  DACC_R12DH  ======================================================= */
#define DAC_DACC_R12DH_DAC0_DH_Pos        (0UL)                     /*!< DAC0_DH (Bit 0)                                       */
#define DAC_DACC_R12DH_DAC0_DH_Msk        (0xfffUL)                 /*!< DAC0_DH (Bitfield-Mask: 0xfff)                        */
#define DAC_DACC_R12DH_DAC1_DH_Pos        (16UL)                    /*!< DAC1_DH (Bit 16)                                      */
#define DAC_DACC_R12DH_DAC1_DH_Msk        (0xfff0000UL)             /*!< DAC1_DH (Bitfield-Mask: 0xfff)                        */
/* ======================================================  DACC_L12DH  ======================================================= */
#define DAC_DACC_L12DH_DAC0_DH_Pos        (4UL)                     /*!< DAC0_DH (Bit 4)                                       */
#define DAC_DACC_L12DH_DAC0_DH_Msk        (0xfff0UL)                /*!< DAC0_DH (Bitfield-Mask: 0xfff)                        */
#define DAC_DACC_L12DH_DAC1_DH_Pos        (20UL)                    /*!< DAC1_DH (Bit 20)                                      */
#define DAC_DACC_L12DH_DAC1_DH_Msk        (0xfff00000UL)            /*!< DAC1_DH (Bitfield-Mask: 0xfff)                        */
/* =======================================================  DACC_R8DH  ======================================================= */
#define DAC_DACC_R8DH_DAC0_DH_Pos         (0UL)                     /*!< DAC0_DH (Bit 0)                                       */
#define DAC_DACC_R8DH_DAC0_DH_Msk         (0xffUL)                  /*!< DAC0_DH (Bitfield-Mask: 0xff)                         */
#define DAC_DACC_R8DH_DAC1_DH_Pos         (8UL)                     /*!< DAC1_DH (Bit 8)                                       */
#define DAC_DACC_R8DH_DAC1_DH_Msk         (0xff00UL)                /*!< DAC1_DH (Bitfield-Mask: 0xff)                         */
/* ========================================================  DAC0_DO  ======================================================== */
#define DAC_DAC0_DO_DAC0_DO_Pos           (0UL)                     /*!< DAC0_DO (Bit 0)                                       */
#define DAC_DAC0_DO_DAC0_DO_Msk           (0xfffUL)                 /*!< DAC0_DO (Bitfield-Mask: 0xfff)                        */
/* ========================================================  DAC1_DO  ======================================================== */
#define DAC_DAC1_DO_DAC1_DO_Pos           (0UL)                     /*!< DAC1_DO (Bit 0)                                       */
#define DAC_DAC1_DO_DAC1_DO_Msk           (0xfffUL)                 /*!< DAC1_DO (Bitfield-Mask: 0xfff)                        */


/* =========================================================================================================================== */
/* ================                                            DBG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ID  =========================================================== */
#define DBG_ID_ID_CODE_Pos                (0UL)                     /*!< ID_CODE (Bit 0)                                       */
#define DBG_ID_ID_CODE_Msk                (0xffffffffUL)            /*!< ID_CODE (Bitfield-Mask: 0xffffffff)                   */
/* ==========================================================  CTL  ========================================================== */
#define DBG_CTL_SLP_HOLD_Pos              (0UL)                     /*!< SLP_HOLD (Bit 0)                                      */
#define DBG_CTL_SLP_HOLD_Msk              (0x1UL)                   /*!< SLP_HOLD (Bitfield-Mask: 0x01)                        */
#define DBG_CTL_DSLP_HOLD_Pos             (1UL)                     /*!< DSLP_HOLD (Bit 1)                                     */
#define DBG_CTL_DSLP_HOLD_Msk             (0x2UL)                   /*!< DSLP_HOLD (Bitfield-Mask: 0x01)                       */
#define DBG_CTL_STB_HOLD_Pos              (2UL)                     /*!< STB_HOLD (Bit 2)                                      */
#define DBG_CTL_STB_HOLD_Msk              (0x4UL)                   /*!< STB_HOLD (Bitfield-Mask: 0x01)                        */
#define DBG_CTL_FWDGT_HOLD_Pos            (8UL)                     /*!< FWDGT_HOLD (Bit 8)                                    */
#define DBG_CTL_FWDGT_HOLD_Msk            (0x100UL)                 /*!< FWDGT_HOLD (Bitfield-Mask: 0x01)                      */
#define DBG_CTL_WWDGT_HOLD_Pos            (9UL)                     /*!< WWDGT_HOLD (Bit 9)                                    */
#define DBG_CTL_WWDGT_HOLD_Msk            (0x200UL)                 /*!< WWDGT_HOLD (Bitfield-Mask: 0x01)                      */
#define DBG_CTL_TIMER0_HOLD_Pos           (10UL)                    /*!< TIMER0_HOLD (Bit 10)                                  */
#define DBG_CTL_TIMER0_HOLD_Msk           (0x400UL)                 /*!< TIMER0_HOLD (Bitfield-Mask: 0x01)                     */
#define DBG_CTL_TIMER1_HOLD_Pos           (11UL)                    /*!< TIMER1_HOLD (Bit 11)                                  */
#define DBG_CTL_TIMER1_HOLD_Msk           (0x800UL)                 /*!< TIMER1_HOLD (Bitfield-Mask: 0x01)                     */
#define DBG_CTL_TIMER2_HOLD_Pos           (12UL)                    /*!< TIMER2_HOLD (Bit 12)                                  */
#define DBG_CTL_TIMER2_HOLD_Msk           (0x1000UL)                /*!< TIMER2_HOLD (Bitfield-Mask: 0x01)                     */
#define DBG_CTL_TIMER3_HOLD_Pos           (13UL)                    /*!< TIMER3_HOLD (Bit 13)                                  */
#define DBG_CTL_TIMER3_HOLD_Msk           (0x2000UL)                /*!< TIMER3_HOLD (Bitfield-Mask: 0x01)                     */
#define DBG_CTL_CAN0_HOLD_Pos             (14UL)                    /*!< CAN0_HOLD (Bit 14)                                    */
#define DBG_CTL_CAN0_HOLD_Msk             (0x4000UL)                /*!< CAN0_HOLD (Bitfield-Mask: 0x01)                       */
#define DBG_CTL_I2C0_HOLD_Pos             (15UL)                    /*!< I2C0_HOLD (Bit 15)                                    */
#define DBG_CTL_I2C0_HOLD_Msk             (0x8000UL)                /*!< I2C0_HOLD (Bitfield-Mask: 0x01)                       */
#define DBG_CTL_I2C1_HOLD_Pos             (16UL)                    /*!< I2C1_HOLD (Bit 16)                                    */
#define DBG_CTL_I2C1_HOLD_Msk             (0x10000UL)               /*!< I2C1_HOLD (Bitfield-Mask: 0x01)                       */
#define DBG_CTL_TIMER4_HOLD_Pos           (18UL)                    /*!< TIMER4_HOLD (Bit 18)                                  */
#define DBG_CTL_TIMER4_HOLD_Msk           (0x40000UL)               /*!< TIMER4_HOLD (Bitfield-Mask: 0x01)                     */
#define DBG_CTL_TIMER5_HOLD_Pos           (19UL)                    /*!< TIMER5_HOLD (Bit 19)                                  */
#define DBG_CTL_TIMER5_HOLD_Msk           (0x80000UL)               /*!< TIMER5_HOLD (Bitfield-Mask: 0x01)                     */
#define DBG_CTL_TIMER6_HOLD_Pos           (20UL)                    /*!< TIMER6_HOLD (Bit 20)                                  */
#define DBG_CTL_TIMER6_HOLD_Msk           (0x100000UL)              /*!< TIMER6_HOLD (Bitfield-Mask: 0x01)                     */
#define DBG_CTL_CAN1_HOLD_Pos             (21UL)                    /*!< CAN1_HOLD (Bit 21)                                    */
#define DBG_CTL_CAN1_HOLD_Msk             (0x200000UL)              /*!< CAN1_HOLD (Bitfield-Mask: 0x01)                       */


/* =========================================================================================================================== */
/* ================                                           DMA0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INTF  ========================================================== */
#define DMA0_INTF_GIF0_Pos                (0UL)                     /*!< GIF0 (Bit 0)                                          */
#define DMA0_INTF_GIF0_Msk                (0x1UL)                   /*!< GIF0 (Bitfield-Mask: 0x01)                            */
#define DMA0_INTF_FTFIF0_Pos              (1UL)                     /*!< FTFIF0 (Bit 1)                                        */
#define DMA0_INTF_FTFIF0_Msk              (0x2UL)                   /*!< FTFIF0 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_HTFIF0_Pos              (2UL)                     /*!< HTFIF0 (Bit 2)                                        */
#define DMA0_INTF_HTFIF0_Msk              (0x4UL)                   /*!< HTFIF0 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_ERRIF0_Pos              (3UL)                     /*!< ERRIF0 (Bit 3)                                        */
#define DMA0_INTF_ERRIF0_Msk              (0x8UL)                   /*!< ERRIF0 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_GIF1_Pos                (4UL)                     /*!< GIF1 (Bit 4)                                          */
#define DMA0_INTF_GIF1_Msk                (0x10UL)                  /*!< GIF1 (Bitfield-Mask: 0x01)                            */
#define DMA0_INTF_FTFIF1_Pos              (5UL)                     /*!< FTFIF1 (Bit 5)                                        */
#define DMA0_INTF_FTFIF1_Msk              (0x20UL)                  /*!< FTFIF1 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_HTFIF1_Pos              (6UL)                     /*!< HTFIF1 (Bit 6)                                        */
#define DMA0_INTF_HTFIF1_Msk              (0x40UL)                  /*!< HTFIF1 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_ERRIF1_Pos              (7UL)                     /*!< ERRIF1 (Bit 7)                                        */
#define DMA0_INTF_ERRIF1_Msk              (0x80UL)                  /*!< ERRIF1 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_GIF2_Pos                (8UL)                     /*!< GIF2 (Bit 8)                                          */
#define DMA0_INTF_GIF2_Msk                (0x100UL)                 /*!< GIF2 (Bitfield-Mask: 0x01)                            */
#define DMA0_INTF_FTFIF2_Pos              (9UL)                     /*!< FTFIF2 (Bit 9)                                        */
#define DMA0_INTF_FTFIF2_Msk              (0x200UL)                 /*!< FTFIF2 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_HTFIF2_Pos              (10UL)                    /*!< HTFIF2 (Bit 10)                                       */
#define DMA0_INTF_HTFIF2_Msk              (0x400UL)                 /*!< HTFIF2 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_ERRIF2_Pos              (11UL)                    /*!< ERRIF2 (Bit 11)                                       */
#define DMA0_INTF_ERRIF2_Msk              (0x800UL)                 /*!< ERRIF2 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_GIF3_Pos                (12UL)                    /*!< GIF3 (Bit 12)                                         */
#define DMA0_INTF_GIF3_Msk                (0x1000UL)                /*!< GIF3 (Bitfield-Mask: 0x01)                            */
#define DMA0_INTF_FTFIF3_Pos              (13UL)                    /*!< FTFIF3 (Bit 13)                                       */
#define DMA0_INTF_FTFIF3_Msk              (0x2000UL)                /*!< FTFIF3 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_HTFIF3_Pos              (14UL)                    /*!< HTFIF3 (Bit 14)                                       */
#define DMA0_INTF_HTFIF3_Msk              (0x4000UL)                /*!< HTFIF3 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_ERRIF3_Pos              (15UL)                    /*!< ERRIF3 (Bit 15)                                       */
#define DMA0_INTF_ERRIF3_Msk              (0x8000UL)                /*!< ERRIF3 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_GIF4_Pos                (16UL)                    /*!< GIF4 (Bit 16)                                         */
#define DMA0_INTF_GIF4_Msk                (0x10000UL)               /*!< GIF4 (Bitfield-Mask: 0x01)                            */
#define DMA0_INTF_FTFIF4_Pos              (17UL)                    /*!< FTFIF4 (Bit 17)                                       */
#define DMA0_INTF_FTFIF4_Msk              (0x20000UL)               /*!< FTFIF4 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_HTFIF4_Pos              (18UL)                    /*!< HTFIF4 (Bit 18)                                       */
#define DMA0_INTF_HTFIF4_Msk              (0x40000UL)               /*!< HTFIF4 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_ERRIF4_Pos              (19UL)                    /*!< ERRIF4 (Bit 19)                                       */
#define DMA0_INTF_ERRIF4_Msk              (0x80000UL)               /*!< ERRIF4 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_GIF5_Pos                (20UL)                    /*!< GIF5 (Bit 20)                                         */
#define DMA0_INTF_GIF5_Msk                (0x100000UL)              /*!< GIF5 (Bitfield-Mask: 0x01)                            */
#define DMA0_INTF_FTFIF5_Pos              (21UL)                    /*!< FTFIF5 (Bit 21)                                       */
#define DMA0_INTF_FTFIF5_Msk              (0x200000UL)              /*!< FTFIF5 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_HTFIF5_Pos              (22UL)                    /*!< HTFIF5 (Bit 22)                                       */
#define DMA0_INTF_HTFIF5_Msk              (0x400000UL)              /*!< HTFIF5 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_ERRIF5_Pos              (23UL)                    /*!< ERRIF5 (Bit 23)                                       */
#define DMA0_INTF_ERRIF5_Msk              (0x800000UL)              /*!< ERRIF5 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_GIF6_Pos                (24UL)                    /*!< GIF6 (Bit 24)                                         */
#define DMA0_INTF_GIF6_Msk                (0x1000000UL)             /*!< GIF6 (Bitfield-Mask: 0x01)                            */
#define DMA0_INTF_FTFIF6_Pos              (25UL)                    /*!< FTFIF6 (Bit 25)                                       */
#define DMA0_INTF_FTFIF6_Msk              (0x2000000UL)             /*!< FTFIF6 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_HTFIF6_Pos              (26UL)                    /*!< HTFIF6 (Bit 26)                                       */
#define DMA0_INTF_HTFIF6_Msk              (0x4000000UL)             /*!< HTFIF6 (Bitfield-Mask: 0x01)                          */
#define DMA0_INTF_ERRIF6_Pos              (27UL)                    /*!< ERRIF6 (Bit 27)                                       */
#define DMA0_INTF_ERRIF6_Msk              (0x8000000UL)             /*!< ERRIF6 (Bitfield-Mask: 0x01)                          */
/* =========================================================  INTC  ========================================================== */
#define DMA0_INTC_GIFC0_Pos               (0UL)                     /*!< GIFC0 (Bit 0)                                         */
#define DMA0_INTC_GIFC0_Msk               (0x1UL)                   /*!< GIFC0 (Bitfield-Mask: 0x01)                           */
#define DMA0_INTC_FTFIFC0_Pos             (1UL)                     /*!< FTFIFC0 (Bit 1)                                       */
#define DMA0_INTC_FTFIFC0_Msk             (0x2UL)                   /*!< FTFIFC0 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_HTFIFC0_Pos             (2UL)                     /*!< HTFIFC0 (Bit 2)                                       */
#define DMA0_INTC_HTFIFC0_Msk             (0x4UL)                   /*!< HTFIFC0 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_ERRIFC0_Pos             (3UL)                     /*!< ERRIFC0 (Bit 3)                                       */
#define DMA0_INTC_ERRIFC0_Msk             (0x8UL)                   /*!< ERRIFC0 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_GIFC1_Pos               (4UL)                     /*!< GIFC1 (Bit 4)                                         */
#define DMA0_INTC_GIFC1_Msk               (0x10UL)                  /*!< GIFC1 (Bitfield-Mask: 0x01)                           */
#define DMA0_INTC_FTFIFC1_Pos             (5UL)                     /*!< FTFIFC1 (Bit 5)                                       */
#define DMA0_INTC_FTFIFC1_Msk             (0x20UL)                  /*!< FTFIFC1 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_HTFIFC1_Pos             (6UL)                     /*!< HTFIFC1 (Bit 6)                                       */
#define DMA0_INTC_HTFIFC1_Msk             (0x40UL)                  /*!< HTFIFC1 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_ERRIFC1_Pos             (7UL)                     /*!< ERRIFC1 (Bit 7)                                       */
#define DMA0_INTC_ERRIFC1_Msk             (0x80UL)                  /*!< ERRIFC1 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_GIFC2_Pos               (8UL)                     /*!< GIFC2 (Bit 8)                                         */
#define DMA0_INTC_GIFC2_Msk               (0x100UL)                 /*!< GIFC2 (Bitfield-Mask: 0x01)                           */
#define DMA0_INTC_FTFIFC2_Pos             (9UL)                     /*!< FTFIFC2 (Bit 9)                                       */
#define DMA0_INTC_FTFIFC2_Msk             (0x200UL)                 /*!< FTFIFC2 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_HTFIFC2_Pos             (10UL)                    /*!< HTFIFC2 (Bit 10)                                      */
#define DMA0_INTC_HTFIFC2_Msk             (0x400UL)                 /*!< HTFIFC2 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_ERRIFC2_Pos             (11UL)                    /*!< ERRIFC2 (Bit 11)                                      */
#define DMA0_INTC_ERRIFC2_Msk             (0x800UL)                 /*!< ERRIFC2 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_GIFC3_Pos               (12UL)                    /*!< GIFC3 (Bit 12)                                        */
#define DMA0_INTC_GIFC3_Msk               (0x1000UL)                /*!< GIFC3 (Bitfield-Mask: 0x01)                           */
#define DMA0_INTC_FTFIFC3_Pos             (13UL)                    /*!< FTFIFC3 (Bit 13)                                      */
#define DMA0_INTC_FTFIFC3_Msk             (0x2000UL)                /*!< FTFIFC3 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_HTFIFC3_Pos             (14UL)                    /*!< HTFIFC3 (Bit 14)                                      */
#define DMA0_INTC_HTFIFC3_Msk             (0x4000UL)                /*!< HTFIFC3 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_ERRIFC3_Pos             (15UL)                    /*!< ERRIFC3 (Bit 15)                                      */
#define DMA0_INTC_ERRIFC3_Msk             (0x8000UL)                /*!< ERRIFC3 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_GIFC4_Pos               (16UL)                    /*!< GIFC4 (Bit 16)                                        */
#define DMA0_INTC_GIFC4_Msk               (0x10000UL)               /*!< GIFC4 (Bitfield-Mask: 0x01)                           */
#define DMA0_INTC_FTFIFC4_Pos             (17UL)                    /*!< FTFIFC4 (Bit 17)                                      */
#define DMA0_INTC_FTFIFC4_Msk             (0x20000UL)               /*!< FTFIFC4 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_HTFIFC4_Pos             (18UL)                    /*!< HTFIFC4 (Bit 18)                                      */
#define DMA0_INTC_HTFIFC4_Msk             (0x40000UL)               /*!< HTFIFC4 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_ERRIFC4_Pos             (19UL)                    /*!< ERRIFC4 (Bit 19)                                      */
#define DMA0_INTC_ERRIFC4_Msk             (0x80000UL)               /*!< ERRIFC4 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_GIFC5_Pos               (20UL)                    /*!< GIFC5 (Bit 20)                                        */
#define DMA0_INTC_GIFC5_Msk               (0x100000UL)              /*!< GIFC5 (Bitfield-Mask: 0x01)                           */
#define DMA0_INTC_FTFIFC5_Pos             (21UL)                    /*!< FTFIFC5 (Bit 21)                                      */
#define DMA0_INTC_FTFIFC5_Msk             (0x200000UL)              /*!< FTFIFC5 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_HTFIFC5_Pos             (22UL)                    /*!< HTFIFC5 (Bit 22)                                      */
#define DMA0_INTC_HTFIFC5_Msk             (0x400000UL)              /*!< HTFIFC5 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_ERRIFC5_Pos             (23UL)                    /*!< ERRIFC5 (Bit 23)                                      */
#define DMA0_INTC_ERRIFC5_Msk             (0x800000UL)              /*!< ERRIFC5 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_GIFC6_Pos               (24UL)                    /*!< GIFC6 (Bit 24)                                        */
#define DMA0_INTC_GIFC6_Msk               (0x1000000UL)             /*!< GIFC6 (Bitfield-Mask: 0x01)                           */
#define DMA0_INTC_FTFIFC6_Pos             (25UL)                    /*!< FTFIFC6 (Bit 25)                                      */
#define DMA0_INTC_FTFIFC6_Msk             (0x2000000UL)             /*!< FTFIFC6 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_HTFIFC6_Pos             (26UL)                    /*!< HTFIFC6 (Bit 26)                                      */
#define DMA0_INTC_HTFIFC6_Msk             (0x4000000UL)             /*!< HTFIFC6 (Bitfield-Mask: 0x01)                         */
#define DMA0_INTC_ERRIFC6_Pos             (27UL)                    /*!< ERRIFC6 (Bit 27)                                      */
#define DMA0_INTC_ERRIFC6_Msk             (0x8000000UL)             /*!< ERRIFC6 (Bitfield-Mask: 0x01)                         */
/* ========================================================  CH0CTL  ========================================================= */
#define DMA0_CH0CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA0_CH0CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH0CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA0_CH0CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH0CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA0_CH0CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH0CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA0_CH0CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH0CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA0_CH0CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA0_CH0CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA0_CH0CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH0CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA0_CH0CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH0CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA0_CH0CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH0CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA0_CH0CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH0CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA0_CH0CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH0CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA0_CH0CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA0_CH0CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA0_CH0CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH0CNT  ========================================================= */
#define DMA0_CH0CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA0_CH0CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH0PADDR  ======================================================== */
#define DMA0_CH0PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA0_CH0PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH0MADDR  ======================================================== */
#define DMA0_CH0MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA0_CH0MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH1CTL  ========================================================= */
#define DMA0_CH1CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA0_CH1CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH1CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA0_CH1CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH1CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA0_CH1CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH1CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA0_CH1CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH1CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA0_CH1CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA0_CH1CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA0_CH1CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH1CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA0_CH1CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH1CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA0_CH1CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH1CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA0_CH1CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH1CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA0_CH1CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH1CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA0_CH1CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA0_CH1CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA0_CH1CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH1CNT  ========================================================= */
#define DMA0_CH1CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA0_CH1CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH1PADDR  ======================================================== */
#define DMA0_CH1PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA0_CH1PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH1MADDR  ======================================================== */
#define DMA0_CH1MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA0_CH1MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH2CTL  ========================================================= */
#define DMA0_CH2CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA0_CH2CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH2CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA0_CH2CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH2CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA0_CH2CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH2CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA0_CH2CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH2CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA0_CH2CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA0_CH2CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA0_CH2CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH2CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA0_CH2CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH2CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA0_CH2CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH2CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA0_CH2CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH2CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA0_CH2CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH2CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA0_CH2CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA0_CH2CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA0_CH2CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH2CNT  ========================================================= */
#define DMA0_CH2CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA0_CH2CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH2PADDR  ======================================================== */
#define DMA0_CH2PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA0_CH2PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH2MADDR  ======================================================== */
#define DMA0_CH2MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA0_CH2MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH3CTL  ========================================================= */
#define DMA0_CH3CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA0_CH3CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH3CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA0_CH3CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH3CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA0_CH3CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH3CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA0_CH3CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH3CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA0_CH3CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA0_CH3CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA0_CH3CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH3CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA0_CH3CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH3CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA0_CH3CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH3CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA0_CH3CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH3CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA0_CH3CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH3CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA0_CH3CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA0_CH3CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA0_CH3CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH3CNT  ========================================================= */
#define DMA0_CH3CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA0_CH3CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH3PADDR  ======================================================== */
#define DMA0_CH3PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA0_CH3PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH3MADDR  ======================================================== */
#define DMA0_CH3MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA0_CH3MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH4CTL  ========================================================= */
#define DMA0_CH4CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA0_CH4CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH4CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA0_CH4CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH4CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA0_CH4CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH4CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA0_CH4CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH4CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA0_CH4CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA0_CH4CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA0_CH4CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH4CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA0_CH4CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH4CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA0_CH4CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH4CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA0_CH4CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH4CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA0_CH4CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH4CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA0_CH4CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA0_CH4CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA0_CH4CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH4CNT  ========================================================= */
#define DMA0_CH4CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA0_CH4CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH4PADDR  ======================================================== */
#define DMA0_CH4PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA0_CH4PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH4MADDR  ======================================================== */
#define DMA0_CH4MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA0_CH4MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH5CTL  ========================================================= */
#define DMA0_CH5CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA0_CH5CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH5CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA0_CH5CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH5CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA0_CH5CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH5CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA0_CH5CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH5CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA0_CH5CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA0_CH5CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA0_CH5CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH5CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA0_CH5CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH5CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA0_CH5CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH5CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA0_CH5CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH5CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA0_CH5CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH5CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA0_CH5CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA0_CH5CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA0_CH5CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH5CNT  ========================================================= */
#define DMA0_CH5CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA0_CH5CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH5PADDR  ======================================================== */
#define DMA0_CH5PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA0_CH5PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH5MADDR  ======================================================== */
#define DMA0_CH5MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA0_CH5MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH6CTL  ========================================================= */
#define DMA0_CH6CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA0_CH6CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH6CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA0_CH6CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH6CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA0_CH6CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH6CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA0_CH6CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA0_CH6CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA0_CH6CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA0_CH6CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA0_CH6CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA0_CH6CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA0_CH6CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH6CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA0_CH6CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA0_CH6CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA0_CH6CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH6CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA0_CH6CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA0_CH6CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA0_CH6CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA0_CH6CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA0_CH6CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH6CNT  ========================================================= */
#define DMA0_CH6CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA0_CH6CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH6PADDR  ======================================================== */
#define DMA0_CH6PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA0_CH6PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH6MADDR  ======================================================== */
#define DMA0_CH6MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA0_CH6MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */


/* =========================================================================================================================== */
/* ================                                           DMA1                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INTF  ========================================================== */
#define DMA1_INTF_GIF0_Pos                (0UL)                     /*!< GIF0 (Bit 0)                                          */
#define DMA1_INTF_GIF0_Msk                (0x1UL)                   /*!< GIF0 (Bitfield-Mask: 0x01)                            */
#define DMA1_INTF_FTFIF0_Pos              (1UL)                     /*!< FTFIF0 (Bit 1)                                        */
#define DMA1_INTF_FTFIF0_Msk              (0x2UL)                   /*!< FTFIF0 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_HTFIF0_Pos              (2UL)                     /*!< HTFIF0 (Bit 2)                                        */
#define DMA1_INTF_HTFIF0_Msk              (0x4UL)                   /*!< HTFIF0 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_ERRIF0_Pos              (3UL)                     /*!< ERRIF0 (Bit 3)                                        */
#define DMA1_INTF_ERRIF0_Msk              (0x8UL)                   /*!< ERRIF0 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_GIF1_Pos                (4UL)                     /*!< GIF1 (Bit 4)                                          */
#define DMA1_INTF_GIF1_Msk                (0x10UL)                  /*!< GIF1 (Bitfield-Mask: 0x01)                            */
#define DMA1_INTF_FTFIF1_Pos              (5UL)                     /*!< FTFIF1 (Bit 5)                                        */
#define DMA1_INTF_FTFIF1_Msk              (0x20UL)                  /*!< FTFIF1 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_HTFIF1_Pos              (6UL)                     /*!< HTFIF1 (Bit 6)                                        */
#define DMA1_INTF_HTFIF1_Msk              (0x40UL)                  /*!< HTFIF1 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_ERRIF1_Pos              (7UL)                     /*!< ERRIF1 (Bit 7)                                        */
#define DMA1_INTF_ERRIF1_Msk              (0x80UL)                  /*!< ERRIF1 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_GIF2_Pos                (8UL)                     /*!< GIF2 (Bit 8)                                          */
#define DMA1_INTF_GIF2_Msk                (0x100UL)                 /*!< GIF2 (Bitfield-Mask: 0x01)                            */
#define DMA1_INTF_FTFIF2_Pos              (9UL)                     /*!< FTFIF2 (Bit 9)                                        */
#define DMA1_INTF_FTFIF2_Msk              (0x200UL)                 /*!< FTFIF2 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_HTFIF2_Pos              (10UL)                    /*!< HTFIF2 (Bit 10)                                       */
#define DMA1_INTF_HTFIF2_Msk              (0x400UL)                 /*!< HTFIF2 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_ERRIF2_Pos              (11UL)                    /*!< ERRIF2 (Bit 11)                                       */
#define DMA1_INTF_ERRIF2_Msk              (0x800UL)                 /*!< ERRIF2 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_GIF3_Pos                (12UL)                    /*!< GIF3 (Bit 12)                                         */
#define DMA1_INTF_GIF3_Msk                (0x1000UL)                /*!< GIF3 (Bitfield-Mask: 0x01)                            */
#define DMA1_INTF_FTFIF3_Pos              (13UL)                    /*!< FTFIF3 (Bit 13)                                       */
#define DMA1_INTF_FTFIF3_Msk              (0x2000UL)                /*!< FTFIF3 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_HTFIF3_Pos              (14UL)                    /*!< HTFIF3 (Bit 14)                                       */
#define DMA1_INTF_HTFIF3_Msk              (0x4000UL)                /*!< HTFIF3 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_ERRIF3_Pos              (15UL)                    /*!< ERRIF3 (Bit 15)                                       */
#define DMA1_INTF_ERRIF3_Msk              (0x8000UL)                /*!< ERRIF3 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_GIF4_Pos                (16UL)                    /*!< GIF4 (Bit 16)                                         */
#define DMA1_INTF_GIF4_Msk                (0x10000UL)               /*!< GIF4 (Bitfield-Mask: 0x01)                            */
#define DMA1_INTF_FTFIF4_Pos              (17UL)                    /*!< FTFIF4 (Bit 17)                                       */
#define DMA1_INTF_FTFIF4_Msk              (0x20000UL)               /*!< FTFIF4 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_HTFIF4_Pos              (18UL)                    /*!< HTFIF4 (Bit 18)                                       */
#define DMA1_INTF_HTFIF4_Msk              (0x40000UL)               /*!< HTFIF4 (Bitfield-Mask: 0x01)                          */
#define DMA1_INTF_ERRIF4_Pos              (19UL)                    /*!< ERRIF4 (Bit 19)                                       */
#define DMA1_INTF_ERRIF4_Msk              (0x80000UL)               /*!< ERRIF4 (Bitfield-Mask: 0x01)                          */
/* =========================================================  INTC  ========================================================== */
#define DMA1_INTC_GIFC0_Pos               (0UL)                     /*!< GIFC0 (Bit 0)                                         */
#define DMA1_INTC_GIFC0_Msk               (0x1UL)                   /*!< GIFC0 (Bitfield-Mask: 0x01)                           */
#define DMA1_INTC_FTFIFC0_Pos             (1UL)                     /*!< FTFIFC0 (Bit 1)                                       */
#define DMA1_INTC_FTFIFC0_Msk             (0x2UL)                   /*!< FTFIFC0 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_HTFIFC0_Pos             (2UL)                     /*!< HTFIFC0 (Bit 2)                                       */
#define DMA1_INTC_HTFIFC0_Msk             (0x4UL)                   /*!< HTFIFC0 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_ERRIFC0_Pos             (3UL)                     /*!< ERRIFC0 (Bit 3)                                       */
#define DMA1_INTC_ERRIFC0_Msk             (0x8UL)                   /*!< ERRIFC0 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_GIFC1_Pos               (4UL)                     /*!< GIFC1 (Bit 4)                                         */
#define DMA1_INTC_GIFC1_Msk               (0x10UL)                  /*!< GIFC1 (Bitfield-Mask: 0x01)                           */
#define DMA1_INTC_FTFIFC1_Pos             (5UL)                     /*!< FTFIFC1 (Bit 5)                                       */
#define DMA1_INTC_FTFIFC1_Msk             (0x20UL)                  /*!< FTFIFC1 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_HTFIFC1_Pos             (6UL)                     /*!< HTFIFC1 (Bit 6)                                       */
#define DMA1_INTC_HTFIFC1_Msk             (0x40UL)                  /*!< HTFIFC1 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_ERRIFC1_Pos             (7UL)                     /*!< ERRIFC1 (Bit 7)                                       */
#define DMA1_INTC_ERRIFC1_Msk             (0x80UL)                  /*!< ERRIFC1 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_GIFC2_Pos               (8UL)                     /*!< GIFC2 (Bit 8)                                         */
#define DMA1_INTC_GIFC2_Msk               (0x100UL)                 /*!< GIFC2 (Bitfield-Mask: 0x01)                           */
#define DMA1_INTC_FTFIFC2_Pos             (9UL)                     /*!< FTFIFC2 (Bit 9)                                       */
#define DMA1_INTC_FTFIFC2_Msk             (0x200UL)                 /*!< FTFIFC2 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_HTFIFC2_Pos             (10UL)                    /*!< HTFIFC2 (Bit 10)                                      */
#define DMA1_INTC_HTFIFC2_Msk             (0x400UL)                 /*!< HTFIFC2 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_ERRIFC2_Pos             (11UL)                    /*!< ERRIFC2 (Bit 11)                                      */
#define DMA1_INTC_ERRIFC2_Msk             (0x800UL)                 /*!< ERRIFC2 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_GIFC3_Pos               (12UL)                    /*!< GIFC3 (Bit 12)                                        */
#define DMA1_INTC_GIFC3_Msk               (0x1000UL)                /*!< GIFC3 (Bitfield-Mask: 0x01)                           */
#define DMA1_INTC_FTFIFC3_Pos             (13UL)                    /*!< FTFIFC3 (Bit 13)                                      */
#define DMA1_INTC_FTFIFC3_Msk             (0x2000UL)                /*!< FTFIFC3 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_HTFIFC3_Pos             (14UL)                    /*!< HTFIFC3 (Bit 14)                                      */
#define DMA1_INTC_HTFIFC3_Msk             (0x4000UL)                /*!< HTFIFC3 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_ERRIFC3_Pos             (15UL)                    /*!< ERRIFC3 (Bit 15)                                      */
#define DMA1_INTC_ERRIFC3_Msk             (0x8000UL)                /*!< ERRIFC3 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_GIFC4_Pos               (16UL)                    /*!< GIFC4 (Bit 16)                                        */
#define DMA1_INTC_GIFC4_Msk               (0x10000UL)               /*!< GIFC4 (Bitfield-Mask: 0x01)                           */
#define DMA1_INTC_FTFIFC4_Pos             (17UL)                    /*!< FTFIFC4 (Bit 17)                                      */
#define DMA1_INTC_FTFIFC4_Msk             (0x20000UL)               /*!< FTFIFC4 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_HTFIFC4_Pos             (18UL)                    /*!< HTFIFC4 (Bit 18)                                      */
#define DMA1_INTC_HTFIFC4_Msk             (0x40000UL)               /*!< HTFIFC4 (Bitfield-Mask: 0x01)                         */
#define DMA1_INTC_ERRIFC4_Pos             (19UL)                    /*!< ERRIFC4 (Bit 19)                                      */
#define DMA1_INTC_ERRIFC4_Msk             (0x80000UL)               /*!< ERRIFC4 (Bitfield-Mask: 0x01)                         */
/* ========================================================  CH0CTL  ========================================================= */
#define DMA1_CH0CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA1_CH0CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH0CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA1_CH0CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH0CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA1_CH0CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH0CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA1_CH0CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH0CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA1_CH0CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA1_CH0CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA1_CH0CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH0CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA1_CH0CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH0CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA1_CH0CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH0CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA1_CH0CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH0CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA1_CH0CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH0CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA1_CH0CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA1_CH0CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA1_CH0CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH0CNT  ========================================================= */
#define DMA1_CH0CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA1_CH0CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH0PADDR  ======================================================== */
#define DMA1_CH0PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA1_CH0PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH0MADDR  ======================================================== */
#define DMA1_CH0MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA1_CH0MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH1CTL  ========================================================= */
#define DMA1_CH1CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA1_CH1CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH1CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA1_CH1CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH1CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA1_CH1CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH1CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA1_CH1CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH1CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA1_CH1CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA1_CH1CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA1_CH1CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH1CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA1_CH1CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH1CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA1_CH1CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH1CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA1_CH1CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH1CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA1_CH1CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH1CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA1_CH1CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA1_CH1CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA1_CH1CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH1CNT  ========================================================= */
#define DMA1_CH1CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA1_CH1CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH1PADDR  ======================================================== */
#define DMA1_CH1PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA1_CH1PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH1MADDR  ======================================================== */
#define DMA1_CH1MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA1_CH1MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH2CTL  ========================================================= */
#define DMA1_CH2CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA1_CH2CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH2CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA1_CH2CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH2CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA1_CH2CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH2CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA1_CH2CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH2CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA1_CH2CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA1_CH2CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA1_CH2CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH2CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA1_CH2CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH2CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA1_CH2CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH2CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA1_CH2CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH2CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA1_CH2CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH2CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA1_CH2CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA1_CH2CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA1_CH2CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH2CNT  ========================================================= */
#define DMA1_CH2CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA1_CH2CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH2PADDR  ======================================================== */
#define DMA1_CH2PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA1_CH2PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH2MADDR  ======================================================== */
#define DMA1_CH2MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA1_CH2MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH3CTL  ========================================================= */
#define DMA1_CH3CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA1_CH3CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH3CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA1_CH3CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH3CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA1_CH3CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH3CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA1_CH3CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH3CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA1_CH3CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA1_CH3CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA1_CH3CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH3CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA1_CH3CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH3CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA1_CH3CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH3CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA1_CH3CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH3CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA1_CH3CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH3CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA1_CH3CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA1_CH3CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA1_CH3CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH3CNT  ========================================================= */
#define DMA1_CH3CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA1_CH3CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH3PADDR  ======================================================== */
#define DMA1_CH3PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA1_CH3PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH3MADDR  ======================================================== */
#define DMA1_CH3MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA1_CH3MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  CH4CTL  ========================================================= */
#define DMA1_CH4CTL_CHEN_Pos              (0UL)                     /*!< CHEN (Bit 0)                                          */
#define DMA1_CH4CTL_CHEN_Msk              (0x1UL)                   /*!< CHEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH4CTL_FTFIE_Pos             (1UL)                     /*!< FTFIE (Bit 1)                                         */
#define DMA1_CH4CTL_FTFIE_Msk             (0x2UL)                   /*!< FTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH4CTL_HTFIE_Pos             (2UL)                     /*!< HTFIE (Bit 2)                                         */
#define DMA1_CH4CTL_HTFIE_Msk             (0x4UL)                   /*!< HTFIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH4CTL_ERRIE_Pos             (3UL)                     /*!< ERRIE (Bit 3)                                         */
#define DMA1_CH4CTL_ERRIE_Msk             (0x8UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define DMA1_CH4CTL_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA1_CH4CTL_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA1_CH4CTL_CMEN_Pos              (5UL)                     /*!< CMEN (Bit 5)                                          */
#define DMA1_CH4CTL_CMEN_Msk              (0x20UL)                  /*!< CMEN (Bitfield-Mask: 0x01)                            */
#define DMA1_CH4CTL_PNAGA_Pos             (6UL)                     /*!< PNAGA (Bit 6)                                         */
#define DMA1_CH4CTL_PNAGA_Msk             (0x40UL)                  /*!< PNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH4CTL_MNAGA_Pos             (7UL)                     /*!< MNAGA (Bit 7)                                         */
#define DMA1_CH4CTL_MNAGA_Msk             (0x80UL)                  /*!< MNAGA (Bitfield-Mask: 0x01)                           */
#define DMA1_CH4CTL_PWIDTH_Pos            (8UL)                     /*!< PWIDTH (Bit 8)                                        */
#define DMA1_CH4CTL_PWIDTH_Msk            (0x300UL)                 /*!< PWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH4CTL_MWIDTH_Pos            (10UL)                    /*!< MWIDTH (Bit 10)                                       */
#define DMA1_CH4CTL_MWIDTH_Msk            (0xc00UL)                 /*!< MWIDTH (Bitfield-Mask: 0x03)                          */
#define DMA1_CH4CTL_PRIO_Pos              (12UL)                    /*!< PRIO (Bit 12)                                         */
#define DMA1_CH4CTL_PRIO_Msk              (0x3000UL)                /*!< PRIO (Bitfield-Mask: 0x03)                            */
#define DMA1_CH4CTL_M2M_Pos               (14UL)                    /*!< M2M (Bit 14)                                          */
#define DMA1_CH4CTL_M2M_Msk               (0x4000UL)                /*!< M2M (Bitfield-Mask: 0x01)                             */
/* ========================================================  CH4CNT  ========================================================= */
#define DMA1_CH4CNT_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA1_CH4CNT_CNT_Msk               (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH4PADDR  ======================================================== */
#define DMA1_CH4PADDR_PADDR_Pos           (0UL)                     /*!< PADDR (Bit 0)                                         */
#define DMA1_CH4PADDR_PADDR_Msk           (0xffffffffUL)            /*!< PADDR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CH4MADDR  ======================================================== */
#define DMA1_CH4MADDR_MADDR_Pos           (0UL)                     /*!< MADDR (Bit 0)                                         */
#define DMA1_CH4MADDR_MADDR_Msk           (0xffffffffUL)            /*!< MADDR (Bitfield-Mask: 0xffffffff)                     */


/* =========================================================================================================================== */
/* ================                                           EXMC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  SNCTL0  ========================================================= */
#define EXMC_SNCTL0_ASYNCWAIT_Pos         (15UL)                    /*!< ASYNCWAIT (Bit 15)                                    */
#define EXMC_SNCTL0_ASYNCWAIT_Msk         (0x8000UL)                /*!< ASYNCWAIT (Bitfield-Mask: 0x01)                       */
#define EXMC_SNCTL0_NRWTEN_Pos            (13UL)                    /*!< NRWTEN (Bit 13)                                       */
#define EXMC_SNCTL0_NRWTEN_Msk            (0x2000UL)                /*!< NRWTEN (Bitfield-Mask: 0x01)                          */
#define EXMC_SNCTL0_WREN_Pos              (12UL)                    /*!< WREN (Bit 12)                                         */
#define EXMC_SNCTL0_WREN_Msk              (0x1000UL)                /*!< WREN (Bitfield-Mask: 0x01)                            */
#define EXMC_SNCTL0_NRWTPOL_Pos           (9UL)                     /*!< NRWTPOL (Bit 9)                                       */
#define EXMC_SNCTL0_NRWTPOL_Msk           (0x200UL)                 /*!< NRWTPOL (Bitfield-Mask: 0x01)                         */
#define EXMC_SNCTL0_NREN_Pos              (6UL)                     /*!< NREN (Bit 6)                                          */
#define EXMC_SNCTL0_NREN_Msk              (0x40UL)                  /*!< NREN (Bitfield-Mask: 0x01)                            */
#define EXMC_SNCTL0_NRW_Pos               (4UL)                     /*!< NRW (Bit 4)                                           */
#define EXMC_SNCTL0_NRW_Msk               (0x30UL)                  /*!< NRW (Bitfield-Mask: 0x03)                             */
#define EXMC_SNCTL0_NRTP_Pos              (2UL)                     /*!< NRTP (Bit 2)                                          */
#define EXMC_SNCTL0_NRTP_Msk              (0xcUL)                   /*!< NRTP (Bitfield-Mask: 0x03)                            */
#define EXMC_SNCTL0_NRMUX_Pos             (1UL)                     /*!< NRMUX (Bit 1)                                         */
#define EXMC_SNCTL0_NRMUX_Msk             (0x2UL)                   /*!< NRMUX (Bitfield-Mask: 0x01)                           */
#define EXMC_SNCTL0_NRBKEN_Pos            (0UL)                     /*!< NRBKEN (Bit 0)                                        */
#define EXMC_SNCTL0_NRBKEN_Msk            (0x1UL)                   /*!< NRBKEN (Bitfield-Mask: 0x01)                          */
/* ========================================================  SNTCFG0  ======================================================== */
#define EXMC_SNTCFG0_BUSLAT_Pos           (16UL)                    /*!< BUSLAT (Bit 16)                                       */
#define EXMC_SNTCFG0_BUSLAT_Msk           (0xf0000UL)               /*!< BUSLAT (Bitfield-Mask: 0x0f)                          */
#define EXMC_SNTCFG0_DSET_Pos             (8UL)                     /*!< DSET (Bit 8)                                          */
#define EXMC_SNTCFG0_DSET_Msk             (0xff00UL)                /*!< DSET (Bitfield-Mask: 0xff)                            */
#define EXMC_SNTCFG0_AHLD_Pos             (4UL)                     /*!< AHLD (Bit 4)                                          */
#define EXMC_SNTCFG0_AHLD_Msk             (0xf0UL)                  /*!< AHLD (Bitfield-Mask: 0x0f)                            */
#define EXMC_SNTCFG0_ASET_Pos             (0UL)                     /*!< ASET (Bit 0)                                          */
#define EXMC_SNTCFG0_ASET_Msk             (0xfUL)                   /*!< ASET (Bitfield-Mask: 0x0f)                            */
/* ========================================================  SNCTL1  ========================================================= */
#define EXMC_SNCTL1_ASYNCWAIT_Pos         (15UL)                    /*!< ASYNCWAIT (Bit 15)                                    */
#define EXMC_SNCTL1_ASYNCWAIT_Msk         (0x8000UL)                /*!< ASYNCWAIT (Bitfield-Mask: 0x01)                       */
#define EXMC_SNCTL1_NRWTEN_Pos            (13UL)                    /*!< NRWTEN (Bit 13)                                       */
#define EXMC_SNCTL1_NRWTEN_Msk            (0x2000UL)                /*!< NRWTEN (Bitfield-Mask: 0x01)                          */
#define EXMC_SNCTL1_WREN_Pos              (12UL)                    /*!< WREN (Bit 12)                                         */
#define EXMC_SNCTL1_WREN_Msk              (0x1000UL)                /*!< WREN (Bitfield-Mask: 0x01)                            */
#define EXMC_SNCTL1_NRWTPOL_Pos           (9UL)                     /*!< NRWTPOL (Bit 9)                                       */
#define EXMC_SNCTL1_NRWTPOL_Msk           (0x200UL)                 /*!< NRWTPOL (Bitfield-Mask: 0x01)                         */
#define EXMC_SNCTL1_NREN_Pos              (6UL)                     /*!< NREN (Bit 6)                                          */
#define EXMC_SNCTL1_NREN_Msk              (0x40UL)                  /*!< NREN (Bitfield-Mask: 0x01)                            */
#define EXMC_SNCTL1_NRW_Pos               (4UL)                     /*!< NRW (Bit 4)                                           */
#define EXMC_SNCTL1_NRW_Msk               (0x30UL)                  /*!< NRW (Bitfield-Mask: 0x03)                             */
#define EXMC_SNCTL1_NRTP_Pos              (2UL)                     /*!< NRTP (Bit 2)                                          */
#define EXMC_SNCTL1_NRTP_Msk              (0xcUL)                   /*!< NRTP (Bitfield-Mask: 0x03)                            */
#define EXMC_SNCTL1_NRMUX_Pos             (1UL)                     /*!< NRMUX (Bit 1)                                         */
#define EXMC_SNCTL1_NRMUX_Msk             (0x2UL)                   /*!< NRMUX (Bitfield-Mask: 0x01)                           */
#define EXMC_SNCTL1_NRBKEN_Pos            (0UL)                     /*!< NRBKEN (Bit 0)                                        */
#define EXMC_SNCTL1_NRBKEN_Msk            (0x1UL)                   /*!< NRBKEN (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                           EXTI                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INTEN  ========================================================= */
#define EXTI_INTEN_INTEN0_Pos             (0UL)                     /*!< INTEN0 (Bit 0)                                        */
#define EXTI_INTEN_INTEN0_Msk             (0x1UL)                   /*!< INTEN0 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN1_Pos             (1UL)                     /*!< INTEN1 (Bit 1)                                        */
#define EXTI_INTEN_INTEN1_Msk             (0x2UL)                   /*!< INTEN1 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN2_Pos             (2UL)                     /*!< INTEN2 (Bit 2)                                        */
#define EXTI_INTEN_INTEN2_Msk             (0x4UL)                   /*!< INTEN2 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN3_Pos             (3UL)                     /*!< INTEN3 (Bit 3)                                        */
#define EXTI_INTEN_INTEN3_Msk             (0x8UL)                   /*!< INTEN3 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN4_Pos             (4UL)                     /*!< INTEN4 (Bit 4)                                        */
#define EXTI_INTEN_INTEN4_Msk             (0x10UL)                  /*!< INTEN4 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN5_Pos             (5UL)                     /*!< INTEN5 (Bit 5)                                        */
#define EXTI_INTEN_INTEN5_Msk             (0x20UL)                  /*!< INTEN5 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN6_Pos             (6UL)                     /*!< INTEN6 (Bit 6)                                        */
#define EXTI_INTEN_INTEN6_Msk             (0x40UL)                  /*!< INTEN6 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN7_Pos             (7UL)                     /*!< INTEN7 (Bit 7)                                        */
#define EXTI_INTEN_INTEN7_Msk             (0x80UL)                  /*!< INTEN7 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN8_Pos             (8UL)                     /*!< INTEN8 (Bit 8)                                        */
#define EXTI_INTEN_INTEN8_Msk             (0x100UL)                 /*!< INTEN8 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN9_Pos             (9UL)                     /*!< INTEN9 (Bit 9)                                        */
#define EXTI_INTEN_INTEN9_Msk             (0x200UL)                 /*!< INTEN9 (Bitfield-Mask: 0x01)                          */
#define EXTI_INTEN_INTEN10_Pos            (10UL)                    /*!< INTEN10 (Bit 10)                                      */
#define EXTI_INTEN_INTEN10_Msk            (0x400UL)                 /*!< INTEN10 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN11_Pos            (11UL)                    /*!< INTEN11 (Bit 11)                                      */
#define EXTI_INTEN_INTEN11_Msk            (0x800UL)                 /*!< INTEN11 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN12_Pos            (12UL)                    /*!< INTEN12 (Bit 12)                                      */
#define EXTI_INTEN_INTEN12_Msk            (0x1000UL)                /*!< INTEN12 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN13_Pos            (13UL)                    /*!< INTEN13 (Bit 13)                                      */
#define EXTI_INTEN_INTEN13_Msk            (0x2000UL)                /*!< INTEN13 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN14_Pos            (14UL)                    /*!< INTEN14 (Bit 14)                                      */
#define EXTI_INTEN_INTEN14_Msk            (0x4000UL)                /*!< INTEN14 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN15_Pos            (15UL)                    /*!< INTEN15 (Bit 15)                                      */
#define EXTI_INTEN_INTEN15_Msk            (0x8000UL)                /*!< INTEN15 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN16_Pos            (16UL)                    /*!< INTEN16 (Bit 16)                                      */
#define EXTI_INTEN_INTEN16_Msk            (0x10000UL)               /*!< INTEN16 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN17_Pos            (17UL)                    /*!< INTEN17 (Bit 17)                                      */
#define EXTI_INTEN_INTEN17_Msk            (0x20000UL)               /*!< INTEN17 (Bitfield-Mask: 0x01)                         */
#define EXTI_INTEN_INTEN18_Pos            (18UL)                    /*!< INTEN18 (Bit 18)                                      */
#define EXTI_INTEN_INTEN18_Msk            (0x40000UL)               /*!< INTEN18 (Bitfield-Mask: 0x01)                         */
/* =========================================================  EVEN  ========================================================== */
#define EXTI_EVEN_EVEN0_Pos               (0UL)                     /*!< EVEN0 (Bit 0)                                         */
#define EXTI_EVEN_EVEN0_Msk               (0x1UL)                   /*!< EVEN0 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN1_Pos               (1UL)                     /*!< EVEN1 (Bit 1)                                         */
#define EXTI_EVEN_EVEN1_Msk               (0x2UL)                   /*!< EVEN1 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN2_Pos               (2UL)                     /*!< EVEN2 (Bit 2)                                         */
#define EXTI_EVEN_EVEN2_Msk               (0x4UL)                   /*!< EVEN2 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN3_Pos               (3UL)                     /*!< EVEN3 (Bit 3)                                         */
#define EXTI_EVEN_EVEN3_Msk               (0x8UL)                   /*!< EVEN3 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN4_Pos               (4UL)                     /*!< EVEN4 (Bit 4)                                         */
#define EXTI_EVEN_EVEN4_Msk               (0x10UL)                  /*!< EVEN4 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN5_Pos               (5UL)                     /*!< EVEN5 (Bit 5)                                         */
#define EXTI_EVEN_EVEN5_Msk               (0x20UL)                  /*!< EVEN5 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN6_Pos               (6UL)                     /*!< EVEN6 (Bit 6)                                         */
#define EXTI_EVEN_EVEN6_Msk               (0x40UL)                  /*!< EVEN6 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN7_Pos               (7UL)                     /*!< EVEN7 (Bit 7)                                         */
#define EXTI_EVEN_EVEN7_Msk               (0x80UL)                  /*!< EVEN7 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN8_Pos               (8UL)                     /*!< EVEN8 (Bit 8)                                         */
#define EXTI_EVEN_EVEN8_Msk               (0x100UL)                 /*!< EVEN8 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN9_Pos               (9UL)                     /*!< EVEN9 (Bit 9)                                         */
#define EXTI_EVEN_EVEN9_Msk               (0x200UL)                 /*!< EVEN9 (Bitfield-Mask: 0x01)                           */
#define EXTI_EVEN_EVEN10_Pos              (10UL)                    /*!< EVEN10 (Bit 10)                                       */
#define EXTI_EVEN_EVEN10_Msk              (0x400UL)                 /*!< EVEN10 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN11_Pos              (11UL)                    /*!< EVEN11 (Bit 11)                                       */
#define EXTI_EVEN_EVEN11_Msk              (0x800UL)                 /*!< EVEN11 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN12_Pos              (12UL)                    /*!< EVEN12 (Bit 12)                                       */
#define EXTI_EVEN_EVEN12_Msk              (0x1000UL)                /*!< EVEN12 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN13_Pos              (13UL)                    /*!< EVEN13 (Bit 13)                                       */
#define EXTI_EVEN_EVEN13_Msk              (0x2000UL)                /*!< EVEN13 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN14_Pos              (14UL)                    /*!< EVEN14 (Bit 14)                                       */
#define EXTI_EVEN_EVEN14_Msk              (0x4000UL)                /*!< EVEN14 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN15_Pos              (15UL)                    /*!< EVEN15 (Bit 15)                                       */
#define EXTI_EVEN_EVEN15_Msk              (0x8000UL)                /*!< EVEN15 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN16_Pos              (16UL)                    /*!< EVEN16 (Bit 16)                                       */
#define EXTI_EVEN_EVEN16_Msk              (0x10000UL)               /*!< EVEN16 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN17_Pos              (17UL)                    /*!< EVEN17 (Bit 17)                                       */
#define EXTI_EVEN_EVEN17_Msk              (0x20000UL)               /*!< EVEN17 (Bitfield-Mask: 0x01)                          */
#define EXTI_EVEN_EVEN18_Pos              (18UL)                    /*!< EVEN18 (Bit 18)                                       */
#define EXTI_EVEN_EVEN18_Msk              (0x40000UL)               /*!< EVEN18 (Bitfield-Mask: 0x01)                          */
/* =========================================================  RTEN  ========================================================== */
#define EXTI_RTEN_RTEN0_Pos               (0UL)                     /*!< RTEN0 (Bit 0)                                         */
#define EXTI_RTEN_RTEN0_Msk               (0x1UL)                   /*!< RTEN0 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN1_Pos               (1UL)                     /*!< RTEN1 (Bit 1)                                         */
#define EXTI_RTEN_RTEN1_Msk               (0x2UL)                   /*!< RTEN1 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN2_Pos               (2UL)                     /*!< RTEN2 (Bit 2)                                         */
#define EXTI_RTEN_RTEN2_Msk               (0x4UL)                   /*!< RTEN2 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN3_Pos               (3UL)                     /*!< RTEN3 (Bit 3)                                         */
#define EXTI_RTEN_RTEN3_Msk               (0x8UL)                   /*!< RTEN3 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN4_Pos               (4UL)                     /*!< RTEN4 (Bit 4)                                         */
#define EXTI_RTEN_RTEN4_Msk               (0x10UL)                  /*!< RTEN4 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN5_Pos               (5UL)                     /*!< RTEN5 (Bit 5)                                         */
#define EXTI_RTEN_RTEN5_Msk               (0x20UL)                  /*!< RTEN5 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN6_Pos               (6UL)                     /*!< RTEN6 (Bit 6)                                         */
#define EXTI_RTEN_RTEN6_Msk               (0x40UL)                  /*!< RTEN6 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN7_Pos               (7UL)                     /*!< RTEN7 (Bit 7)                                         */
#define EXTI_RTEN_RTEN7_Msk               (0x80UL)                  /*!< RTEN7 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN8_Pos               (8UL)                     /*!< RTEN8 (Bit 8)                                         */
#define EXTI_RTEN_RTEN8_Msk               (0x100UL)                 /*!< RTEN8 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN9_Pos               (9UL)                     /*!< RTEN9 (Bit 9)                                         */
#define EXTI_RTEN_RTEN9_Msk               (0x200UL)                 /*!< RTEN9 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTEN_RTEN10_Pos              (10UL)                    /*!< RTEN10 (Bit 10)                                       */
#define EXTI_RTEN_RTEN10_Msk              (0x400UL)                 /*!< RTEN10 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN11_Pos              (11UL)                    /*!< RTEN11 (Bit 11)                                       */
#define EXTI_RTEN_RTEN11_Msk              (0x800UL)                 /*!< RTEN11 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN12_Pos              (12UL)                    /*!< RTEN12 (Bit 12)                                       */
#define EXTI_RTEN_RTEN12_Msk              (0x1000UL)                /*!< RTEN12 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN13_Pos              (13UL)                    /*!< RTEN13 (Bit 13)                                       */
#define EXTI_RTEN_RTEN13_Msk              (0x2000UL)                /*!< RTEN13 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN14_Pos              (14UL)                    /*!< RTEN14 (Bit 14)                                       */
#define EXTI_RTEN_RTEN14_Msk              (0x4000UL)                /*!< RTEN14 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN15_Pos              (15UL)                    /*!< RTEN15 (Bit 15)                                       */
#define EXTI_RTEN_RTEN15_Msk              (0x8000UL)                /*!< RTEN15 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN16_Pos              (16UL)                    /*!< RTEN16 (Bit 16)                                       */
#define EXTI_RTEN_RTEN16_Msk              (0x10000UL)               /*!< RTEN16 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN17_Pos              (17UL)                    /*!< RTEN17 (Bit 17)                                       */
#define EXTI_RTEN_RTEN17_Msk              (0x20000UL)               /*!< RTEN17 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTEN_RTEN18_Pos              (18UL)                    /*!< RTEN18 (Bit 18)                                       */
#define EXTI_RTEN_RTEN18_Msk              (0x40000UL)               /*!< RTEN18 (Bitfield-Mask: 0x01)                          */
/* =========================================================  FTEN  ========================================================== */
#define EXTI_FTEN_FTEN0_Pos               (0UL)                     /*!< FTEN0 (Bit 0)                                         */
#define EXTI_FTEN_FTEN0_Msk               (0x1UL)                   /*!< FTEN0 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN1_Pos               (1UL)                     /*!< FTEN1 (Bit 1)                                         */
#define EXTI_FTEN_FTEN1_Msk               (0x2UL)                   /*!< FTEN1 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN2_Pos               (2UL)                     /*!< FTEN2 (Bit 2)                                         */
#define EXTI_FTEN_FTEN2_Msk               (0x4UL)                   /*!< FTEN2 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN3_Pos               (3UL)                     /*!< FTEN3 (Bit 3)                                         */
#define EXTI_FTEN_FTEN3_Msk               (0x8UL)                   /*!< FTEN3 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN4_Pos               (4UL)                     /*!< FTEN4 (Bit 4)                                         */
#define EXTI_FTEN_FTEN4_Msk               (0x10UL)                  /*!< FTEN4 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN5_Pos               (5UL)                     /*!< FTEN5 (Bit 5)                                         */
#define EXTI_FTEN_FTEN5_Msk               (0x20UL)                  /*!< FTEN5 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN6_Pos               (6UL)                     /*!< FTEN6 (Bit 6)                                         */
#define EXTI_FTEN_FTEN6_Msk               (0x40UL)                  /*!< FTEN6 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN7_Pos               (7UL)                     /*!< FTEN7 (Bit 7)                                         */
#define EXTI_FTEN_FTEN7_Msk               (0x80UL)                  /*!< FTEN7 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN8_Pos               (8UL)                     /*!< FTEN8 (Bit 8)                                         */
#define EXTI_FTEN_FTEN8_Msk               (0x100UL)                 /*!< FTEN8 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN9_Pos               (9UL)                     /*!< FTEN9 (Bit 9)                                         */
#define EXTI_FTEN_FTEN9_Msk               (0x200UL)                 /*!< FTEN9 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTEN_FTEN10_Pos              (10UL)                    /*!< FTEN10 (Bit 10)                                       */
#define EXTI_FTEN_FTEN10_Msk              (0x400UL)                 /*!< FTEN10 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN11_Pos              (11UL)                    /*!< FTEN11 (Bit 11)                                       */
#define EXTI_FTEN_FTEN11_Msk              (0x800UL)                 /*!< FTEN11 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN12_Pos              (12UL)                    /*!< FTEN12 (Bit 12)                                       */
#define EXTI_FTEN_FTEN12_Msk              (0x1000UL)                /*!< FTEN12 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN13_Pos              (13UL)                    /*!< FTEN13 (Bit 13)                                       */
#define EXTI_FTEN_FTEN13_Msk              (0x2000UL)                /*!< FTEN13 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN14_Pos              (14UL)                    /*!< FTEN14 (Bit 14)                                       */
#define EXTI_FTEN_FTEN14_Msk              (0x4000UL)                /*!< FTEN14 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN15_Pos              (15UL)                    /*!< FTEN15 (Bit 15)                                       */
#define EXTI_FTEN_FTEN15_Msk              (0x8000UL)                /*!< FTEN15 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN16_Pos              (16UL)                    /*!< FTEN16 (Bit 16)                                       */
#define EXTI_FTEN_FTEN16_Msk              (0x10000UL)               /*!< FTEN16 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN17_Pos              (17UL)                    /*!< FTEN17 (Bit 17)                                       */
#define EXTI_FTEN_FTEN17_Msk              (0x20000UL)               /*!< FTEN17 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTEN_FTEN18_Pos              (18UL)                    /*!< FTEN18 (Bit 18)                                       */
#define EXTI_FTEN_FTEN18_Msk              (0x40000UL)               /*!< FTEN18 (Bitfield-Mask: 0x01)                          */
/* =========================================================  SWIEV  ========================================================= */
#define EXTI_SWIEV_SWIEV0_Pos             (0UL)                     /*!< SWIEV0 (Bit 0)                                        */
#define EXTI_SWIEV_SWIEV0_Msk             (0x1UL)                   /*!< SWIEV0 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV1_Pos             (1UL)                     /*!< SWIEV1 (Bit 1)                                        */
#define EXTI_SWIEV_SWIEV1_Msk             (0x2UL)                   /*!< SWIEV1 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV2_Pos             (2UL)                     /*!< SWIEV2 (Bit 2)                                        */
#define EXTI_SWIEV_SWIEV2_Msk             (0x4UL)                   /*!< SWIEV2 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV3_Pos             (3UL)                     /*!< SWIEV3 (Bit 3)                                        */
#define EXTI_SWIEV_SWIEV3_Msk             (0x8UL)                   /*!< SWIEV3 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV4_Pos             (4UL)                     /*!< SWIEV4 (Bit 4)                                        */
#define EXTI_SWIEV_SWIEV4_Msk             (0x10UL)                  /*!< SWIEV4 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV5_Pos             (5UL)                     /*!< SWIEV5 (Bit 5)                                        */
#define EXTI_SWIEV_SWIEV5_Msk             (0x20UL)                  /*!< SWIEV5 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV6_Pos             (6UL)                     /*!< SWIEV6 (Bit 6)                                        */
#define EXTI_SWIEV_SWIEV6_Msk             (0x40UL)                  /*!< SWIEV6 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV7_Pos             (7UL)                     /*!< SWIEV7 (Bit 7)                                        */
#define EXTI_SWIEV_SWIEV7_Msk             (0x80UL)                  /*!< SWIEV7 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV8_Pos             (8UL)                     /*!< SWIEV8 (Bit 8)                                        */
#define EXTI_SWIEV_SWIEV8_Msk             (0x100UL)                 /*!< SWIEV8 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV9_Pos             (9UL)                     /*!< SWIEV9 (Bit 9)                                        */
#define EXTI_SWIEV_SWIEV9_Msk             (0x200UL)                 /*!< SWIEV9 (Bitfield-Mask: 0x01)                          */
#define EXTI_SWIEV_SWIEV10_Pos            (10UL)                    /*!< SWIEV10 (Bit 10)                                      */
#define EXTI_SWIEV_SWIEV10_Msk            (0x400UL)                 /*!< SWIEV10 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV11_Pos            (11UL)                    /*!< SWIEV11 (Bit 11)                                      */
#define EXTI_SWIEV_SWIEV11_Msk            (0x800UL)                 /*!< SWIEV11 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV12_Pos            (12UL)                    /*!< SWIEV12 (Bit 12)                                      */
#define EXTI_SWIEV_SWIEV12_Msk            (0x1000UL)                /*!< SWIEV12 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV13_Pos            (13UL)                    /*!< SWIEV13 (Bit 13)                                      */
#define EXTI_SWIEV_SWIEV13_Msk            (0x2000UL)                /*!< SWIEV13 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV14_Pos            (14UL)                    /*!< SWIEV14 (Bit 14)                                      */
#define EXTI_SWIEV_SWIEV14_Msk            (0x4000UL)                /*!< SWIEV14 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV15_Pos            (15UL)                    /*!< SWIEV15 (Bit 15)                                      */
#define EXTI_SWIEV_SWIEV15_Msk            (0x8000UL)                /*!< SWIEV15 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV16_Pos            (16UL)                    /*!< SWIEV16 (Bit 16)                                      */
#define EXTI_SWIEV_SWIEV16_Msk            (0x10000UL)               /*!< SWIEV16 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV17_Pos            (17UL)                    /*!< SWIEV17 (Bit 17)                                      */
#define EXTI_SWIEV_SWIEV17_Msk            (0x20000UL)               /*!< SWIEV17 (Bitfield-Mask: 0x01)                         */
#define EXTI_SWIEV_SWIEV18_Pos            (18UL)                    /*!< SWIEV18 (Bit 18)                                      */
#define EXTI_SWIEV_SWIEV18_Msk            (0x40000UL)               /*!< SWIEV18 (Bitfield-Mask: 0x01)                         */
/* ==========================================================  PD  =========================================================== */
#define EXTI_PD_PD0_Pos                   (0UL)                     /*!< PD0 (Bit 0)                                           */
#define EXTI_PD_PD0_Msk                   (0x1UL)                   /*!< PD0 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD1_Pos                   (1UL)                     /*!< PD1 (Bit 1)                                           */
#define EXTI_PD_PD1_Msk                   (0x2UL)                   /*!< PD1 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD2_Pos                   (2UL)                     /*!< PD2 (Bit 2)                                           */
#define EXTI_PD_PD2_Msk                   (0x4UL)                   /*!< PD2 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD3_Pos                   (3UL)                     /*!< PD3 (Bit 3)                                           */
#define EXTI_PD_PD3_Msk                   (0x8UL)                   /*!< PD3 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD4_Pos                   (4UL)                     /*!< PD4 (Bit 4)                                           */
#define EXTI_PD_PD4_Msk                   (0x10UL)                  /*!< PD4 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD5_Pos                   (5UL)                     /*!< PD5 (Bit 5)                                           */
#define EXTI_PD_PD5_Msk                   (0x20UL)                  /*!< PD5 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD6_Pos                   (6UL)                     /*!< PD6 (Bit 6)                                           */
#define EXTI_PD_PD6_Msk                   (0x40UL)                  /*!< PD6 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD7_Pos                   (7UL)                     /*!< PD7 (Bit 7)                                           */
#define EXTI_PD_PD7_Msk                   (0x80UL)                  /*!< PD7 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD8_Pos                   (8UL)                     /*!< PD8 (Bit 8)                                           */
#define EXTI_PD_PD8_Msk                   (0x100UL)                 /*!< PD8 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD9_Pos                   (9UL)                     /*!< PD9 (Bit 9)                                           */
#define EXTI_PD_PD9_Msk                   (0x200UL)                 /*!< PD9 (Bitfield-Mask: 0x01)                             */
#define EXTI_PD_PD10_Pos                  (10UL)                    /*!< PD10 (Bit 10)                                         */
#define EXTI_PD_PD10_Msk                  (0x400UL)                 /*!< PD10 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD11_Pos                  (11UL)                    /*!< PD11 (Bit 11)                                         */
#define EXTI_PD_PD11_Msk                  (0x800UL)                 /*!< PD11 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD12_Pos                  (12UL)                    /*!< PD12 (Bit 12)                                         */
#define EXTI_PD_PD12_Msk                  (0x1000UL)                /*!< PD12 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD13_Pos                  (13UL)                    /*!< PD13 (Bit 13)                                         */
#define EXTI_PD_PD13_Msk                  (0x2000UL)                /*!< PD13 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD14_Pos                  (14UL)                    /*!< PD14 (Bit 14)                                         */
#define EXTI_PD_PD14_Msk                  (0x4000UL)                /*!< PD14 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD15_Pos                  (15UL)                    /*!< PD15 (Bit 15)                                         */
#define EXTI_PD_PD15_Msk                  (0x8000UL)                /*!< PD15 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD16_Pos                  (16UL)                    /*!< PD16 (Bit 16)                                         */
#define EXTI_PD_PD16_Msk                  (0x10000UL)               /*!< PD16 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD17_Pos                  (17UL)                    /*!< PD17 (Bit 17)                                         */
#define EXTI_PD_PD17_Msk                  (0x20000UL)               /*!< PD17 (Bitfield-Mask: 0x01)                            */
#define EXTI_PD_PD18_Pos                  (18UL)                    /*!< PD18 (Bit 18)                                         */
#define EXTI_PD_PD18_Msk                  (0x40000UL)               /*!< PD18 (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                            FMC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  WS  =========================================================== */
#define FMC_WS_WSCNT_Pos                  (0UL)                     /*!< WSCNT (Bit 0)                                         */
#define FMC_WS_WSCNT_Msk                  (0x7UL)                   /*!< WSCNT (Bitfield-Mask: 0x07)                           */
/* =========================================================  KEY0  ========================================================== */
#define FMC_KEY0_KEY_Pos                  (0UL)                     /*!< KEY (Bit 0)                                           */
#define FMC_KEY0_KEY_Msk                  (0xffffffffUL)            /*!< KEY (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  OBKEY  ========================================================= */
#define FMC_OBKEY_OBKEY_Pos               (0UL)                     /*!< OBKEY (Bit 0)                                         */
#define FMC_OBKEY_OBKEY_Msk               (0xffffffffUL)            /*!< OBKEY (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  STAT0  ========================================================= */
#define FMC_STAT0_ENDF_Pos                (5UL)                     /*!< ENDF (Bit 5)                                          */
#define FMC_STAT0_ENDF_Msk                (0x20UL)                  /*!< ENDF (Bitfield-Mask: 0x01)                            */
#define FMC_STAT0_WPERR_Pos               (4UL)                     /*!< WPERR (Bit 4)                                         */
#define FMC_STAT0_WPERR_Msk               (0x10UL)                  /*!< WPERR (Bitfield-Mask: 0x01)                           */
#define FMC_STAT0_PGERR_Pos               (2UL)                     /*!< PGERR (Bit 2)                                         */
#define FMC_STAT0_PGERR_Msk               (0x4UL)                   /*!< PGERR (Bitfield-Mask: 0x01)                           */
#define FMC_STAT0_BUSY_Pos                (0UL)                     /*!< BUSY (Bit 0)                                          */
#define FMC_STAT0_BUSY_Msk                (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
/* =========================================================  CTL0  ========================================================== */
#define FMC_CTL0_ENDIE_Pos                (12UL)                    /*!< ENDIE (Bit 12)                                        */
#define FMC_CTL0_ENDIE_Msk                (0x1000UL)                /*!< ENDIE (Bitfield-Mask: 0x01)                           */
#define FMC_CTL0_ERRIE_Pos                (10UL)                    /*!< ERRIE (Bit 10)                                        */
#define FMC_CTL0_ERRIE_Msk                (0x400UL)                 /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define FMC_CTL0_OBWEN_Pos                (9UL)                     /*!< OBWEN (Bit 9)                                         */
#define FMC_CTL0_OBWEN_Msk                (0x200UL)                 /*!< OBWEN (Bitfield-Mask: 0x01)                           */
#define FMC_CTL0_LK_Pos                   (7UL)                     /*!< LK (Bit 7)                                            */
#define FMC_CTL0_LK_Msk                   (0x80UL)                  /*!< LK (Bitfield-Mask: 0x01)                              */
#define FMC_CTL0_START_Pos                (6UL)                     /*!< START (Bit 6)                                         */
#define FMC_CTL0_START_Msk                (0x40UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define FMC_CTL0_OBER_Pos                 (5UL)                     /*!< OBER (Bit 5)                                          */
#define FMC_CTL0_OBER_Msk                 (0x20UL)                  /*!< OBER (Bitfield-Mask: 0x01)                            */
#define FMC_CTL0_OBPG_Pos                 (4UL)                     /*!< OBPG (Bit 4)                                          */
#define FMC_CTL0_OBPG_Msk                 (0x10UL)                  /*!< OBPG (Bitfield-Mask: 0x01)                            */
#define FMC_CTL0_MER_Pos                  (2UL)                     /*!< MER (Bit 2)                                           */
#define FMC_CTL0_MER_Msk                  (0x4UL)                   /*!< MER (Bitfield-Mask: 0x01)                             */
#define FMC_CTL0_PER_Pos                  (1UL)                     /*!< PER (Bit 1)                                           */
#define FMC_CTL0_PER_Msk                  (0x2UL)                   /*!< PER (Bitfield-Mask: 0x01)                             */
#define FMC_CTL0_PG_Pos                   (0UL)                     /*!< PG (Bit 0)                                            */
#define FMC_CTL0_PG_Msk                   (0x1UL)                   /*!< PG (Bitfield-Mask: 0x01)                              */
/* =========================================================  ADDR0  ========================================================= */
#define FMC_ADDR0_ADDR_Pos                (0UL)                     /*!< ADDR (Bit 0)                                          */
#define FMC_ADDR0_ADDR_Msk                (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  OBSTAT  ========================================================= */
#define FMC_OBSTAT_OBERR_Pos              (0UL)                     /*!< OBERR (Bit 0)                                         */
#define FMC_OBSTAT_OBERR_Msk              (0x1UL)                   /*!< OBERR (Bitfield-Mask: 0x01)                           */
#define FMC_OBSTAT_SPC_Pos                (1UL)                     /*!< SPC (Bit 1)                                           */
#define FMC_OBSTAT_SPC_Msk                (0x2UL)                   /*!< SPC (Bitfield-Mask: 0x01)                             */
#define FMC_OBSTAT_USER_Pos               (2UL)                     /*!< USER (Bit 2)                                          */
#define FMC_OBSTAT_USER_Msk               (0x3fcUL)                 /*!< USER (Bitfield-Mask: 0xff)                            */
#define FMC_OBSTAT_DATA_Pos               (10UL)                    /*!< DATA (Bit 10)                                         */
#define FMC_OBSTAT_DATA_Msk               (0x3fffc00UL)             /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ==========================================================  WP  =========================================================== */
#define FMC_WP_WP_Pos                     (0UL)                     /*!< WP (Bit 0)                                            */
#define FMC_WP_WP_Msk                     (0xffffffffUL)            /*!< WP (Bitfield-Mask: 0xffffffff)                        */
/* ==========================================================  PID  ========================================================== */
#define FMC_PID_PID_Pos                   (0UL)                     /*!< PID (Bit 0)                                           */
#define FMC_PID_PID_Msk                   (0xffffffffUL)            /*!< PID (Bitfield-Mask: 0xffffffff)                       */


/* =========================================================================================================================== */
/* ================                                           FWDGT                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CTL  ========================================================== */
#define FWDGT_CTL_CMD_Pos                 (0UL)                     /*!< CMD (Bit 0)                                           */
#define FWDGT_CTL_CMD_Msk                 (0xffffUL)                /*!< CMD (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define FWDGT_PSC_PSC_Pos                 (0UL)                     /*!< PSC (Bit 0)                                           */
#define FWDGT_PSC_PSC_Msk                 (0x7UL)                   /*!< PSC (Bitfield-Mask: 0x07)                             */
/* ==========================================================  RLD  ========================================================== */
#define FWDGT_RLD_RLD_Pos                 (0UL)                     /*!< RLD (Bit 0)                                           */
#define FWDGT_RLD_RLD_Msk                 (0xfffUL)                 /*!< RLD (Bitfield-Mask: 0xfff)                            */
/* =========================================================  STAT  ========================================================== */
#define FWDGT_STAT_PUD_Pos                (0UL)                     /*!< PUD (Bit 0)                                           */
#define FWDGT_STAT_PUD_Msk                (0x1UL)                   /*!< PUD (Bitfield-Mask: 0x01)                             */
#define FWDGT_STAT_RUD_Pos                (1UL)                     /*!< RUD (Bit 1)                                           */
#define FWDGT_STAT_RUD_Msk                (0x2UL)                   /*!< RUD (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                           GPIOA                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTL0  ========================================================== */
#define GPIO_CTL0_CTL7_Pos               (30UL)                    /*!< CTL7 (Bit 30)                                         */
#define GPIO_CTL0_CTL7_Msk               (0xc0000000UL)            /*!< CTL7 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD7_Pos                (28UL)                    /*!< MD7 (Bit 28)                                          */
#define GPIO_CTL0_MD7_Msk                (0x30000000UL)            /*!< MD7 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL0_CTL6_Pos               (26UL)                    /*!< CTL6 (Bit 26)                                         */
#define GPIO_CTL0_CTL6_Msk               (0xc000000UL)             /*!< CTL6 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD6_Pos                (24UL)                    /*!< MD6 (Bit 24)                                          */
#define GPIO_CTL0_MD6_Msk                (0x3000000UL)             /*!< MD6 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL0_CTL5_Pos               (22UL)                    /*!< CTL5 (Bit 22)                                         */
#define GPIO_CTL0_CTL5_Msk               (0xc00000UL)              /*!< CTL5 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD5_Pos                (20UL)                    /*!< MD5 (Bit 20)                                          */
#define GPIO_CTL0_MD5_Msk                (0x300000UL)              /*!< MD5 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL0_CTL4_Pos               (18UL)                    /*!< CTL4 (Bit 18)                                         */
#define GPIO_CTL0_CTL4_Msk               (0xc0000UL)               /*!< CTL4 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD4_Pos                (16UL)                    /*!< MD4 (Bit 16)                                          */
#define GPIO_CTL0_MD4_Msk                (0x30000UL)               /*!< MD4 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL0_CTL3_Pos               (14UL)                    /*!< CTL3 (Bit 14)                                         */
#define GPIO_CTL0_CTL3_Msk               (0xc000UL)                /*!< CTL3 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD3_Pos                (12UL)                    /*!< MD3 (Bit 12)                                          */
#define GPIO_CTL0_MD3_Msk                (0x3000UL)                /*!< MD3 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL0_CTL2_Pos               (10UL)                    /*!< CTL2 (Bit 10)                                         */
#define GPIO_CTL0_CTL2_Msk               (0xc00UL)                 /*!< CTL2 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD2_Pos                (8UL)                     /*!< MD2 (Bit 8)                                           */
#define GPIO_CTL0_MD2_Msk                (0x300UL)                 /*!< MD2 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL0_CTL1_Pos               (6UL)                     /*!< CTL1 (Bit 6)                                          */
#define GPIO_CTL0_CTL1_Msk               (0xc0UL)                  /*!< CTL1 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD1_Pos                (4UL)                     /*!< MD1 (Bit 4)                                           */
#define GPIO_CTL0_MD1_Msk                (0x30UL)                  /*!< MD1 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL0_CTL0_Pos               (2UL)                     /*!< CTL0 (Bit 2)                                          */
#define GPIO_CTL0_CTL0_Msk               (0xcUL)                   /*!< CTL0 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL0_MD0_Pos                (0UL)                     /*!< MD0 (Bit 0)                                           */
#define GPIO_CTL0_MD0_Msk                (0x3UL)                   /*!< MD0 (Bitfield-Mask: 0x03)                             */
/* =========================================================  CTL1  ========================================================== */
#define GPIO_CTL1_CTL15_Pos              (30UL)                    /*!< CTL15 (Bit 30)                                        */
#define GPIO_CTL1_CTL15_Msk              (0xc0000000UL)            /*!< CTL15 (Bitfield-Mask: 0x03)                           */
#define GPIO_CTL1_MD15_Pos               (28UL)                    /*!< MD15 (Bit 28)                                         */
#define GPIO_CTL1_MD15_Msk               (0x30000000UL)            /*!< MD15 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_CTL14_Pos              (26UL)                    /*!< CTL14 (Bit 26)                                        */
#define GPIO_CTL1_CTL14_Msk              (0xc000000UL)             /*!< CTL14 (Bitfield-Mask: 0x03)                           */
#define GPIO_CTL1_MD14_Pos               (24UL)                    /*!< MD14 (Bit 24)                                         */
#define GPIO_CTL1_MD14_Msk               (0x3000000UL)             /*!< MD14 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_CTL13_Pos              (22UL)                    /*!< CTL13 (Bit 22)                                        */
#define GPIO_CTL1_CTL13_Msk              (0xc00000UL)              /*!< CTL13 (Bitfield-Mask: 0x03)                           */
#define GPIO_CTL1_MD13_Pos               (20UL)                    /*!< MD13 (Bit 20)                                         */
#define GPIO_CTL1_MD13_Msk               (0x300000UL)              /*!< MD13 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_CTL12_Pos              (18UL)                    /*!< CTL12 (Bit 18)                                        */
#define GPIO_CTL1_CTL12_Msk              (0xc0000UL)               /*!< CTL12 (Bitfield-Mask: 0x03)                           */
#define GPIO_CTL1_MD12_Pos               (16UL)                    /*!< MD12 (Bit 16)                                         */
#define GPIO_CTL1_MD12_Msk               (0x30000UL)               /*!< MD12 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_CTL11_Pos              (14UL)                    /*!< CTL11 (Bit 14)                                        */
#define GPIO_CTL1_CTL11_Msk              (0xc000UL)                /*!< CTL11 (Bitfield-Mask: 0x03)                           */
#define GPIO_CTL1_MD11_Pos               (12UL)                    /*!< MD11 (Bit 12)                                         */
#define GPIO_CTL1_MD11_Msk               (0x3000UL)                /*!< MD11 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_CTL10_Pos              (10UL)                    /*!< CTL10 (Bit 10)                                        */
#define GPIO_CTL1_CTL10_Msk              (0xc00UL)                 /*!< CTL10 (Bitfield-Mask: 0x03)                           */
#define GPIO_CTL1_MD10_Pos               (8UL)                     /*!< MD10 (Bit 8)                                          */
#define GPIO_CTL1_MD10_Msk               (0x300UL)                 /*!< MD10 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_CTL9_Pos               (6UL)                     /*!< CTL9 (Bit 6)                                          */
#define GPIO_CTL1_CTL9_Msk               (0xc0UL)                  /*!< CTL9 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_MD9_Pos                (4UL)                     /*!< MD9 (Bit 4)                                           */
#define GPIO_CTL1_MD9_Msk                (0x30UL)                  /*!< MD9 (Bitfield-Mask: 0x03)                             */
#define GPIO_CTL1_CTL8_Pos               (2UL)                     /*!< CTL8 (Bit 2)                                          */
#define GPIO_CTL1_CTL8_Msk               (0xcUL)                   /*!< CTL8 (Bitfield-Mask: 0x03)                            */
#define GPIO_CTL1_MD8_Pos                (0UL)                     /*!< MD8 (Bit 0)                                           */
#define GPIO_CTL1_MD8_Msk                (0x3UL)                   /*!< MD8 (Bitfield-Mask: 0x03)                             */
/* =========================================================  ISTAT  ========================================================= */
#define GPIO_ISTAT_ISTAT15_Pos           (15UL)                    /*!< ISTAT15 (Bit 15)                                      */
#define GPIO_ISTAT_ISTAT15_Msk           (0x8000UL)                /*!< ISTAT15 (Bitfield-Mask: 0x01)                         */
#define GPIO_ISTAT_ISTAT14_Pos           (14UL)                    /*!< ISTAT14 (Bit 14)                                      */
#define GPIO_ISTAT_ISTAT14_Msk           (0x4000UL)                /*!< ISTAT14 (Bitfield-Mask: 0x01)                         */
#define GPIO_ISTAT_ISTAT13_Pos           (13UL)                    /*!< ISTAT13 (Bit 13)                                      */
#define GPIO_ISTAT_ISTAT13_Msk           (0x2000UL)                /*!< ISTAT13 (Bitfield-Mask: 0x01)                         */
#define GPIO_ISTAT_ISTAT12_Pos           (12UL)                    /*!< ISTAT12 (Bit 12)                                      */
#define GPIO_ISTAT_ISTAT12_Msk           (0x1000UL)                /*!< ISTAT12 (Bitfield-Mask: 0x01)                         */
#define GPIO_ISTAT_ISTAT11_Pos           (11UL)                    /*!< ISTAT11 (Bit 11)                                      */
#define GPIO_ISTAT_ISTAT11_Msk           (0x800UL)                 /*!< ISTAT11 (Bitfield-Mask: 0x01)                         */
#define GPIO_ISTAT_ISTAT10_Pos           (10UL)                    /*!< ISTAT10 (Bit 10)                                      */
#define GPIO_ISTAT_ISTAT10_Msk           (0x400UL)                 /*!< ISTAT10 (Bitfield-Mask: 0x01)                         */
#define GPIO_ISTAT_ISTAT9_Pos            (9UL)                     /*!< ISTAT9 (Bit 9)                                        */
#define GPIO_ISTAT_ISTAT9_Msk            (0x200UL)                 /*!< ISTAT9 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT8_Pos            (8UL)                     /*!< ISTAT8 (Bit 8)                                        */
#define GPIO_ISTAT_ISTAT8_Msk            (0x100UL)                 /*!< ISTAT8 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT7_Pos            (7UL)                     /*!< ISTAT7 (Bit 7)                                        */
#define GPIO_ISTAT_ISTAT7_Msk            (0x80UL)                  /*!< ISTAT7 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT6_Pos            (6UL)                     /*!< ISTAT6 (Bit 6)                                        */
#define GPIO_ISTAT_ISTAT6_Msk            (0x40UL)                  /*!< ISTAT6 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT5_Pos            (5UL)                     /*!< ISTAT5 (Bit 5)                                        */
#define GPIO_ISTAT_ISTAT5_Msk            (0x20UL)                  /*!< ISTAT5 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT4_Pos            (4UL)                     /*!< ISTAT4 (Bit 4)                                        */
#define GPIO_ISTAT_ISTAT4_Msk            (0x10UL)                  /*!< ISTAT4 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT3_Pos            (3UL)                     /*!< ISTAT3 (Bit 3)                                        */
#define GPIO_ISTAT_ISTAT3_Msk            (0x8UL)                   /*!< ISTAT3 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT2_Pos            (2UL)                     /*!< ISTAT2 (Bit 2)                                        */
#define GPIO_ISTAT_ISTAT2_Msk            (0x4UL)                   /*!< ISTAT2 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT1_Pos            (1UL)                     /*!< ISTAT1 (Bit 1)                                        */
#define GPIO_ISTAT_ISTAT1_Msk            (0x2UL)                   /*!< ISTAT1 (Bitfield-Mask: 0x01)                          */
#define GPIO_ISTAT_ISTAT0_Pos            (0UL)                     /*!< ISTAT0 (Bit 0)                                        */
#define GPIO_ISTAT_ISTAT0_Msk            (0x1UL)                   /*!< ISTAT0 (Bitfield-Mask: 0x01)                          */
/* =========================================================  OCTL  ========================================================== */
#define GPIO_OCTL_OCTL15_Pos             (15UL)                    /*!< OCTL15 (Bit 15)                                       */
#define GPIO_OCTL_OCTL15_Msk             (0x8000UL)                /*!< OCTL15 (Bitfield-Mask: 0x01)                          */
#define GPIO_OCTL_OCTL14_Pos             (14UL)                    /*!< OCTL14 (Bit 14)                                       */
#define GPIO_OCTL_OCTL14_Msk             (0x4000UL)                /*!< OCTL14 (Bitfield-Mask: 0x01)                          */
#define GPIO_OCTL_OCTL13_Pos             (13UL)                    /*!< OCTL13 (Bit 13)                                       */
#define GPIO_OCTL_OCTL13_Msk             (0x2000UL)                /*!< OCTL13 (Bitfield-Mask: 0x01)                          */
#define GPIO_OCTL_OCTL12_Pos             (12UL)                    /*!< OCTL12 (Bit 12)                                       */
#define GPIO_OCTL_OCTL12_Msk             (0x1000UL)                /*!< OCTL12 (Bitfield-Mask: 0x01)                          */
#define GPIO_OCTL_OCTL11_Pos             (11UL)                    /*!< OCTL11 (Bit 11)                                       */
#define GPIO_OCTL_OCTL11_Msk             (0x800UL)                 /*!< OCTL11 (Bitfield-Mask: 0x01)                          */
#define GPIO_OCTL_OCTL10_Pos             (10UL)                    /*!< OCTL10 (Bit 10)                                       */
#define GPIO_OCTL_OCTL10_Msk             (0x400UL)                 /*!< OCTL10 (Bitfield-Mask: 0x01)                          */
#define GPIO_OCTL_OCTL9_Pos              (9UL)                     /*!< OCTL9 (Bit 9)                                         */
#define GPIO_OCTL_OCTL9_Msk              (0x200UL)                 /*!< OCTL9 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL8_Pos              (8UL)                     /*!< OCTL8 (Bit 8)                                         */
#define GPIO_OCTL_OCTL8_Msk              (0x100UL)                 /*!< OCTL8 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL7_Pos              (7UL)                     /*!< OCTL7 (Bit 7)                                         */
#define GPIO_OCTL_OCTL7_Msk              (0x80UL)                  /*!< OCTL7 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL6_Pos              (6UL)                     /*!< OCTL6 (Bit 6)                                         */
#define GPIO_OCTL_OCTL6_Msk              (0x40UL)                  /*!< OCTL6 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL5_Pos              (5UL)                     /*!< OCTL5 (Bit 5)                                         */
#define GPIO_OCTL_OCTL5_Msk              (0x20UL)                  /*!< OCTL5 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL4_Pos              (4UL)                     /*!< OCTL4 (Bit 4)                                         */
#define GPIO_OCTL_OCTL4_Msk              (0x10UL)                  /*!< OCTL4 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL3_Pos              (3UL)                     /*!< OCTL3 (Bit 3)                                         */
#define GPIO_OCTL_OCTL3_Msk              (0x8UL)                   /*!< OCTL3 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL2_Pos              (2UL)                     /*!< OCTL2 (Bit 2)                                         */
#define GPIO_OCTL_OCTL2_Msk              (0x4UL)                   /*!< OCTL2 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL1_Pos              (1UL)                     /*!< OCTL1 (Bit 1)                                         */
#define GPIO_OCTL_OCTL1_Msk              (0x2UL)                   /*!< OCTL1 (Bitfield-Mask: 0x01)                           */
#define GPIO_OCTL_OCTL0_Pos              (0UL)                     /*!< OCTL0 (Bit 0)                                         */
#define GPIO_OCTL_OCTL0_Msk              (0x1UL)                   /*!< OCTL0 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  BOP  ========================================================== */
#define GPIO_BOP_CR15_Pos                (31UL)                    /*!< CR15 (Bit 31)                                         */
#define GPIO_BOP_CR15_Msk                (0x80000000UL)            /*!< CR15 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_CR14_Pos                (30UL)                    /*!< CR14 (Bit 30)                                         */
#define GPIO_BOP_CR14_Msk                (0x40000000UL)            /*!< CR14 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_CR13_Pos                (29UL)                    /*!< CR13 (Bit 29)                                         */
#define GPIO_BOP_CR13_Msk                (0x20000000UL)            /*!< CR13 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_CR12_Pos                (28UL)                    /*!< CR12 (Bit 28)                                         */
#define GPIO_BOP_CR12_Msk                (0x10000000UL)            /*!< CR12 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_CR11_Pos                (27UL)                    /*!< CR11 (Bit 27)                                         */
#define GPIO_BOP_CR11_Msk                (0x8000000UL)             /*!< CR11 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_CR10_Pos                (26UL)                    /*!< CR10 (Bit 26)                                         */
#define GPIO_BOP_CR10_Msk                (0x4000000UL)             /*!< CR10 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_CR9_Pos                 (25UL)                    /*!< CR9 (Bit 25)                                          */
#define GPIO_BOP_CR9_Msk                 (0x2000000UL)             /*!< CR9 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR8_Pos                 (24UL)                    /*!< CR8 (Bit 24)                                          */
#define GPIO_BOP_CR8_Msk                 (0x1000000UL)             /*!< CR8 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR7_Pos                 (23UL)                    /*!< CR7 (Bit 23)                                          */
#define GPIO_BOP_CR7_Msk                 (0x800000UL)              /*!< CR7 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR6_Pos                 (22UL)                    /*!< CR6 (Bit 22)                                          */
#define GPIO_BOP_CR6_Msk                 (0x400000UL)              /*!< CR6 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR5_Pos                 (21UL)                    /*!< CR5 (Bit 21)                                          */
#define GPIO_BOP_CR5_Msk                 (0x200000UL)              /*!< CR5 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR4_Pos                 (20UL)                    /*!< CR4 (Bit 20)                                          */
#define GPIO_BOP_CR4_Msk                 (0x100000UL)              /*!< CR4 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR3_Pos                 (19UL)                    /*!< CR3 (Bit 19)                                          */
#define GPIO_BOP_CR3_Msk                 (0x80000UL)               /*!< CR3 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR2_Pos                 (18UL)                    /*!< CR2 (Bit 18)                                          */
#define GPIO_BOP_CR2_Msk                 (0x40000UL)               /*!< CR2 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR1_Pos                 (17UL)                    /*!< CR1 (Bit 17)                                          */
#define GPIO_BOP_CR1_Msk                 (0x20000UL)               /*!< CR1 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_CR0_Pos                 (16UL)                    /*!< CR0 (Bit 16)                                          */
#define GPIO_BOP_CR0_Msk                 (0x10000UL)               /*!< CR0 (Bitfield-Mask: 0x01)                             */
#define GPIO_BOP_BOP15_Pos               (15UL)                    /*!< BOP15 (Bit 15)                                        */
#define GPIO_BOP_BOP15_Msk               (0x8000UL)                /*!< BOP15 (Bitfield-Mask: 0x01)                           */
#define GPIO_BOP_BOP14_Pos               (14UL)                    /*!< BOP14 (Bit 14)                                        */
#define GPIO_BOP_BOP14_Msk               (0x4000UL)                /*!< BOP14 (Bitfield-Mask: 0x01)                           */
#define GPIO_BOP_BOP13_Pos               (13UL)                    /*!< BOP13 (Bit 13)                                        */
#define GPIO_BOP_BOP13_Msk               (0x2000UL)                /*!< BOP13 (Bitfield-Mask: 0x01)                           */
#define GPIO_BOP_BOP12_Pos               (12UL)                    /*!< BOP12 (Bit 12)                                        */
#define GPIO_BOP_BOP12_Msk               (0x1000UL)                /*!< BOP12 (Bitfield-Mask: 0x01)                           */
#define GPIO_BOP_BOP11_Pos               (11UL)                    /*!< BOP11 (Bit 11)                                        */
#define GPIO_BOP_BOP11_Msk               (0x800UL)                 /*!< BOP11 (Bitfield-Mask: 0x01)                           */
#define GPIO_BOP_BOP10_Pos               (10UL)                    /*!< BOP10 (Bit 10)                                        */
#define GPIO_BOP_BOP10_Msk               (0x400UL)                 /*!< BOP10 (Bitfield-Mask: 0x01)                           */
#define GPIO_BOP_BOP9_Pos                (9UL)                     /*!< BOP9 (Bit 9)                                          */
#define GPIO_BOP_BOP9_Msk                (0x200UL)                 /*!< BOP9 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP8_Pos                (8UL)                     /*!< BOP8 (Bit 8)                                          */
#define GPIO_BOP_BOP8_Msk                (0x100UL)                 /*!< BOP8 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP7_Pos                (7UL)                     /*!< BOP7 (Bit 7)                                          */
#define GPIO_BOP_BOP7_Msk                (0x80UL)                  /*!< BOP7 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP6_Pos                (6UL)                     /*!< BOP6 (Bit 6)                                          */
#define GPIO_BOP_BOP6_Msk                (0x40UL)                  /*!< BOP6 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP5_Pos                (5UL)                     /*!< BOP5 (Bit 5)                                          */
#define GPIO_BOP_BOP5_Msk                (0x20UL)                  /*!< BOP5 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP4_Pos                (4UL)                     /*!< BOP4 (Bit 4)                                          */
#define GPIO_BOP_BOP4_Msk                (0x10UL)                  /*!< BOP4 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP3_Pos                (3UL)                     /*!< BOP3 (Bit 3)                                          */
#define GPIO_BOP_BOP3_Msk                (0x8UL)                   /*!< BOP3 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP2_Pos                (2UL)                     /*!< BOP2 (Bit 2)                                          */
#define GPIO_BOP_BOP2_Msk                (0x4UL)                   /*!< BOP2 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP1_Pos                (1UL)                     /*!< BOP1 (Bit 1)                                          */
#define GPIO_BOP_BOP1_Msk                (0x2UL)                   /*!< BOP1 (Bitfield-Mask: 0x01)                            */
#define GPIO_BOP_BOP0_Pos                (0UL)                     /*!< BOP0 (Bit 0)                                          */
#define GPIO_BOP_BOP0_Msk                (0x1UL)                   /*!< BOP0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  BC  =========================================================== */
#define GPIO_BC_CR15_Pos                 (15UL)                    /*!< CR15 (Bit 15)                                         */
#define GPIO_BC_CR15_Msk                 (0x8000UL)                /*!< CR15 (Bitfield-Mask: 0x01)                            */
#define GPIO_BC_CR14_Pos                 (14UL)                    /*!< CR14 (Bit 14)                                         */
#define GPIO_BC_CR14_Msk                 (0x4000UL)                /*!< CR14 (Bitfield-Mask: 0x01)                            */
#define GPIO_BC_CR13_Pos                 (13UL)                    /*!< CR13 (Bit 13)                                         */
#define GPIO_BC_CR13_Msk                 (0x2000UL)                /*!< CR13 (Bitfield-Mask: 0x01)                            */
#define GPIO_BC_CR12_Pos                 (12UL)                    /*!< CR12 (Bit 12)                                         */
#define GPIO_BC_CR12_Msk                 (0x1000UL)                /*!< CR12 (Bitfield-Mask: 0x01)                            */
#define GPIO_BC_CR11_Pos                 (11UL)                    /*!< CR11 (Bit 11)                                         */
#define GPIO_BC_CR11_Msk                 (0x800UL)                 /*!< CR11 (Bitfield-Mask: 0x01)                            */
#define GPIO_BC_CR10_Pos                 (10UL)                    /*!< CR10 (Bit 10)                                         */
#define GPIO_BC_CR10_Msk                 (0x400UL)                 /*!< CR10 (Bitfield-Mask: 0x01)                            */
#define GPIO_BC_CR9_Pos                  (9UL)                     /*!< CR9 (Bit 9)                                           */
#define GPIO_BC_CR9_Msk                  (0x200UL)                 /*!< CR9 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR8_Pos                  (8UL)                     /*!< CR8 (Bit 8)                                           */
#define GPIO_BC_CR8_Msk                  (0x100UL)                 /*!< CR8 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR7_Pos                  (7UL)                     /*!< CR7 (Bit 7)                                           */
#define GPIO_BC_CR7_Msk                  (0x80UL)                  /*!< CR7 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR6_Pos                  (6UL)                     /*!< CR6 (Bit 6)                                           */
#define GPIO_BC_CR6_Msk                  (0x40UL)                  /*!< CR6 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR5_Pos                  (5UL)                     /*!< CR5 (Bit 5)                                           */
#define GPIO_BC_CR5_Msk                  (0x20UL)                  /*!< CR5 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR4_Pos                  (4UL)                     /*!< CR4 (Bit 4)                                           */
#define GPIO_BC_CR4_Msk                  (0x10UL)                  /*!< CR4 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR3_Pos                  (3UL)                     /*!< CR3 (Bit 3)                                           */
#define GPIO_BC_CR3_Msk                  (0x8UL)                   /*!< CR3 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR2_Pos                  (2UL)                     /*!< CR2 (Bit 2)                                           */
#define GPIO_BC_CR2_Msk                  (0x4UL)                   /*!< CR2 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR1_Pos                  (1UL)                     /*!< CR1 (Bit 1)                                           */
#define GPIO_BC_CR1_Msk                  (0x2UL)                   /*!< CR1 (Bitfield-Mask: 0x01)                             */
#define GPIO_BC_CR0_Pos                  (0UL)                     /*!< CR0 (Bit 0)                                           */
#define GPIO_BC_CR0_Msk                  (0x1UL)                   /*!< CR0 (Bitfield-Mask: 0x01)                             */
/* =========================================================  LOCK  ========================================================== */
#define GPIO_LOCK_LKK_Pos                (16UL)                    /*!< LKK (Bit 16)                                          */
#define GPIO_LOCK_LKK_Msk                (0x10000UL)               /*!< LKK (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK15_Pos               (15UL)                    /*!< LK15 (Bit 15)                                         */
#define GPIO_LOCK_LK15_Msk               (0x8000UL)                /*!< LK15 (Bitfield-Mask: 0x01)                            */
#define GPIO_LOCK_LK14_Pos               (14UL)                    /*!< LK14 (Bit 14)                                         */
#define GPIO_LOCK_LK14_Msk               (0x4000UL)                /*!< LK14 (Bitfield-Mask: 0x01)                            */
#define GPIO_LOCK_LK13_Pos               (13UL)                    /*!< LK13 (Bit 13)                                         */
#define GPIO_LOCK_LK13_Msk               (0x2000UL)                /*!< LK13 (Bitfield-Mask: 0x01)                            */
#define GPIO_LOCK_LK12_Pos               (12UL)                    /*!< LK12 (Bit 12)                                         */
#define GPIO_LOCK_LK12_Msk               (0x1000UL)                /*!< LK12 (Bitfield-Mask: 0x01)                            */
#define GPIO_LOCK_LK11_Pos               (11UL)                    /*!< LK11 (Bit 11)                                         */
#define GPIO_LOCK_LK11_Msk               (0x800UL)                 /*!< LK11 (Bitfield-Mask: 0x01)                            */
#define GPIO_LOCK_LK10_Pos               (10UL)                    /*!< LK10 (Bit 10)                                         */
#define GPIO_LOCK_LK10_Msk               (0x400UL)                 /*!< LK10 (Bitfield-Mask: 0x01)                            */
#define GPIO_LOCK_LK9_Pos                (9UL)                     /*!< LK9 (Bit 9)                                           */
#define GPIO_LOCK_LK9_Msk                (0x200UL)                 /*!< LK9 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK8_Pos                (8UL)                     /*!< LK8 (Bit 8)                                           */
#define GPIO_LOCK_LK8_Msk                (0x100UL)                 /*!< LK8 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK7_Pos                (7UL)                     /*!< LK7 (Bit 7)                                           */
#define GPIO_LOCK_LK7_Msk                (0x80UL)                  /*!< LK7 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK6_Pos                (6UL)                     /*!< LK6 (Bit 6)                                           */
#define GPIO_LOCK_LK6_Msk                (0x40UL)                  /*!< LK6 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK5_Pos                (5UL)                     /*!< LK5 (Bit 5)                                           */
#define GPIO_LOCK_LK5_Msk                (0x20UL)                  /*!< LK5 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK4_Pos                (4UL)                     /*!< LK4 (Bit 4)                                           */
#define GPIO_LOCK_LK4_Msk                (0x10UL)                  /*!< LK4 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK3_Pos                (3UL)                     /*!< LK3 (Bit 3)                                           */
#define GPIO_LOCK_LK3_Msk                (0x8UL)                   /*!< LK3 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK2_Pos                (2UL)                     /*!< LK2 (Bit 2)                                           */
#define GPIO_LOCK_LK2_Msk                (0x4UL)                   /*!< LK2 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK1_Pos                (1UL)                     /*!< LK1 (Bit 1)                                           */
#define GPIO_LOCK_LK1_Msk                (0x2UL)                   /*!< LK1 (Bitfield-Mask: 0x01)                             */
#define GPIO_LOCK_LK0_Pos                (0UL)                     /*!< LK0 (Bit 0)                                           */
#define GPIO_LOCK_LK0_Msk                (0x1UL)                   /*!< LK0 (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                           I2C0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTL0  ========================================================== */
#define I2C_CTL0_SRESET_Pos              (15UL)                    /*!< SRESET (Bit 15)                                       */
#define I2C_CTL0_SRESET_Msk              (0x8000UL)                /*!< SRESET (Bitfield-Mask: 0x01)                          */
#define I2C_CTL0_SALT_Pos                (13UL)                    /*!< SALT (Bit 13)                                         */
#define I2C_CTL0_SALT_Msk                (0x2000UL)                /*!< SALT (Bitfield-Mask: 0x01)                            */
#define I2C_CTL0_PECTRANS_Pos            (12UL)                    /*!< PECTRANS (Bit 12)                                     */
#define I2C_CTL0_PECTRANS_Msk            (0x1000UL)                /*!< PECTRANS (Bitfield-Mask: 0x01)                        */
#define I2C_CTL0_POAP_Pos                (11UL)                    /*!< POAP (Bit 11)                                         */
#define I2C_CTL0_POAP_Msk                (0x800UL)                 /*!< POAP (Bitfield-Mask: 0x01)                            */
#define I2C_CTL0_ACKEN_Pos               (10UL)                    /*!< ACKEN (Bit 10)                                        */
#define I2C_CTL0_ACKEN_Msk               (0x400UL)                 /*!< ACKEN (Bitfield-Mask: 0x01)                           */
#define I2C_CTL0_STOP_Pos                (9UL)                     /*!< STOP (Bit 9)                                          */
#define I2C_CTL0_STOP_Msk                (0x200UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2C_CTL0_START_Pos               (8UL)                     /*!< START (Bit 8)                                         */
#define I2C_CTL0_START_Msk               (0x100UL)                 /*!< START (Bitfield-Mask: 0x01)                           */
#define I2C_CTL0_SS_Pos                  (7UL)                     /*!< SS (Bit 7)                                            */
#define I2C_CTL0_SS_Msk                  (0x80UL)                  /*!< SS (Bitfield-Mask: 0x01)                              */
#define I2C_CTL0_GCEN_Pos                (6UL)                     /*!< GCEN (Bit 6)                                          */
#define I2C_CTL0_GCEN_Msk                (0x40UL)                  /*!< GCEN (Bitfield-Mask: 0x01)                            */
#define I2C_CTL0_PECEN_Pos               (5UL)                     /*!< PECEN (Bit 5)                                         */
#define I2C_CTL0_PECEN_Msk               (0x20UL)                  /*!< PECEN (Bitfield-Mask: 0x01)                           */
#define I2C_CTL0_ARPEN_Pos               (4UL)                     /*!< ARPEN (Bit 4)                                         */
#define I2C_CTL0_ARPEN_Msk               (0x10UL)                  /*!< ARPEN (Bitfield-Mask: 0x01)                           */
#define I2C_CTL0_SMBSEL_Pos              (3UL)                     /*!< SMBSEL (Bit 3)                                        */
#define I2C_CTL0_SMBSEL_Msk              (0x8UL)                   /*!< SMBSEL (Bitfield-Mask: 0x01)                          */
#define I2C_CTL0_SMBEN_Pos               (1UL)                     /*!< SMBEN (Bit 1)                                         */
#define I2C_CTL0_SMBEN_Msk               (0x2UL)                   /*!< SMBEN (Bitfield-Mask: 0x01)                           */
#define I2C_CTL0_I2CEN_Pos               (0UL)                     /*!< I2CEN (Bit 0)                                         */
#define I2C_CTL0_I2CEN_Msk               (0x1UL)                   /*!< I2CEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  CTL1  ========================================================== */
#define I2C_CTL1_DMALST_Pos              (12UL)                    /*!< DMALST (Bit 12)                                       */
#define I2C_CTL1_DMALST_Msk              (0x1000UL)                /*!< DMALST (Bitfield-Mask: 0x01)                          */
#define I2C_CTL1_DMAON_Pos               (11UL)                    /*!< DMAON (Bit 11)                                        */
#define I2C_CTL1_DMAON_Msk               (0x800UL)                 /*!< DMAON (Bitfield-Mask: 0x01)                           */
#define I2C_CTL1_BUFIE_Pos               (10UL)                    /*!< BUFIE (Bit 10)                                        */
#define I2C_CTL1_BUFIE_Msk               (0x400UL)                 /*!< BUFIE (Bitfield-Mask: 0x01)                           */
#define I2C_CTL1_EVIE_Pos                (9UL)                     /*!< EVIE (Bit 9)                                          */
#define I2C_CTL1_EVIE_Msk                (0x200UL)                 /*!< EVIE (Bitfield-Mask: 0x01)                            */
#define I2C_CTL1_ERRIE_Pos               (8UL)                     /*!< ERRIE (Bit 8)                                         */
#define I2C_CTL1_ERRIE_Msk               (0x100UL)                 /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define I2C_CTL1_I2CCLK_Pos              (0UL)                     /*!< I2CCLK (Bit 0)                                        */
#define I2C_CTL1_I2CCLK_Msk              (0x3fUL)                  /*!< I2CCLK (Bitfield-Mask: 0x3f)                          */
/* ========================================================  SADDR0  ========================================================= */
#define I2C_SADDR0_ADDFORMAT_Pos         (15UL)                    /*!< ADDFORMAT (Bit 15)                                    */
#define I2C_SADDR0_ADDFORMAT_Msk         (0x8000UL)                /*!< ADDFORMAT (Bitfield-Mask: 0x01)                       */
#define I2C_SADDR0_ADDRESS9_8_Pos        (8UL)                     /*!< ADDRESS9_8 (Bit 8)                                    */
#define I2C_SADDR0_ADDRESS9_8_Msk        (0x300UL)                 /*!< ADDRESS9_8 (Bitfield-Mask: 0x03)                      */
#define I2C_SADDR0_ADDRESS7_1_Pos        (1UL)                     /*!< ADDRESS7_1 (Bit 1)                                    */
#define I2C_SADDR0_ADDRESS7_1_Msk        (0xfeUL)                  /*!< ADDRESS7_1 (Bitfield-Mask: 0x7f)                      */
#define I2C_SADDR0_ADDRESS0_Pos          (0UL)                     /*!< ADDRESS0 (Bit 0)                                      */
#define I2C_SADDR0_ADDRESS0_Msk          (0x1UL)                   /*!< ADDRESS0 (Bitfield-Mask: 0x01)                        */
/* ========================================================  SADDR1  ========================================================= */
#define I2C_SADDR1_ADDRESS2_Pos          (1UL)                     /*!< ADDRESS2 (Bit 1)                                      */
#define I2C_SADDR1_ADDRESS2_Msk          (0xfeUL)                  /*!< ADDRESS2 (Bitfield-Mask: 0x7f)                        */
#define I2C_SADDR1_DUADEN_Pos            (0UL)                     /*!< DUADEN (Bit 0)                                        */
#define I2C_SADDR1_DUADEN_Msk            (0x1UL)                   /*!< DUADEN (Bitfield-Mask: 0x01)                          */
/* =========================================================  DATA  ========================================================== */
#define I2C_DATA_TRB_Pos                 (0UL)                     /*!< TRB (Bit 0)                                           */
#define I2C_DATA_TRB_Msk                 (0xffUL)                  /*!< TRB (Bitfield-Mask: 0xff)                             */
/* =========================================================  STAT0  ========================================================= */
#define I2C_STAT0_SMBALT_Pos             (15UL)                    /*!< SMBALT (Bit 15)                                       */
#define I2C_STAT0_SMBALT_Msk             (0x8000UL)                /*!< SMBALT (Bitfield-Mask: 0x01)                          */
#define I2C_STAT0_SMBTO_Pos              (14UL)                    /*!< SMBTO (Bit 14)                                        */
#define I2C_STAT0_SMBTO_Msk              (0x4000UL)                /*!< SMBTO (Bitfield-Mask: 0x01)                           */
#define I2C_STAT0_PECERR_Pos             (12UL)                    /*!< PECERR (Bit 12)                                       */
#define I2C_STAT0_PECERR_Msk             (0x1000UL)                /*!< PECERR (Bitfield-Mask: 0x01)                          */
#define I2C_STAT0_OUERR_Pos              (11UL)                    /*!< OUERR (Bit 11)                                        */
#define I2C_STAT0_OUERR_Msk              (0x800UL)                 /*!< OUERR (Bitfield-Mask: 0x01)                           */
#define I2C_STAT0_AERR_Pos               (10UL)                    /*!< AERR (Bit 10)                                         */
#define I2C_STAT0_AERR_Msk               (0x400UL)                 /*!< AERR (Bitfield-Mask: 0x01)                            */
#define I2C_STAT0_LOSTARB_Pos            (9UL)                     /*!< LOSTARB (Bit 9)                                       */
#define I2C_STAT0_LOSTARB_Msk            (0x200UL)                 /*!< LOSTARB (Bitfield-Mask: 0x01)                         */
#define I2C_STAT0_BERR_Pos               (8UL)                     /*!< BERR (Bit 8)                                          */
#define I2C_STAT0_BERR_Msk               (0x100UL)                 /*!< BERR (Bitfield-Mask: 0x01)                            */
#define I2C_STAT0_TBE_Pos                (7UL)                     /*!< TBE (Bit 7)                                           */
#define I2C_STAT0_TBE_Msk                (0x80UL)                  /*!< TBE (Bitfield-Mask: 0x01)                             */
#define I2C_STAT0_RBNE_Pos               (6UL)                     /*!< RBNE (Bit 6)                                          */
#define I2C_STAT0_RBNE_Msk               (0x40UL)                  /*!< RBNE (Bitfield-Mask: 0x01)                            */
#define I2C_STAT0_STPDET_Pos             (4UL)                     /*!< STPDET (Bit 4)                                        */
#define I2C_STAT0_STPDET_Msk             (0x10UL)                  /*!< STPDET (Bitfield-Mask: 0x01)                          */
#define I2C_STAT0_ADD10SEND_Pos          (3UL)                     /*!< ADD10SEND (Bit 3)                                     */
#define I2C_STAT0_ADD10SEND_Msk          (0x8UL)                   /*!< ADD10SEND (Bitfield-Mask: 0x01)                       */
#define I2C_STAT0_BTC_Pos                (2UL)                     /*!< BTC (Bit 2)                                           */
#define I2C_STAT0_BTC_Msk                (0x4UL)                   /*!< BTC (Bitfield-Mask: 0x01)                             */
#define I2C_STAT0_ADDSEND_Pos            (1UL)                     /*!< ADDSEND (Bit 1)                                       */
#define I2C_STAT0_ADDSEND_Msk            (0x2UL)                   /*!< ADDSEND (Bitfield-Mask: 0x01)                         */
#define I2C_STAT0_SBSEND_Pos             (0UL)                     /*!< SBSEND (Bit 0)                                        */
#define I2C_STAT0_SBSEND_Msk             (0x1UL)                   /*!< SBSEND (Bitfield-Mask: 0x01)                          */
/* =========================================================  STAT1  ========================================================= */
#define I2C_STAT1_PECV_Pos               (8UL)                     /*!< PECV (Bit 8)                                          */
#define I2C_STAT1_PECV_Msk               (0xff00UL)                /*!< PECV (Bitfield-Mask: 0xff)                            */
#define I2C_STAT1_DUMODF_Pos             (7UL)                     /*!< DUMODF (Bit 7)                                        */
#define I2C_STAT1_DUMODF_Msk             (0x80UL)                  /*!< DUMODF (Bitfield-Mask: 0x01)                          */
#define I2C_STAT1_HSTSMB_Pos             (6UL)                     /*!< HSTSMB (Bit 6)                                        */
#define I2C_STAT1_HSTSMB_Msk             (0x40UL)                  /*!< HSTSMB (Bitfield-Mask: 0x01)                          */
#define I2C_STAT1_DEFSMB_Pos             (5UL)                     /*!< DEFSMB (Bit 5)                                        */
#define I2C_STAT1_DEFSMB_Msk             (0x20UL)                  /*!< DEFSMB (Bitfield-Mask: 0x01)                          */
#define I2C_STAT1_RXGC_Pos               (4UL)                     /*!< RXGC (Bit 4)                                          */
#define I2C_STAT1_RXGC_Msk               (0x10UL)                  /*!< RXGC (Bitfield-Mask: 0x01)                            */
#define I2C_STAT1_TR_Pos                 (2UL)                     /*!< TR (Bit 2)                                            */
#define I2C_STAT1_TR_Msk                 (0x4UL)                   /*!< TR (Bitfield-Mask: 0x01)                              */
#define I2C_STAT1_I2CBSY_Pos             (1UL)                     /*!< I2CBSY (Bit 1)                                        */
#define I2C_STAT1_I2CBSY_Msk             (0x2UL)                   /*!< I2CBSY (Bitfield-Mask: 0x01)                          */
#define I2C_STAT1_MASTER_Pos             (0UL)                     /*!< MASTER (Bit 0)                                        */
#define I2C_STAT1_MASTER_Msk             (0x1UL)                   /*!< MASTER (Bitfield-Mask: 0x01)                          */
/* =========================================================  CKCFG  ========================================================= */
#define I2C_CKCFG_FAST_Pos               (15UL)                    /*!< FAST (Bit 15)                                         */
#define I2C_CKCFG_FAST_Msk               (0x8000UL)                /*!< FAST (Bitfield-Mask: 0x01)                            */
#define I2C_CKCFG_DTCY_Pos               (14UL)                    /*!< DTCY (Bit 14)                                         */
#define I2C_CKCFG_DTCY_Msk               (0x4000UL)                /*!< DTCY (Bitfield-Mask: 0x01)                            */
#define I2C_CKCFG_CLKC_Pos               (0UL)                     /*!< CLKC (Bit 0)                                          */
#define I2C_CKCFG_CLKC_Msk               (0xfffUL)                 /*!< CLKC (Bitfield-Mask: 0xfff)                           */
/* ==========================================================  RT  =========================================================== */
#define I2C_RT_RISETIME_Pos              (0UL)                     /*!< RISETIME (Bit 0)                                      */
#define I2C_RT_RISETIME_Msk              (0x3fUL)                  /*!< RISETIME (Bitfield-Mask: 0x3f)                        */


/* =========================================================================================================================== */
/* ================                                           ECLIC                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  CLICCFG  ======================================================== */
#define ECLIC_CLICCFG_NLBITS_Pos          (1UL)                     /*!< NLBITS (Bit 1)                                        */
#define ECLIC_CLICCFG_NLBITS_Msk          (0x1eUL)                  /*!< NLBITS (Bitfield-Mask: 0x0f)                          */
/* =======================================================  CLICINFO  ======================================================== */
#define ECLIC_CLICINFO_NUM_INTERRUPT_Pos  (0UL)                     /*!< NUM_INTERRUPT (Bit 0)                                 */
#define ECLIC_CLICINFO_NUM_INTERRUPT_Msk  (0x1fffUL)                /*!< NUM_INTERRUPT (Bitfield-Mask: 0x1fff)                 */
#define ECLIC_CLICINFO_VERSION_Pos        (13UL)                    /*!< VERSION (Bit 13)                                      */
#define ECLIC_CLICINFO_VERSION_Msk        (0x1fe000UL)              /*!< VERSION (Bitfield-Mask: 0xff)                         */
#define ECLIC_CLICINFO_CLICINTCTLBITS_Pos (21UL)                    /*!< CLICINTCTLBITS (Bit 21)                               */
#define ECLIC_CLICINFO_CLICINTCTLBITS_Msk (0x1e00000UL)             /*!< CLICINTCTLBITS (Bitfield-Mask: 0x0f)                  */
/* ==========================================================  MTH  ========================================================== */
#define ECLIC_MTH_MTH_Pos                 (0UL)                     /*!< MTH (Bit 0)                                           */
#define ECLIC_MTH_MTH_Msk                 (0xffUL)                  /*!< MTH (Bitfield-Mask: 0xff)                             */
/* ======================================================  CLICINTIP_0  ====================================================== */
#define ECLIC_CLICINTIP_0_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_0_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_1  ====================================================== */
#define ECLIC_CLICINTIP_1_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_1_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_2  ====================================================== */
#define ECLIC_CLICINTIP_2_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_2_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_3  ====================================================== */
#define ECLIC_CLICINTIP_3_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_3_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_4  ====================================================== */
#define ECLIC_CLICINTIP_4_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_4_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_5  ====================================================== */
#define ECLIC_CLICINTIP_5_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_5_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_6  ====================================================== */
#define ECLIC_CLICINTIP_6_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_6_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_7  ====================================================== */
#define ECLIC_CLICINTIP_7_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_7_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_8  ====================================================== */
#define ECLIC_CLICINTIP_8_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_8_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIP_9  ====================================================== */
#define ECLIC_CLICINTIP_9_IP_Pos          (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_9_IP_Msk          (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_10  ====================================================== */
#define ECLIC_CLICINTIP_10_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_10_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_11  ====================================================== */
#define ECLIC_CLICINTIP_11_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_11_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_12  ====================================================== */
#define ECLIC_CLICINTIP_12_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_12_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_13  ====================================================== */
#define ECLIC_CLICINTIP_13_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_13_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_14  ====================================================== */
#define ECLIC_CLICINTIP_14_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_14_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_15  ====================================================== */
#define ECLIC_CLICINTIP_15_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_15_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_16  ====================================================== */
#define ECLIC_CLICINTIP_16_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_16_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_17  ====================================================== */
#define ECLIC_CLICINTIP_17_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_17_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_18  ====================================================== */
#define ECLIC_CLICINTIP_18_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_18_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_19  ====================================================== */
#define ECLIC_CLICINTIP_19_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_19_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_20  ====================================================== */
#define ECLIC_CLICINTIP_20_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_20_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_21  ====================================================== */
#define ECLIC_CLICINTIP_21_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_21_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_22  ====================================================== */
#define ECLIC_CLICINTIP_22_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_22_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_23  ====================================================== */
#define ECLIC_CLICINTIP_23_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_23_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_24  ====================================================== */
#define ECLIC_CLICINTIP_24_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_24_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_25  ====================================================== */
#define ECLIC_CLICINTIP_25_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_25_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_26  ====================================================== */
#define ECLIC_CLICINTIP_26_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_26_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_27  ====================================================== */
#define ECLIC_CLICINTIP_27_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_27_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_28  ====================================================== */
#define ECLIC_CLICINTIP_28_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_28_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_29  ====================================================== */
#define ECLIC_CLICINTIP_29_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_29_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_30  ====================================================== */
#define ECLIC_CLICINTIP_30_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_30_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_31  ====================================================== */
#define ECLIC_CLICINTIP_31_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_31_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_32  ====================================================== */
#define ECLIC_CLICINTIP_32_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_32_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_33  ====================================================== */
#define ECLIC_CLICINTIP_33_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_33_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_34  ====================================================== */
#define ECLIC_CLICINTIP_34_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_34_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_35  ====================================================== */
#define ECLIC_CLICINTIP_35_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_35_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_36  ====================================================== */
#define ECLIC_CLICINTIP_36_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_36_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_37  ====================================================== */
#define ECLIC_CLICINTIP_37_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_37_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_38  ====================================================== */
#define ECLIC_CLICINTIP_38_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_38_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_39  ====================================================== */
#define ECLIC_CLICINTIP_39_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_39_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_40  ====================================================== */
#define ECLIC_CLICINTIP_40_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_40_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_41  ====================================================== */
#define ECLIC_CLICINTIP_41_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_41_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_42  ====================================================== */
#define ECLIC_CLICINTIP_42_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_42_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_43  ====================================================== */
#define ECLIC_CLICINTIP_43_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_43_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_44  ====================================================== */
#define ECLIC_CLICINTIP_44_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_44_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_45  ====================================================== */
#define ECLIC_CLICINTIP_45_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_45_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_46  ====================================================== */
#define ECLIC_CLICINTIP_46_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_46_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_47  ====================================================== */
#define ECLIC_CLICINTIP_47_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_47_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_48  ====================================================== */
#define ECLIC_CLICINTIP_48_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_48_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_49  ====================================================== */
#define ECLIC_CLICINTIP_49_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_49_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_50  ====================================================== */
#define ECLIC_CLICINTIP_50_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_50_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_51  ====================================================== */
#define ECLIC_CLICINTIP_51_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_51_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_52  ====================================================== */
#define ECLIC_CLICINTIP_52_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_52_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_53  ====================================================== */
#define ECLIC_CLICINTIP_53_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_53_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_54  ====================================================== */
#define ECLIC_CLICINTIP_54_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_54_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_55  ====================================================== */
#define ECLIC_CLICINTIP_55_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_55_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_56  ====================================================== */
#define ECLIC_CLICINTIP_56_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_56_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_57  ====================================================== */
#define ECLIC_CLICINTIP_57_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_57_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_58  ====================================================== */
#define ECLIC_CLICINTIP_58_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_58_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_59  ====================================================== */
#define ECLIC_CLICINTIP_59_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_59_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_60  ====================================================== */
#define ECLIC_CLICINTIP_60_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_60_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_61  ====================================================== */
#define ECLIC_CLICINTIP_61_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_61_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_62  ====================================================== */
#define ECLIC_CLICINTIP_62_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_62_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_63  ====================================================== */
#define ECLIC_CLICINTIP_63_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_63_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_64  ====================================================== */
#define ECLIC_CLICINTIP_64_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_64_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_65  ====================================================== */
#define ECLIC_CLICINTIP_65_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_65_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_66  ====================================================== */
#define ECLIC_CLICINTIP_66_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_66_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_67  ====================================================== */
#define ECLIC_CLICINTIP_67_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_67_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_68  ====================================================== */
#define ECLIC_CLICINTIP_68_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_68_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_69  ====================================================== */
#define ECLIC_CLICINTIP_69_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_69_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_70  ====================================================== */
#define ECLIC_CLICINTIP_70_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_70_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_71  ====================================================== */
#define ECLIC_CLICINTIP_71_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_71_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_72  ====================================================== */
#define ECLIC_CLICINTIP_72_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_72_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_73  ====================================================== */
#define ECLIC_CLICINTIP_73_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_73_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_74  ====================================================== */
#define ECLIC_CLICINTIP_74_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_74_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_75  ====================================================== */
#define ECLIC_CLICINTIP_75_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_75_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_76  ====================================================== */
#define ECLIC_CLICINTIP_76_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_76_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_77  ====================================================== */
#define ECLIC_CLICINTIP_77_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_77_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_78  ====================================================== */
#define ECLIC_CLICINTIP_78_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_78_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_79  ====================================================== */
#define ECLIC_CLICINTIP_79_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_79_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_80  ====================================================== */
#define ECLIC_CLICINTIP_80_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_80_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_81  ====================================================== */
#define ECLIC_CLICINTIP_81_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_81_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_82  ====================================================== */
#define ECLIC_CLICINTIP_82_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_82_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_83  ====================================================== */
#define ECLIC_CLICINTIP_83_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_83_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_84  ====================================================== */
#define ECLIC_CLICINTIP_84_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_84_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_85  ====================================================== */
#define ECLIC_CLICINTIP_85_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_85_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIP_86  ====================================================== */
#define ECLIC_CLICINTIP_86_IP_Pos         (0UL)                     /*!< IP (Bit 0)                                            */
#define ECLIC_CLICINTIP_86_IP_Msk         (0x1UL)                   /*!< IP (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_0  ====================================================== */
#define ECLIC_CLICINTIE_0_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_0_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_1  ====================================================== */
#define ECLIC_CLICINTIE_1_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_1_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_2  ====================================================== */
#define ECLIC_CLICINTIE_2_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_2_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_3  ====================================================== */
#define ECLIC_CLICINTIE_3_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_3_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_4  ====================================================== */
#define ECLIC_CLICINTIE_4_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_4_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_5  ====================================================== */
#define ECLIC_CLICINTIE_5_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_5_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_6  ====================================================== */
#define ECLIC_CLICINTIE_6_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_6_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_7  ====================================================== */
#define ECLIC_CLICINTIE_7_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_7_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_8  ====================================================== */
#define ECLIC_CLICINTIE_8_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_8_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ======================================================  CLICINTIE_9  ====================================================== */
#define ECLIC_CLICINTIE_9_IE_Pos          (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_9_IE_Msk          (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_10  ====================================================== */
#define ECLIC_CLICINTIE_10_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_10_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_11  ====================================================== */
#define ECLIC_CLICINTIE_11_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_11_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_12  ====================================================== */
#define ECLIC_CLICINTIE_12_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_12_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_13  ====================================================== */
#define ECLIC_CLICINTIE_13_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_13_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_14  ====================================================== */
#define ECLIC_CLICINTIE_14_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_14_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_15  ====================================================== */
#define ECLIC_CLICINTIE_15_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_15_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_16  ====================================================== */
#define ECLIC_CLICINTIE_16_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_16_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_17  ====================================================== */
#define ECLIC_CLICINTIE_17_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_17_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_18  ====================================================== */
#define ECLIC_CLICINTIE_18_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_18_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_19  ====================================================== */
#define ECLIC_CLICINTIE_19_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_19_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_20  ====================================================== */
#define ECLIC_CLICINTIE_20_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_20_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_21  ====================================================== */
#define ECLIC_CLICINTIE_21_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_21_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_22  ====================================================== */
#define ECLIC_CLICINTIE_22_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_22_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_23  ====================================================== */
#define ECLIC_CLICINTIE_23_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_23_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_24  ====================================================== */
#define ECLIC_CLICINTIE_24_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_24_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_25  ====================================================== */
#define ECLIC_CLICINTIE_25_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_25_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_26  ====================================================== */
#define ECLIC_CLICINTIE_26_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_26_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_27  ====================================================== */
#define ECLIC_CLICINTIE_27_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_27_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_28  ====================================================== */
#define ECLIC_CLICINTIE_28_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_28_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_29  ====================================================== */
#define ECLIC_CLICINTIE_29_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_29_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_30  ====================================================== */
#define ECLIC_CLICINTIE_30_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_30_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_31  ====================================================== */
#define ECLIC_CLICINTIE_31_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_31_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_32  ====================================================== */
#define ECLIC_CLICINTIE_32_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_32_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_33  ====================================================== */
#define ECLIC_CLICINTIE_33_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_33_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_34  ====================================================== */
#define ECLIC_CLICINTIE_34_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_34_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_35  ====================================================== */
#define ECLIC_CLICINTIE_35_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_35_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_36  ====================================================== */
#define ECLIC_CLICINTIE_36_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_36_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_37  ====================================================== */
#define ECLIC_CLICINTIE_37_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_37_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_38  ====================================================== */
#define ECLIC_CLICINTIE_38_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_38_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_39  ====================================================== */
#define ECLIC_CLICINTIE_39_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_39_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_40  ====================================================== */
#define ECLIC_CLICINTIE_40_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_40_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_41  ====================================================== */
#define ECLIC_CLICINTIE_41_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_41_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_42  ====================================================== */
#define ECLIC_CLICINTIE_42_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_42_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_43  ====================================================== */
#define ECLIC_CLICINTIE_43_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_43_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_44  ====================================================== */
#define ECLIC_CLICINTIE_44_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_44_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_45  ====================================================== */
#define ECLIC_CLICINTIE_45_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_45_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_46  ====================================================== */
#define ECLIC_CLICINTIE_46_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_46_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_47  ====================================================== */
#define ECLIC_CLICINTIE_47_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_47_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_48  ====================================================== */
#define ECLIC_CLICINTIE_48_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_48_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_49  ====================================================== */
#define ECLIC_CLICINTIE_49_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_49_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_50  ====================================================== */
#define ECLIC_CLICINTIE_50_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_50_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_51  ====================================================== */
#define ECLIC_CLICINTIE_51_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_51_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_52  ====================================================== */
#define ECLIC_CLICINTIE_52_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_52_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_53  ====================================================== */
#define ECLIC_CLICINTIE_53_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_53_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_54  ====================================================== */
#define ECLIC_CLICINTIE_54_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_54_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_55  ====================================================== */
#define ECLIC_CLICINTIE_55_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_55_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_56  ====================================================== */
#define ECLIC_CLICINTIE_56_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_56_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_57  ====================================================== */
#define ECLIC_CLICINTIE_57_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_57_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_58  ====================================================== */
#define ECLIC_CLICINTIE_58_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_58_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_59  ====================================================== */
#define ECLIC_CLICINTIE_59_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_59_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_60  ====================================================== */
#define ECLIC_CLICINTIE_60_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_60_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_61  ====================================================== */
#define ECLIC_CLICINTIE_61_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_61_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_62  ====================================================== */
#define ECLIC_CLICINTIE_62_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_62_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_63  ====================================================== */
#define ECLIC_CLICINTIE_63_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_63_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_64  ====================================================== */
#define ECLIC_CLICINTIE_64_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_64_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_65  ====================================================== */
#define ECLIC_CLICINTIE_65_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_65_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_66  ====================================================== */
#define ECLIC_CLICINTIE_66_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_66_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_67  ====================================================== */
#define ECLIC_CLICINTIE_67_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_67_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_68  ====================================================== */
#define ECLIC_CLICINTIE_68_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_68_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_69  ====================================================== */
#define ECLIC_CLICINTIE_69_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_69_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_70  ====================================================== */
#define ECLIC_CLICINTIE_70_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_70_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_71  ====================================================== */
#define ECLIC_CLICINTIE_71_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_71_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_72  ====================================================== */
#define ECLIC_CLICINTIE_72_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_72_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_73  ====================================================== */
#define ECLIC_CLICINTIE_73_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_73_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_74  ====================================================== */
#define ECLIC_CLICINTIE_74_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_74_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_75  ====================================================== */
#define ECLIC_CLICINTIE_75_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_75_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_76  ====================================================== */
#define ECLIC_CLICINTIE_76_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_76_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_77  ====================================================== */
#define ECLIC_CLICINTIE_77_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_77_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_78  ====================================================== */
#define ECLIC_CLICINTIE_78_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_78_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_79  ====================================================== */
#define ECLIC_CLICINTIE_79_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_79_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_80  ====================================================== */
#define ECLIC_CLICINTIE_80_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_80_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_81  ====================================================== */
#define ECLIC_CLICINTIE_81_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_81_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_82  ====================================================== */
#define ECLIC_CLICINTIE_82_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_82_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_83  ====================================================== */
#define ECLIC_CLICINTIE_83_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_83_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_84  ====================================================== */
#define ECLIC_CLICINTIE_84_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_84_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_85  ====================================================== */
#define ECLIC_CLICINTIE_85_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_85_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTIE_86  ====================================================== */
#define ECLIC_CLICINTIE_86_IE_Pos         (0UL)                     /*!< IE (Bit 0)                                            */
#define ECLIC_CLICINTIE_86_IE_Msk         (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =====================================================  CLICINTATTR_0  ===================================================== */
#define ECLIC_CLICINTATTR_0_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_0_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_0_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_0_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_1  ===================================================== */
#define ECLIC_CLICINTATTR_1_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_1_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_1_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_1_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_2  ===================================================== */
#define ECLIC_CLICINTATTR_2_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_2_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_2_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_2_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_3  ===================================================== */
#define ECLIC_CLICINTATTR_3_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_3_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_3_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_3_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_4  ===================================================== */
#define ECLIC_CLICINTATTR_4_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_4_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_4_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_4_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_5  ===================================================== */
#define ECLIC_CLICINTATTR_5_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_5_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_5_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_5_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_6  ===================================================== */
#define ECLIC_CLICINTATTR_6_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_6_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_6_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_6_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_7  ===================================================== */
#define ECLIC_CLICINTATTR_7_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_7_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_7_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_7_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_8  ===================================================== */
#define ECLIC_CLICINTATTR_8_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_8_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_8_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_8_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTATTR_9  ===================================================== */
#define ECLIC_CLICINTATTR_9_SHV_Pos       (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_9_SHV_Msk       (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_9_TRIG_Pos      (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_9_TRIG_Msk      (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_10  ===================================================== */
#define ECLIC_CLICINTATTR_10_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_10_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_10_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_10_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_11  ===================================================== */
#define ECLIC_CLICINTATTR_11_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_11_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_11_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_11_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_12  ===================================================== */
#define ECLIC_CLICINTATTR_12_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_12_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_12_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_12_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_13  ===================================================== */
#define ECLIC_CLICINTATTR_13_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_13_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_13_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_13_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_14  ===================================================== */
#define ECLIC_CLICINTATTR_14_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_14_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_14_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_14_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_15  ===================================================== */
#define ECLIC_CLICINTATTR_15_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_15_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_15_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_15_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_16  ===================================================== */
#define ECLIC_CLICINTATTR_16_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_16_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_16_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_16_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_17  ===================================================== */
#define ECLIC_CLICINTATTR_17_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_17_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_17_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_17_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_18  ===================================================== */
#define ECLIC_CLICINTATTR_18_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_18_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_18_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_18_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_19  ===================================================== */
#define ECLIC_CLICINTATTR_19_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_19_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_19_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_19_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_20  ===================================================== */
#define ECLIC_CLICINTATTR_20_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_20_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_20_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_20_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_21  ===================================================== */
#define ECLIC_CLICINTATTR_21_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_21_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_21_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_21_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_22  ===================================================== */
#define ECLIC_CLICINTATTR_22_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_22_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_22_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_22_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_23  ===================================================== */
#define ECLIC_CLICINTATTR_23_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_23_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_23_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_23_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_24  ===================================================== */
#define ECLIC_CLICINTATTR_24_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_24_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_24_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_24_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_25  ===================================================== */
#define ECLIC_CLICINTATTR_25_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_25_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_25_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_25_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_26  ===================================================== */
#define ECLIC_CLICINTATTR_26_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_26_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_26_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_26_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_27  ===================================================== */
#define ECLIC_CLICINTATTR_27_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_27_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_27_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_27_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_28  ===================================================== */
#define ECLIC_CLICINTATTR_28_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_28_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_28_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_28_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_29  ===================================================== */
#define ECLIC_CLICINTATTR_29_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_29_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_29_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_29_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_30  ===================================================== */
#define ECLIC_CLICINTATTR_30_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_30_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_30_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_30_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_31  ===================================================== */
#define ECLIC_CLICINTATTR_31_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_31_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_31_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_31_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_32  ===================================================== */
#define ECLIC_CLICINTATTR_32_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_32_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_32_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_32_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_33  ===================================================== */
#define ECLIC_CLICINTATTR_33_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_33_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_33_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_33_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_34  ===================================================== */
#define ECLIC_CLICINTATTR_34_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_34_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_34_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_34_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_35  ===================================================== */
#define ECLIC_CLICINTATTR_35_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_35_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_35_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_35_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_36  ===================================================== */
#define ECLIC_CLICINTATTR_36_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_36_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_36_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_36_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_37  ===================================================== */
#define ECLIC_CLICINTATTR_37_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_37_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_37_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_37_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_38  ===================================================== */
#define ECLIC_CLICINTATTR_38_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_38_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_38_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_38_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_39  ===================================================== */
#define ECLIC_CLICINTATTR_39_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_39_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_39_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_39_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_40  ===================================================== */
#define ECLIC_CLICINTATTR_40_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_40_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_40_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_40_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_41  ===================================================== */
#define ECLIC_CLICINTATTR_41_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_41_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_41_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_41_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_42  ===================================================== */
#define ECLIC_CLICINTATTR_42_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_42_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_42_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_42_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_43  ===================================================== */
#define ECLIC_CLICINTATTR_43_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_43_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_43_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_43_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_44  ===================================================== */
#define ECLIC_CLICINTATTR_44_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_44_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_44_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_44_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_45  ===================================================== */
#define ECLIC_CLICINTATTR_45_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_45_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_45_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_45_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_46  ===================================================== */
#define ECLIC_CLICINTATTR_46_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_46_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_46_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_46_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_47  ===================================================== */
#define ECLIC_CLICINTATTR_47_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_47_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_47_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_47_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_48  ===================================================== */
#define ECLIC_CLICINTATTR_48_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_48_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_48_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_48_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_49  ===================================================== */
#define ECLIC_CLICINTATTR_49_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_49_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_49_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_49_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_50  ===================================================== */
#define ECLIC_CLICINTATTR_50_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_50_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_50_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_50_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_51  ===================================================== */
#define ECLIC_CLICINTATTR_51_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_51_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_51_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_51_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_52  ===================================================== */
#define ECLIC_CLICINTATTR_52_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_52_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_52_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_52_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_53  ===================================================== */
#define ECLIC_CLICINTATTR_53_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_53_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_53_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_53_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_54  ===================================================== */
#define ECLIC_CLICINTATTR_54_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_54_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_54_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_54_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_55  ===================================================== */
#define ECLIC_CLICINTATTR_55_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_55_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_55_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_55_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_56  ===================================================== */
#define ECLIC_CLICINTATTR_56_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_56_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_56_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_56_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_57  ===================================================== */
#define ECLIC_CLICINTATTR_57_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_57_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_57_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_57_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_58  ===================================================== */
#define ECLIC_CLICINTATTR_58_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_58_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_58_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_58_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_59  ===================================================== */
#define ECLIC_CLICINTATTR_59_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_59_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_59_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_59_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_60  ===================================================== */
#define ECLIC_CLICINTATTR_60_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_60_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_60_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_60_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_61  ===================================================== */
#define ECLIC_CLICINTATTR_61_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_61_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_61_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_61_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_62  ===================================================== */
#define ECLIC_CLICINTATTR_62_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_62_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_62_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_62_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_63  ===================================================== */
#define ECLIC_CLICINTATTR_63_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_63_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_63_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_63_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_64  ===================================================== */
#define ECLIC_CLICINTATTR_64_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_64_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_64_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_64_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_65  ===================================================== */
#define ECLIC_CLICINTATTR_65_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_65_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_65_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_65_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_66  ===================================================== */
#define ECLIC_CLICINTATTR_66_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_66_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_66_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_66_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_67  ===================================================== */
#define ECLIC_CLICINTATTR_67_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_67_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_67_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_67_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_68  ===================================================== */
#define ECLIC_CLICINTATTR_68_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_68_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_68_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_68_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_69  ===================================================== */
#define ECLIC_CLICINTATTR_69_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_69_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_69_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_69_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_70  ===================================================== */
#define ECLIC_CLICINTATTR_70_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_70_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_70_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_70_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_71  ===================================================== */
#define ECLIC_CLICINTATTR_71_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_71_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_71_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_71_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_72  ===================================================== */
#define ECLIC_CLICINTATTR_72_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_72_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_72_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_72_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_73  ===================================================== */
#define ECLIC_CLICINTATTR_73_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_73_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_73_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_73_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_74  ===================================================== */
#define ECLIC_CLICINTATTR_74_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_74_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_74_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_74_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_75  ===================================================== */
#define ECLIC_CLICINTATTR_75_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_75_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_75_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_75_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_76  ===================================================== */
#define ECLIC_CLICINTATTR_76_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_76_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_76_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_76_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_77  ===================================================== */
#define ECLIC_CLICINTATTR_77_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_77_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_77_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_77_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_78  ===================================================== */
#define ECLIC_CLICINTATTR_78_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_78_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_78_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_78_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_79  ===================================================== */
#define ECLIC_CLICINTATTR_79_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_79_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_79_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_79_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_80  ===================================================== */
#define ECLIC_CLICINTATTR_80_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_80_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_80_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_80_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_81  ===================================================== */
#define ECLIC_CLICINTATTR_81_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_81_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_81_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_81_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_82  ===================================================== */
#define ECLIC_CLICINTATTR_82_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_82_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_82_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_82_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_83  ===================================================== */
#define ECLIC_CLICINTATTR_83_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_83_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_83_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_83_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_84  ===================================================== */
#define ECLIC_CLICINTATTR_84_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_84_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_84_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_84_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_85  ===================================================== */
#define ECLIC_CLICINTATTR_85_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_85_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_85_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_85_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* ====================================================  CLICINTATTR_86  ===================================================== */
#define ECLIC_CLICINTATTR_86_SHV_Pos      (0UL)                     /*!< SHV (Bit 0)                                           */
#define ECLIC_CLICINTATTR_86_SHV_Msk      (0x1UL)                   /*!< SHV (Bitfield-Mask: 0x01)                             */
#define ECLIC_CLICINTATTR_86_TRIG_Pos     (1UL)                     /*!< TRIG (Bit 1)                                          */
#define ECLIC_CLICINTATTR_86_TRIG_Msk     (0x6UL)                   /*!< TRIG (Bitfield-Mask: 0x03)                            */
/* =====================================================  CLICINTCTL_0  ====================================================== */
#define ECLIC_CLICINTCTL_0_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_0_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_1  ====================================================== */
#define ECLIC_CLICINTCTL_1_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_1_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_2  ====================================================== */
#define ECLIC_CLICINTCTL_2_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_2_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_3  ====================================================== */
#define ECLIC_CLICINTCTL_3_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_3_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_4  ====================================================== */
#define ECLIC_CLICINTCTL_4_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_4_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_5  ====================================================== */
#define ECLIC_CLICINTCTL_5_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_5_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_6  ====================================================== */
#define ECLIC_CLICINTCTL_6_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_6_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_7  ====================================================== */
#define ECLIC_CLICINTCTL_7_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_7_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_8  ====================================================== */
#define ECLIC_CLICINTCTL_8_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_8_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_9  ====================================================== */
#define ECLIC_CLICINTCTL_9_LEVEL_PRIORITY_Pos (0UL)                 /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_9_LEVEL_PRIORITY_Msk (0xffUL)              /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_10  ===================================================== */
#define ECLIC_CLICINTCTL_10_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_10_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_11  ===================================================== */
#define ECLIC_CLICINTCTL_11_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_11_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_12  ===================================================== */
#define ECLIC_CLICINTCTL_12_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_12_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_13  ===================================================== */
#define ECLIC_CLICINTCTL_13_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_13_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_14  ===================================================== */
#define ECLIC_CLICINTCTL_14_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_14_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_15  ===================================================== */
#define ECLIC_CLICINTCTL_15_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_15_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_16  ===================================================== */
#define ECLIC_CLICINTCTL_16_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_16_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_17  ===================================================== */
#define ECLIC_CLICINTCTL_17_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_17_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_18  ===================================================== */
#define ECLIC_CLICINTCTL_18_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_18_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_19  ===================================================== */
#define ECLIC_CLICINTCTL_19_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_19_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_20  ===================================================== */
#define ECLIC_CLICINTCTL_20_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_20_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_21  ===================================================== */
#define ECLIC_CLICINTCTL_21_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_21_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_22  ===================================================== */
#define ECLIC_CLICINTCTL_22_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_22_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_23  ===================================================== */
#define ECLIC_CLICINTCTL_23_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_23_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_24  ===================================================== */
#define ECLIC_CLICINTCTL_24_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_24_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_25  ===================================================== */
#define ECLIC_CLICINTCTL_25_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_25_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_26  ===================================================== */
#define ECLIC_CLICINTCTL_26_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_26_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_27  ===================================================== */
#define ECLIC_CLICINTCTL_27_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_27_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_28  ===================================================== */
#define ECLIC_CLICINTCTL_28_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_28_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_29  ===================================================== */
#define ECLIC_CLICINTCTL_29_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_29_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_30  ===================================================== */
#define ECLIC_CLICINTCTL_30_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_30_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_31  ===================================================== */
#define ECLIC_CLICINTCTL_31_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_31_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_32  ===================================================== */
#define ECLIC_CLICINTCTL_32_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_32_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_33  ===================================================== */
#define ECLIC_CLICINTCTL_33_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_33_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_34  ===================================================== */
#define ECLIC_CLICINTCTL_34_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_34_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_35  ===================================================== */
#define ECLIC_CLICINTCTL_35_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_35_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_36  ===================================================== */
#define ECLIC_CLICINTCTL_36_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_36_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_37  ===================================================== */
#define ECLIC_CLICINTCTL_37_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_37_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_38  ===================================================== */
#define ECLIC_CLICINTCTL_38_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_38_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_39  ===================================================== */
#define ECLIC_CLICINTCTL_39_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_39_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_40  ===================================================== */
#define ECLIC_CLICINTCTL_40_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_40_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_41  ===================================================== */
#define ECLIC_CLICINTCTL_41_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_41_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_42  ===================================================== */
#define ECLIC_CLICINTCTL_42_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_42_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_43  ===================================================== */
#define ECLIC_CLICINTCTL_43_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_43_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_44  ===================================================== */
#define ECLIC_CLICINTCTL_44_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_44_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_45  ===================================================== */
#define ECLIC_CLICINTCTL_45_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_45_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_46  ===================================================== */
#define ECLIC_CLICINTCTL_46_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_46_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_47  ===================================================== */
#define ECLIC_CLICINTCTL_47_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_47_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_48  ===================================================== */
#define ECLIC_CLICINTCTL_48_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_48_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_49  ===================================================== */
#define ECLIC_CLICINTCTL_49_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_49_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_50  ===================================================== */
#define ECLIC_CLICINTCTL_50_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_50_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_51  ===================================================== */
#define ECLIC_CLICINTCTL_51_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_51_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_52  ===================================================== */
#define ECLIC_CLICINTCTL_52_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_52_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_53  ===================================================== */
#define ECLIC_CLICINTCTL_53_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_53_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_54  ===================================================== */
#define ECLIC_CLICINTCTL_54_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_54_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_55  ===================================================== */
#define ECLIC_CLICINTCTL_55_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_55_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_56  ===================================================== */
#define ECLIC_CLICINTCTL_56_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_56_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_57  ===================================================== */
#define ECLIC_CLICINTCTL_57_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_57_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_58  ===================================================== */
#define ECLIC_CLICINTCTL_58_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_58_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_59  ===================================================== */
#define ECLIC_CLICINTCTL_59_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_59_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_60  ===================================================== */
#define ECLIC_CLICINTCTL_60_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_60_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_61  ===================================================== */
#define ECLIC_CLICINTCTL_61_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_61_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_62  ===================================================== */
#define ECLIC_CLICINTCTL_62_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_62_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_63  ===================================================== */
#define ECLIC_CLICINTCTL_63_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_63_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_64  ===================================================== */
#define ECLIC_CLICINTCTL_64_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_64_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_65  ===================================================== */
#define ECLIC_CLICINTCTL_65_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_65_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_66  ===================================================== */
#define ECLIC_CLICINTCTL_66_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_66_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_67  ===================================================== */
#define ECLIC_CLICINTCTL_67_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_67_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_68  ===================================================== */
#define ECLIC_CLICINTCTL_68_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_68_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_69  ===================================================== */
#define ECLIC_CLICINTCTL_69_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_69_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_70  ===================================================== */
#define ECLIC_CLICINTCTL_70_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_70_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_71  ===================================================== */
#define ECLIC_CLICINTCTL_71_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_71_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_72  ===================================================== */
#define ECLIC_CLICINTCTL_72_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_72_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_73  ===================================================== */
#define ECLIC_CLICINTCTL_73_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_73_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_74  ===================================================== */
#define ECLIC_CLICINTCTL_74_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_74_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_75  ===================================================== */
#define ECLIC_CLICINTCTL_75_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_75_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_76  ===================================================== */
#define ECLIC_CLICINTCTL_76_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_76_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_77  ===================================================== */
#define ECLIC_CLICINTCTL_77_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_77_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_78  ===================================================== */
#define ECLIC_CLICINTCTL_78_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_78_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_79  ===================================================== */
#define ECLIC_CLICINTCTL_79_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_79_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_80  ===================================================== */
#define ECLIC_CLICINTCTL_80_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_80_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_81  ===================================================== */
#define ECLIC_CLICINTCTL_81_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_81_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_82  ===================================================== */
#define ECLIC_CLICINTCTL_82_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_82_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_83  ===================================================== */
#define ECLIC_CLICINTCTL_83_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_83_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_84  ===================================================== */
#define ECLIC_CLICINTCTL_84_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_84_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_85  ===================================================== */
#define ECLIC_CLICINTCTL_85_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_85_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */
/* =====================================================  CLICINTCTL_86  ===================================================== */
#define ECLIC_CLICINTCTL_86_LEVEL_PRIORITY_Pos (0UL)                /*!< LEVEL_PRIORITY (Bit 0)                                */
#define ECLIC_CLICINTCTL_86_LEVEL_PRIORITY_Msk (0xffUL)             /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff)                  */


/* =========================================================================================================================== */
/* ================                                            PMU                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CTL  ========================================================== */
#define PMU_CTL_BKPWEN_Pos                (8UL)                     /*!< BKPWEN (Bit 8)                                        */
#define PMU_CTL_BKPWEN_Msk                (0x100UL)                 /*!< BKPWEN (Bitfield-Mask: 0x01)                          */
#define PMU_CTL_LVDT_Pos                  (5UL)                     /*!< LVDT (Bit 5)                                          */
#define PMU_CTL_LVDT_Msk                  (0xe0UL)                  /*!< LVDT (Bitfield-Mask: 0x07)                            */
#define PMU_CTL_LVDEN_Pos                 (4UL)                     /*!< LVDEN (Bit 4)                                         */
#define PMU_CTL_LVDEN_Msk                 (0x10UL)                  /*!< LVDEN (Bitfield-Mask: 0x01)                           */
#define PMU_CTL_STBRST_Pos                (3UL)                     /*!< STBRST (Bit 3)                                        */
#define PMU_CTL_STBRST_Msk                (0x8UL)                   /*!< STBRST (Bitfield-Mask: 0x01)                          */
#define PMU_CTL_WURST_Pos                 (2UL)                     /*!< WURST (Bit 2)                                         */
#define PMU_CTL_WURST_Msk                 (0x4UL)                   /*!< WURST (Bitfield-Mask: 0x01)                           */
#define PMU_CTL_STBMOD_Pos                (1UL)                     /*!< STBMOD (Bit 1)                                        */
#define PMU_CTL_STBMOD_Msk                (0x2UL)                   /*!< STBMOD (Bitfield-Mask: 0x01)                          */
#define PMU_CTL_LDOLP_Pos                 (0UL)                     /*!< LDOLP (Bit 0)                                         */
#define PMU_CTL_LDOLP_Msk                 (0x1UL)                   /*!< LDOLP (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CS  =========================================================== */
#define PMU_CS_WUPEN_Pos                  (8UL)                     /*!< WUPEN (Bit 8)                                         */
#define PMU_CS_WUPEN_Msk                  (0x100UL)                 /*!< WUPEN (Bitfield-Mask: 0x01)                           */
#define PMU_CS_LVDF_Pos                   (2UL)                     /*!< LVDF (Bit 2)                                          */
#define PMU_CS_LVDF_Msk                   (0x4UL)                   /*!< LVDF (Bitfield-Mask: 0x01)                            */
#define PMU_CS_STBF_Pos                   (1UL)                     /*!< STBF (Bit 1)                                          */
#define PMU_CS_STBF_Msk                   (0x2UL)                   /*!< STBF (Bitfield-Mask: 0x01)                            */
#define PMU_CS_WUF_Pos                    (0UL)                     /*!< WUF (Bit 0)                                           */
#define PMU_CS_WUF_Msk                    (0x1UL)                   /*!< WUF (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            RCU                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CTL  ========================================================== */
#define RCU_CTL_IRC8MEN_Pos               (0UL)                     /*!< IRC8MEN (Bit 0)                                       */
#define RCU_CTL_IRC8MEN_Msk               (0x1UL)                   /*!< IRC8MEN (Bitfield-Mask: 0x01)                         */
#define RCU_CTL_IRC8MSTB_Pos              (1UL)                     /*!< IRC8MSTB (Bit 1)                                      */
#define RCU_CTL_IRC8MSTB_Msk              (0x2UL)                   /*!< IRC8MSTB (Bitfield-Mask: 0x01)                        */
#define RCU_CTL_IRC8MADJ_Pos              (3UL)                     /*!< IRC8MADJ (Bit 3)                                      */
#define RCU_CTL_IRC8MADJ_Msk              (0xf8UL)                  /*!< IRC8MADJ (Bitfield-Mask: 0x1f)                        */
#define RCU_CTL_IRC8MCALIB_Pos            (8UL)                     /*!< IRC8MCALIB (Bit 8)                                    */
#define RCU_CTL_IRC8MCALIB_Msk            (0xff00UL)                /*!< IRC8MCALIB (Bitfield-Mask: 0xff)                      */
#define RCU_CTL_HXTALEN_Pos               (16UL)                    /*!< HXTALEN (Bit 16)                                      */
#define RCU_CTL_HXTALEN_Msk               (0x10000UL)               /*!< HXTALEN (Bitfield-Mask: 0x01)                         */
#define RCU_CTL_HXTALSTB_Pos              (17UL)                    /*!< HXTALSTB (Bit 17)                                     */
#define RCU_CTL_HXTALSTB_Msk              (0x20000UL)               /*!< HXTALSTB (Bitfield-Mask: 0x01)                        */
#define RCU_CTL_HXTALBPS_Pos              (18UL)                    /*!< HXTALBPS (Bit 18)                                     */
#define RCU_CTL_HXTALBPS_Msk              (0x40000UL)               /*!< HXTALBPS (Bitfield-Mask: 0x01)                        */
#define RCU_CTL_CKMEN_Pos                 (19UL)                    /*!< CKMEN (Bit 19)                                        */
#define RCU_CTL_CKMEN_Msk                 (0x80000UL)               /*!< CKMEN (Bitfield-Mask: 0x01)                           */
#define RCU_CTL_PLLEN_Pos                 (24UL)                    /*!< PLLEN (Bit 24)                                        */
#define RCU_CTL_PLLEN_Msk                 (0x1000000UL)             /*!< PLLEN (Bitfield-Mask: 0x01)                           */
#define RCU_CTL_PLLSTB_Pos                (25UL)                    /*!< PLLSTB (Bit 25)                                       */
#define RCU_CTL_PLLSTB_Msk                (0x2000000UL)             /*!< PLLSTB (Bitfield-Mask: 0x01)                          */
#define RCU_CTL_PLL1EN_Pos                (26UL)                    /*!< PLL1EN (Bit 26)                                       */
#define RCU_CTL_PLL1EN_Msk                (0x4000000UL)             /*!< PLL1EN (Bitfield-Mask: 0x01)                          */
#define RCU_CTL_PLL1STB_Pos               (27UL)                    /*!< PLL1STB (Bit 27)                                      */
#define RCU_CTL_PLL1STB_Msk               (0x8000000UL)             /*!< PLL1STB (Bitfield-Mask: 0x01)                         */
#define RCU_CTL_PLL2EN_Pos                (28UL)                    /*!< PLL2EN (Bit 28)                                       */
#define RCU_CTL_PLL2EN_Msk                (0x10000000UL)            /*!< PLL2EN (Bitfield-Mask: 0x01)                          */
#define RCU_CTL_PLL2STB_Pos               (29UL)                    /*!< PLL2STB (Bit 29)                                      */
#define RCU_CTL_PLL2STB_Msk               (0x20000000UL)            /*!< PLL2STB (Bitfield-Mask: 0x01)                         */
/* =========================================================  CFG0  ========================================================== */
#define RCU_CFG0_SCS_Pos                  (0UL)                     /*!< SCS (Bit 0)                                           */
#define RCU_CFG0_SCS_Msk                  (0x3UL)                   /*!< SCS (Bitfield-Mask: 0x03)                             */
#define RCU_CFG0_SCSS_Pos                 (2UL)                     /*!< SCSS (Bit 2)                                          */
#define RCU_CFG0_SCSS_Msk                 (0xcUL)                   /*!< SCSS (Bitfield-Mask: 0x03)                            */
#define RCU_CFG0_AHBPSC_Pos               (4UL)                     /*!< AHBPSC (Bit 4)                                        */
#define RCU_CFG0_AHBPSC_Msk               (0xf0UL)                  /*!< AHBPSC (Bitfield-Mask: 0x0f)                          */
#define RCU_CFG0_APB1PSC_Pos              (8UL)                     /*!< APB1PSC (Bit 8)                                       */
#define RCU_CFG0_APB1PSC_Msk              (0x700UL)                 /*!< APB1PSC (Bitfield-Mask: 0x07)                         */
#define RCU_CFG0_APB2PSC_Pos              (11UL)                    /*!< APB2PSC (Bit 11)                                      */
#define RCU_CFG0_APB2PSC_Msk              (0x3800UL)                /*!< APB2PSC (Bitfield-Mask: 0x07)                         */
#define RCU_CFG0_ADCPSC_1_0_Pos           (14UL)                    /*!< ADCPSC_1_0 (Bit 14)                                   */
#define RCU_CFG0_ADCPSC_1_0_Msk           (0xc000UL)                /*!< ADCPSC_1_0 (Bitfield-Mask: 0x03)                      */
#define RCU_CFG0_PLLSEL_Pos               (16UL)                    /*!< PLLSEL (Bit 16)                                       */
#define RCU_CFG0_PLLSEL_Msk               (0x10000UL)               /*!< PLLSEL (Bitfield-Mask: 0x01)                          */
#define RCU_CFG0_PREDV0_LSB_Pos           (17UL)                    /*!< PREDV0_LSB (Bit 17)                                   */
#define RCU_CFG0_PREDV0_LSB_Msk           (0x20000UL)               /*!< PREDV0_LSB (Bitfield-Mask: 0x01)                      */
#define RCU_CFG0_PLLMF_3_0_Pos            (18UL)                    /*!< PLLMF_3_0 (Bit 18)                                    */
#define RCU_CFG0_PLLMF_3_0_Msk            (0x3c0000UL)              /*!< PLLMF_3_0 (Bitfield-Mask: 0x0f)                       */
#define RCU_CFG0_USBFSPSC_Pos             (22UL)                    /*!< USBFSPSC (Bit 22)                                     */
#define RCU_CFG0_USBFSPSC_Msk             (0xc00000UL)              /*!< USBFSPSC (Bitfield-Mask: 0x03)                        */
#define RCU_CFG0_CKOUT0SEL_Pos            (24UL)                    /*!< CKOUT0SEL (Bit 24)                                    */
#define RCU_CFG0_CKOUT0SEL_Msk            (0xf000000UL)             /*!< CKOUT0SEL (Bitfield-Mask: 0x0f)                       */
#define RCU_CFG0_ADCPSC_2_Pos             (28UL)                    /*!< ADCPSC_2 (Bit 28)                                     */
#define RCU_CFG0_ADCPSC_2_Msk             (0x10000000UL)            /*!< ADCPSC_2 (Bitfield-Mask: 0x01)                        */
#define RCU_CFG0_PLLMF_4_Pos              (29UL)                    /*!< PLLMF_4 (Bit 29)                                      */
#define RCU_CFG0_PLLMF_4_Msk              (0x20000000UL)            /*!< PLLMF_4 (Bitfield-Mask: 0x01)                         */
/* ==========================================================  INT  ========================================================== */
#define RCU_INT_IRC40KSTBIF_Pos           (0UL)                     /*!< IRC40KSTBIF (Bit 0)                                   */
#define RCU_INT_IRC40KSTBIF_Msk           (0x1UL)                   /*!< IRC40KSTBIF (Bitfield-Mask: 0x01)                     */
#define RCU_INT_LXTALSTBIF_Pos            (1UL)                     /*!< LXTALSTBIF (Bit 1)                                    */
#define RCU_INT_LXTALSTBIF_Msk            (0x2UL)                   /*!< LXTALSTBIF (Bitfield-Mask: 0x01)                      */
#define RCU_INT_IRC8MSTBIF_Pos            (2UL)                     /*!< IRC8MSTBIF (Bit 2)                                    */
#define RCU_INT_IRC8MSTBIF_Msk            (0x4UL)                   /*!< IRC8MSTBIF (Bitfield-Mask: 0x01)                      */
#define RCU_INT_HXTALSTBIF_Pos            (3UL)                     /*!< HXTALSTBIF (Bit 3)                                    */
#define RCU_INT_HXTALSTBIF_Msk            (0x8UL)                   /*!< HXTALSTBIF (Bitfield-Mask: 0x01)                      */
#define RCU_INT_PLLSTBIF_Pos              (4UL)                     /*!< PLLSTBIF (Bit 4)                                      */
#define RCU_INT_PLLSTBIF_Msk              (0x10UL)                  /*!< PLLSTBIF (Bitfield-Mask: 0x01)                        */
#define RCU_INT_PLL1STBIF_Pos             (5UL)                     /*!< PLL1STBIF (Bit 5)                                     */
#define RCU_INT_PLL1STBIF_Msk             (0x20UL)                  /*!< PLL1STBIF (Bitfield-Mask: 0x01)                       */
#define RCU_INT_PLL2STBIF_Pos             (6UL)                     /*!< PLL2STBIF (Bit 6)                                     */
#define RCU_INT_PLL2STBIF_Msk             (0x40UL)                  /*!< PLL2STBIF (Bitfield-Mask: 0x01)                       */
#define RCU_INT_CKMIF_Pos                 (7UL)                     /*!< CKMIF (Bit 7)                                         */
#define RCU_INT_CKMIF_Msk                 (0x80UL)                  /*!< CKMIF (Bitfield-Mask: 0x01)                           */
#define RCU_INT_IRC40KSTBIE_Pos           (8UL)                     /*!< IRC40KSTBIE (Bit 8)                                   */
#define RCU_INT_IRC40KSTBIE_Msk           (0x100UL)                 /*!< IRC40KSTBIE (Bitfield-Mask: 0x01)                     */
#define RCU_INT_LXTALSTBIE_Pos            (9UL)                     /*!< LXTALSTBIE (Bit 9)                                    */
#define RCU_INT_LXTALSTBIE_Msk            (0x200UL)                 /*!< LXTALSTBIE (Bitfield-Mask: 0x01)                      */
#define RCU_INT_IRC8MSTBIE_Pos            (10UL)                    /*!< IRC8MSTBIE (Bit 10)                                   */
#define RCU_INT_IRC8MSTBIE_Msk            (0x400UL)                 /*!< IRC8MSTBIE (Bitfield-Mask: 0x01)                      */
#define RCU_INT_HXTALSTBIE_Pos            (11UL)                    /*!< HXTALSTBIE (Bit 11)                                   */
#define RCU_INT_HXTALSTBIE_Msk            (0x800UL)                 /*!< HXTALSTBIE (Bitfield-Mask: 0x01)                      */
#define RCU_INT_PLLSTBIE_Pos              (12UL)                    /*!< PLLSTBIE (Bit 12)                                     */
#define RCU_INT_PLLSTBIE_Msk              (0x1000UL)                /*!< PLLSTBIE (Bitfield-Mask: 0x01)                        */
#define RCU_INT_PLL1STBIE_Pos             (13UL)                    /*!< PLL1STBIE (Bit 13)                                    */
#define RCU_INT_PLL1STBIE_Msk             (0x2000UL)                /*!< PLL1STBIE (Bitfield-Mask: 0x01)                       */
#define RCU_INT_PLL2STBIE_Pos             (14UL)                    /*!< PLL2STBIE (Bit 14)                                    */
#define RCU_INT_PLL2STBIE_Msk             (0x4000UL)                /*!< PLL2STBIE (Bitfield-Mask: 0x01)                       */
#define RCU_INT_IRC40KSTBIC_Pos           (16UL)                    /*!< IRC40KSTBIC (Bit 16)                                  */
#define RCU_INT_IRC40KSTBIC_Msk           (0x10000UL)               /*!< IRC40KSTBIC (Bitfield-Mask: 0x01)                     */
#define RCU_INT_LXTALSTBIC_Pos            (17UL)                    /*!< LXTALSTBIC (Bit 17)                                   */
#define RCU_INT_LXTALSTBIC_Msk            (0x20000UL)               /*!< LXTALSTBIC (Bitfield-Mask: 0x01)                      */
#define RCU_INT_IRC8MSTBIC_Pos            (18UL)                    /*!< IRC8MSTBIC (Bit 18)                                   */
#define RCU_INT_IRC8MSTBIC_Msk            (0x40000UL)               /*!< IRC8MSTBIC (Bitfield-Mask: 0x01)                      */
#define RCU_INT_HXTALSTBIC_Pos            (19UL)                    /*!< HXTALSTBIC (Bit 19)                                   */
#define RCU_INT_HXTALSTBIC_Msk            (0x80000UL)               /*!< HXTALSTBIC (Bitfield-Mask: 0x01)                      */
#define RCU_INT_PLLSTBIC_Pos              (20UL)                    /*!< PLLSTBIC (Bit 20)                                     */
#define RCU_INT_PLLSTBIC_Msk              (0x100000UL)              /*!< PLLSTBIC (Bitfield-Mask: 0x01)                        */
#define RCU_INT_PLL1STBIC_Pos             (21UL)                    /*!< PLL1STBIC (Bit 21)                                    */
#define RCU_INT_PLL1STBIC_Msk             (0x200000UL)              /*!< PLL1STBIC (Bitfield-Mask: 0x01)                       */
#define RCU_INT_PLL2STBIC_Pos             (22UL)                    /*!< PLL2STBIC (Bit 22)                                    */
#define RCU_INT_PLL2STBIC_Msk             (0x400000UL)              /*!< PLL2STBIC (Bitfield-Mask: 0x01)                       */
#define RCU_INT_CKMIC_Pos                 (23UL)                    /*!< CKMIC (Bit 23)                                        */
#define RCU_INT_CKMIC_Msk                 (0x800000UL)              /*!< CKMIC (Bitfield-Mask: 0x01)                           */
/* ========================================================  APB2RST  ======================================================== */
#define RCU_APB2RST_AFRST_Pos             (0UL)                     /*!< AFRST (Bit 0)                                         */
#define RCU_APB2RST_AFRST_Msk             (0x1UL)                   /*!< AFRST (Bitfield-Mask: 0x01)                           */
#define RCU_APB2RST_PARST_Pos             (2UL)                     /*!< PARST (Bit 2)                                         */
#define RCU_APB2RST_PARST_Msk             (0x4UL)                   /*!< PARST (Bitfield-Mask: 0x01)                           */
#define RCU_APB2RST_PBRST_Pos             (3UL)                     /*!< PBRST (Bit 3)                                         */
#define RCU_APB2RST_PBRST_Msk             (0x8UL)                   /*!< PBRST (Bitfield-Mask: 0x01)                           */
#define RCU_APB2RST_PCRST_Pos             (4UL)                     /*!< PCRST (Bit 4)                                         */
#define RCU_APB2RST_PCRST_Msk             (0x10UL)                  /*!< PCRST (Bitfield-Mask: 0x01)                           */
#define RCU_APB2RST_PDRST_Pos             (5UL)                     /*!< PDRST (Bit 5)                                         */
#define RCU_APB2RST_PDRST_Msk             (0x20UL)                  /*!< PDRST (Bitfield-Mask: 0x01)                           */
#define RCU_APB2RST_PERST_Pos             (6UL)                     /*!< PERST (Bit 6)                                         */
#define RCU_APB2RST_PERST_Msk             (0x40UL)                  /*!< PERST (Bitfield-Mask: 0x01)                           */
#define RCU_APB2RST_ADC0RST_Pos           (9UL)                     /*!< ADC0RST (Bit 9)                                       */
#define RCU_APB2RST_ADC0RST_Msk           (0x200UL)                 /*!< ADC0RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB2RST_ADC1RST_Pos           (10UL)                    /*!< ADC1RST (Bit 10)                                      */
#define RCU_APB2RST_ADC1RST_Msk           (0x400UL)                 /*!< ADC1RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB2RST_TIMER0RST_Pos         (11UL)                    /*!< TIMER0RST (Bit 11)                                    */
#define RCU_APB2RST_TIMER0RST_Msk         (0x800UL)                 /*!< TIMER0RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB2RST_SPI0RST_Pos           (12UL)                    /*!< SPI0RST (Bit 12)                                      */
#define RCU_APB2RST_SPI0RST_Msk           (0x1000UL)                /*!< SPI0RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB2RST_USART0RST_Pos         (14UL)                    /*!< USART0RST (Bit 14)                                    */
#define RCU_APB2RST_USART0RST_Msk         (0x4000UL)                /*!< USART0RST (Bitfield-Mask: 0x01)                       */
/* ========================================================  APB1RST  ======================================================== */
#define RCU_APB1RST_TIMER1RST_Pos         (0UL)                     /*!< TIMER1RST (Bit 0)                                     */
#define RCU_APB1RST_TIMER1RST_Msk         (0x1UL)                   /*!< TIMER1RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_TIMER2RST_Pos         (1UL)                     /*!< TIMER2RST (Bit 1)                                     */
#define RCU_APB1RST_TIMER2RST_Msk         (0x2UL)                   /*!< TIMER2RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_TIMER3RST_Pos         (2UL)                     /*!< TIMER3RST (Bit 2)                                     */
#define RCU_APB1RST_TIMER3RST_Msk         (0x4UL)                   /*!< TIMER3RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_TIMER4RST_Pos         (3UL)                     /*!< TIMER4RST (Bit 3)                                     */
#define RCU_APB1RST_TIMER4RST_Msk         (0x8UL)                   /*!< TIMER4RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_TIMER5RST_Pos         (4UL)                     /*!< TIMER5RST (Bit 4)                                     */
#define RCU_APB1RST_TIMER5RST_Msk         (0x10UL)                  /*!< TIMER5RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_TIMER6RST_Pos         (5UL)                     /*!< TIMER6RST (Bit 5)                                     */
#define RCU_APB1RST_TIMER6RST_Msk         (0x20UL)                  /*!< TIMER6RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_WWDGTRST_Pos          (11UL)                    /*!< WWDGTRST (Bit 11)                                     */
#define RCU_APB1RST_WWDGTRST_Msk          (0x800UL)                 /*!< WWDGTRST (Bitfield-Mask: 0x01)                        */
#define RCU_APB1RST_SPI1RST_Pos           (14UL)                    /*!< SPI1RST (Bit 14)                                      */
#define RCU_APB1RST_SPI1RST_Msk           (0x4000UL)                /*!< SPI1RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB1RST_SPI2RST_Pos           (15UL)                    /*!< SPI2RST (Bit 15)                                      */
#define RCU_APB1RST_SPI2RST_Msk           (0x8000UL)                /*!< SPI2RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB1RST_USART1RST_Pos         (17UL)                    /*!< USART1RST (Bit 17)                                    */
#define RCU_APB1RST_USART1RST_Msk         (0x20000UL)               /*!< USART1RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_USART2RST_Pos         (18UL)                    /*!< USART2RST (Bit 18)                                    */
#define RCU_APB1RST_USART2RST_Msk         (0x40000UL)               /*!< USART2RST (Bitfield-Mask: 0x01)                       */
#define RCU_APB1RST_UART3RST_Pos          (19UL)                    /*!< UART3RST (Bit 19)                                     */
#define RCU_APB1RST_UART3RST_Msk          (0x80000UL)               /*!< UART3RST (Bitfield-Mask: 0x01)                        */
#define RCU_APB1RST_UART4RST_Pos          (20UL)                    /*!< UART4RST (Bit 20)                                     */
#define RCU_APB1RST_UART4RST_Msk          (0x100000UL)              /*!< UART4RST (Bitfield-Mask: 0x01)                        */
#define RCU_APB1RST_I2C0RST_Pos           (21UL)                    /*!< I2C0RST (Bit 21)                                      */
#define RCU_APB1RST_I2C0RST_Msk           (0x200000UL)              /*!< I2C0RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB1RST_I2C1RST_Pos           (22UL)                    /*!< I2C1RST (Bit 22)                                      */
#define RCU_APB1RST_I2C1RST_Msk           (0x400000UL)              /*!< I2C1RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB1RST_CAN0RST_Pos           (25UL)                    /*!< CAN0RST (Bit 25)                                      */
#define RCU_APB1RST_CAN0RST_Msk           (0x2000000UL)             /*!< CAN0RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB1RST_CAN1RST_Pos           (26UL)                    /*!< CAN1RST (Bit 26)                                      */
#define RCU_APB1RST_CAN1RST_Msk           (0x4000000UL)             /*!< CAN1RST (Bitfield-Mask: 0x01)                         */
#define RCU_APB1RST_BKPIRST_Pos           (27UL)                    /*!< BKPIRST (Bit 27)                                      */
#define RCU_APB1RST_BKPIRST_Msk           (0x8000000UL)             /*!< BKPIRST (Bitfield-Mask: 0x01)                         */
#define RCU_APB1RST_PMURST_Pos            (28UL)                    /*!< PMURST (Bit 28)                                       */
#define RCU_APB1RST_PMURST_Msk            (0x10000000UL)            /*!< PMURST (Bitfield-Mask: 0x01)                          */
#define RCU_APB1RST_DACRST_Pos            (29UL)                    /*!< DACRST (Bit 29)                                       */
#define RCU_APB1RST_DACRST_Msk            (0x20000000UL)            /*!< DACRST (Bitfield-Mask: 0x01)                          */
/* =========================================================  AHBEN  ========================================================= */
#define RCU_AHBEN_DMA0EN_Pos              (0UL)                     /*!< DMA0EN (Bit 0)                                        */
#define RCU_AHBEN_DMA0EN_Msk              (0x1UL)                   /*!< DMA0EN (Bitfield-Mask: 0x01)                          */
#define RCU_AHBEN_DMA1EN_Pos              (1UL)                     /*!< DMA1EN (Bit 1)                                        */
#define RCU_AHBEN_DMA1EN_Msk              (0x2UL)                   /*!< DMA1EN (Bitfield-Mask: 0x01)                          */
#define RCU_AHBEN_SRAMSPEN_Pos            (2UL)                     /*!< SRAMSPEN (Bit 2)                                      */
#define RCU_AHBEN_SRAMSPEN_Msk            (0x4UL)                   /*!< SRAMSPEN (Bitfield-Mask: 0x01)                        */
#define RCU_AHBEN_FMCSPEN_Pos             (4UL)                     /*!< FMCSPEN (Bit 4)                                       */
#define RCU_AHBEN_FMCSPEN_Msk             (0x10UL)                  /*!< FMCSPEN (Bitfield-Mask: 0x01)                         */
#define RCU_AHBEN_CRCEN_Pos               (6UL)                     /*!< CRCEN (Bit 6)                                         */
#define RCU_AHBEN_CRCEN_Msk               (0x40UL)                  /*!< CRCEN (Bitfield-Mask: 0x01)                           */
#define RCU_AHBEN_EXMCEN_Pos              (8UL)                     /*!< EXMCEN (Bit 8)                                        */
#define RCU_AHBEN_EXMCEN_Msk              (0x100UL)                 /*!< EXMCEN (Bitfield-Mask: 0x01)                          */
#define RCU_AHBEN_USBFSEN_Pos             (12UL)                    /*!< USBFSEN (Bit 12)                                      */
#define RCU_AHBEN_USBFSEN_Msk             (0x1000UL)                /*!< USBFSEN (Bitfield-Mask: 0x01)                         */
/* ========================================================  APB2EN  ========================================================= */
#define RCU_APB2EN_AFEN_Pos               (0UL)                     /*!< AFEN (Bit 0)                                          */
#define RCU_APB2EN_AFEN_Msk               (0x1UL)                   /*!< AFEN (Bitfield-Mask: 0x01)                            */
#define RCU_APB2EN_PAEN_Pos               (2UL)                     /*!< PAEN (Bit 2)                                          */
#define RCU_APB2EN_PAEN_Msk               (0x4UL)                   /*!< PAEN (Bitfield-Mask: 0x01)                            */
#define RCU_APB2EN_PBEN_Pos               (3UL)                     /*!< PBEN (Bit 3)                                          */
#define RCU_APB2EN_PBEN_Msk               (0x8UL)                   /*!< PBEN (Bitfield-Mask: 0x01)                            */
#define RCU_APB2EN_PCEN_Pos               (4UL)                     /*!< PCEN (Bit 4)                                          */
#define RCU_APB2EN_PCEN_Msk               (0x10UL)                  /*!< PCEN (Bitfield-Mask: 0x01)                            */
#define RCU_APB2EN_PDEN_Pos               (5UL)                     /*!< PDEN (Bit 5)                                          */
#define RCU_APB2EN_PDEN_Msk               (0x20UL)                  /*!< PDEN (Bitfield-Mask: 0x01)                            */
#define RCU_APB2EN_PEEN_Pos               (6UL)                     /*!< PEEN (Bit 6)                                          */
#define RCU_APB2EN_PEEN_Msk               (0x40UL)                  /*!< PEEN (Bitfield-Mask: 0x01)                            */
#define RCU_APB2EN_ADC0EN_Pos             (9UL)                     /*!< ADC0EN (Bit 9)                                        */
#define RCU_APB2EN_ADC0EN_Msk             (0x200UL)                 /*!< ADC0EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB2EN_ADC1EN_Pos             (10UL)                    /*!< ADC1EN (Bit 10)                                       */
#define RCU_APB2EN_ADC1EN_Msk             (0x400UL)                 /*!< ADC1EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB2EN_TIMER0EN_Pos           (11UL)                    /*!< TIMER0EN (Bit 11)                                     */
#define RCU_APB2EN_TIMER0EN_Msk           (0x800UL)                 /*!< TIMER0EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB2EN_SPI0EN_Pos             (12UL)                    /*!< SPI0EN (Bit 12)                                       */
#define RCU_APB2EN_SPI0EN_Msk             (0x1000UL)                /*!< SPI0EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB2EN_USART0EN_Pos           (14UL)                    /*!< USART0EN (Bit 14)                                     */
#define RCU_APB2EN_USART0EN_Msk           (0x4000UL)                /*!< USART0EN (Bitfield-Mask: 0x01)                        */
/* ========================================================  APB1EN  ========================================================= */
#define RCU_APB1EN_TIMER1EN_Pos           (0UL)                     /*!< TIMER1EN (Bit 0)                                      */
#define RCU_APB1EN_TIMER1EN_Msk           (0x1UL)                   /*!< TIMER1EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_TIMER2EN_Pos           (1UL)                     /*!< TIMER2EN (Bit 1)                                      */
#define RCU_APB1EN_TIMER2EN_Msk           (0x2UL)                   /*!< TIMER2EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_TIMER3EN_Pos           (2UL)                     /*!< TIMER3EN (Bit 2)                                      */
#define RCU_APB1EN_TIMER3EN_Msk           (0x4UL)                   /*!< TIMER3EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_TIMER4EN_Pos           (3UL)                     /*!< TIMER4EN (Bit 3)                                      */
#define RCU_APB1EN_TIMER4EN_Msk           (0x8UL)                   /*!< TIMER4EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_TIMER5EN_Pos           (4UL)                     /*!< TIMER5EN (Bit 4)                                      */
#define RCU_APB1EN_TIMER5EN_Msk           (0x10UL)                  /*!< TIMER5EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_TIMER6EN_Pos           (5UL)                     /*!< TIMER6EN (Bit 5)                                      */
#define RCU_APB1EN_TIMER6EN_Msk           (0x20UL)                  /*!< TIMER6EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_WWDGTEN_Pos            (11UL)                    /*!< WWDGTEN (Bit 11)                                      */
#define RCU_APB1EN_WWDGTEN_Msk            (0x800UL)                 /*!< WWDGTEN (Bitfield-Mask: 0x01)                         */
#define RCU_APB1EN_SPI1EN_Pos             (14UL)                    /*!< SPI1EN (Bit 14)                                       */
#define RCU_APB1EN_SPI1EN_Msk             (0x4000UL)                /*!< SPI1EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB1EN_SPI2EN_Pos             (15UL)                    /*!< SPI2EN (Bit 15)                                       */
#define RCU_APB1EN_SPI2EN_Msk             (0x8000UL)                /*!< SPI2EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB1EN_USART1EN_Pos           (17UL)                    /*!< USART1EN (Bit 17)                                     */
#define RCU_APB1EN_USART1EN_Msk           (0x20000UL)               /*!< USART1EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_USART2EN_Pos           (18UL)                    /*!< USART2EN (Bit 18)                                     */
#define RCU_APB1EN_USART2EN_Msk           (0x40000UL)               /*!< USART2EN (Bitfield-Mask: 0x01)                        */
#define RCU_APB1EN_UART3EN_Pos            (19UL)                    /*!< UART3EN (Bit 19)                                      */
#define RCU_APB1EN_UART3EN_Msk            (0x80000UL)               /*!< UART3EN (Bitfield-Mask: 0x01)                         */
#define RCU_APB1EN_UART4EN_Pos            (20UL)                    /*!< UART4EN (Bit 20)                                      */
#define RCU_APB1EN_UART4EN_Msk            (0x100000UL)              /*!< UART4EN (Bitfield-Mask: 0x01)                         */
#define RCU_APB1EN_I2C0EN_Pos             (21UL)                    /*!< I2C0EN (Bit 21)                                       */
#define RCU_APB1EN_I2C0EN_Msk             (0x200000UL)              /*!< I2C0EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB1EN_I2C1EN_Pos             (22UL)                    /*!< I2C1EN (Bit 22)                                       */
#define RCU_APB1EN_I2C1EN_Msk             (0x400000UL)              /*!< I2C1EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB1EN_CAN0EN_Pos             (25UL)                    /*!< CAN0EN (Bit 25)                                       */
#define RCU_APB1EN_CAN0EN_Msk             (0x2000000UL)             /*!< CAN0EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB1EN_CAN1EN_Pos             (26UL)                    /*!< CAN1EN (Bit 26)                                       */
#define RCU_APB1EN_CAN1EN_Msk             (0x4000000UL)             /*!< CAN1EN (Bitfield-Mask: 0x01)                          */
#define RCU_APB1EN_BKPIEN_Pos             (27UL)                    /*!< BKPIEN (Bit 27)                                       */
#define RCU_APB1EN_BKPIEN_Msk             (0x8000000UL)             /*!< BKPIEN (Bitfield-Mask: 0x01)                          */
#define RCU_APB1EN_PMUEN_Pos              (28UL)                    /*!< PMUEN (Bit 28)                                        */
#define RCU_APB1EN_PMUEN_Msk              (0x10000000UL)            /*!< PMUEN (Bitfield-Mask: 0x01)                           */
#define RCU_APB1EN_DACEN_Pos              (29UL)                    /*!< DACEN (Bit 29)                                        */
#define RCU_APB1EN_DACEN_Msk              (0x20000000UL)            /*!< DACEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  BDCTL  ========================================================= */
#define RCU_BDCTL_LXTALEN_Pos             (0UL)                     /*!< LXTALEN (Bit 0)                                       */
#define RCU_BDCTL_LXTALEN_Msk             (0x1UL)                   /*!< LXTALEN (Bitfield-Mask: 0x01)                         */
#define RCU_BDCTL_LXTALSTB_Pos            (1UL)                     /*!< LXTALSTB (Bit 1)                                      */
#define RCU_BDCTL_LXTALSTB_Msk            (0x2UL)                   /*!< LXTALSTB (Bitfield-Mask: 0x01)                        */
#define RCU_BDCTL_LXTALBPS_Pos            (2UL)                     /*!< LXTALBPS (Bit 2)                                      */
#define RCU_BDCTL_LXTALBPS_Msk            (0x4UL)                   /*!< LXTALBPS (Bitfield-Mask: 0x01)                        */
#define RCU_BDCTL_RTCSRC_Pos              (8UL)                     /*!< RTCSRC (Bit 8)                                        */
#define RCU_BDCTL_RTCSRC_Msk              (0x300UL)                 /*!< RTCSRC (Bitfield-Mask: 0x03)                          */
#define RCU_BDCTL_RTCEN_Pos               (15UL)                    /*!< RTCEN (Bit 15)                                        */
#define RCU_BDCTL_RTCEN_Msk               (0x8000UL)                /*!< RTCEN (Bitfield-Mask: 0x01)                           */
#define RCU_BDCTL_BKPRST_Pos              (16UL)                    /*!< BKPRST (Bit 16)                                       */
#define RCU_BDCTL_BKPRST_Msk              (0x10000UL)               /*!< BKPRST (Bitfield-Mask: 0x01)                          */
/* ========================================================  RSTSCK  ========================================================= */
#define RCU_RSTSCK_IRC40KEN_Pos           (0UL)                     /*!< IRC40KEN (Bit 0)                                      */
#define RCU_RSTSCK_IRC40KEN_Msk           (0x1UL)                   /*!< IRC40KEN (Bitfield-Mask: 0x01)                        */
#define RCU_RSTSCK_IRC40KSTB_Pos          (1UL)                     /*!< IRC40KSTB (Bit 1)                                     */
#define RCU_RSTSCK_IRC40KSTB_Msk          (0x2UL)                   /*!< IRC40KSTB (Bitfield-Mask: 0x01)                       */
#define RCU_RSTSCK_RSTFC_Pos              (24UL)                    /*!< RSTFC (Bit 24)                                        */
#define RCU_RSTSCK_RSTFC_Msk              (0x1000000UL)             /*!< RSTFC (Bitfield-Mask: 0x01)                           */
#define RCU_RSTSCK_EPRSTF_Pos             (26UL)                    /*!< EPRSTF (Bit 26)                                       */
#define RCU_RSTSCK_EPRSTF_Msk             (0x4000000UL)             /*!< EPRSTF (Bitfield-Mask: 0x01)                          */
#define RCU_RSTSCK_PORRSTF_Pos            (27UL)                    /*!< PORRSTF (Bit 27)                                      */
#define RCU_RSTSCK_PORRSTF_Msk            (0x8000000UL)             /*!< PORRSTF (Bitfield-Mask: 0x01)                         */
#define RCU_RSTSCK_SWRSTF_Pos             (28UL)                    /*!< SWRSTF (Bit 28)                                       */
#define RCU_RSTSCK_SWRSTF_Msk             (0x10000000UL)            /*!< SWRSTF (Bitfield-Mask: 0x01)                          */
#define RCU_RSTSCK_FWDGTRSTF_Pos          (29UL)                    /*!< FWDGTRSTF (Bit 29)                                    */
#define RCU_RSTSCK_FWDGTRSTF_Msk          (0x20000000UL)            /*!< FWDGTRSTF (Bitfield-Mask: 0x01)                       */
#define RCU_RSTSCK_WWDGTRSTF_Pos          (30UL)                    /*!< WWDGTRSTF (Bit 30)                                    */
#define RCU_RSTSCK_WWDGTRSTF_Msk          (0x40000000UL)            /*!< WWDGTRSTF (Bitfield-Mask: 0x01)                       */
#define RCU_RSTSCK_LPRSTF_Pos             (31UL)                    /*!< LPRSTF (Bit 31)                                       */
#define RCU_RSTSCK_LPRSTF_Msk             (0x80000000UL)            /*!< LPRSTF (Bitfield-Mask: 0x01)                          */
/* ========================================================  AHBRST  ========================================================= */
#define RCU_AHBRST_USBFSRST_Pos           (12UL)                    /*!< USBFSRST (Bit 12)                                     */
#define RCU_AHBRST_USBFSRST_Msk           (0x1000UL)                /*!< USBFSRST (Bitfield-Mask: 0x01)                        */
/* =========================================================  CFG1  ========================================================== */
#define RCU_CFG1_PREDV0_Pos               (0UL)                     /*!< PREDV0 (Bit 0)                                        */
#define RCU_CFG1_PREDV0_Msk               (0xfUL)                   /*!< PREDV0 (Bitfield-Mask: 0x0f)                          */
#define RCU_CFG1_PREDV1_Pos               (4UL)                     /*!< PREDV1 (Bit 4)                                        */
#define RCU_CFG1_PREDV1_Msk               (0xf0UL)                  /*!< PREDV1 (Bitfield-Mask: 0x0f)                          */
#define RCU_CFG1_PLL1MF_Pos               (8UL)                     /*!< PLL1MF (Bit 8)                                        */
#define RCU_CFG1_PLL1MF_Msk               (0xf00UL)                 /*!< PLL1MF (Bitfield-Mask: 0x0f)                          */
#define RCU_CFG1_PLL2MF_Pos               (12UL)                    /*!< PLL2MF (Bit 12)                                       */
#define RCU_CFG1_PLL2MF_Msk               (0xf000UL)                /*!< PLL2MF (Bitfield-Mask: 0x0f)                          */
#define RCU_CFG1_PREDV0SEL_Pos            (16UL)                    /*!< PREDV0SEL (Bit 16)                                    */
#define RCU_CFG1_PREDV0SEL_Msk            (0x10000UL)               /*!< PREDV0SEL (Bitfield-Mask: 0x01)                       */
#define RCU_CFG1_I2S1SEL_Pos              (17UL)                    /*!< I2S1SEL (Bit 17)                                      */
#define RCU_CFG1_I2S1SEL_Msk              (0x20000UL)               /*!< I2S1SEL (Bitfield-Mask: 0x01)                         */
#define RCU_CFG1_I2S2SEL_Pos              (18UL)                    /*!< I2S2SEL (Bit 18)                                      */
#define RCU_CFG1_I2S2SEL_Msk              (0x40000UL)               /*!< I2S2SEL (Bitfield-Mask: 0x01)                         */
/* ==========================================================  DSV  ========================================================== */
#define RCU_DSV_DSLPVS_Pos                (0UL)                     /*!< DSLPVS (Bit 0)                                        */
#define RCU_DSV_DSLPVS_Msk                (0x3UL)                   /*!< DSLPVS (Bitfield-Mask: 0x03)                          */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INTEN  ========================================================= */
#define RTC_INTEN_OVIE_Pos                (2UL)                     /*!< OVIE (Bit 2)                                          */
#define RTC_INTEN_OVIE_Msk                (0x4UL)                   /*!< OVIE (Bitfield-Mask: 0x01)                            */
#define RTC_INTEN_ALRMIE_Pos              (1UL)                     /*!< ALRMIE (Bit 1)                                        */
#define RTC_INTEN_ALRMIE_Msk              (0x2UL)                   /*!< ALRMIE (Bitfield-Mask: 0x01)                          */
#define RTC_INTEN_SCIE_Pos                (0UL)                     /*!< SCIE (Bit 0)                                          */
#define RTC_INTEN_SCIE_Msk                (0x1UL)                   /*!< SCIE (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CTL  ========================================================== */
#define RTC_CTL_LWOFF_Pos                 (5UL)                     /*!< LWOFF (Bit 5)                                         */
#define RTC_CTL_LWOFF_Msk                 (0x20UL)                  /*!< LWOFF (Bitfield-Mask: 0x01)                           */
#define RTC_CTL_CMF_Pos                   (4UL)                     /*!< CMF (Bit 4)                                           */
#define RTC_CTL_CMF_Msk                   (0x10UL)                  /*!< CMF (Bitfield-Mask: 0x01)                             */
#define RTC_CTL_RSYNF_Pos                 (3UL)                     /*!< RSYNF (Bit 3)                                         */
#define RTC_CTL_RSYNF_Msk                 (0x8UL)                   /*!< RSYNF (Bitfield-Mask: 0x01)                           */
#define RTC_CTL_OVIF_Pos                  (2UL)                     /*!< OVIF (Bit 2)                                          */
#define RTC_CTL_OVIF_Msk                  (0x4UL)                   /*!< OVIF (Bitfield-Mask: 0x01)                            */
#define RTC_CTL_ALRMIF_Pos                (1UL)                     /*!< ALRMIF (Bit 1)                                        */
#define RTC_CTL_ALRMIF_Msk                (0x2UL)                   /*!< ALRMIF (Bitfield-Mask: 0x01)                          */
#define RTC_CTL_SCIF_Pos                  (0UL)                     /*!< SCIF (Bit 0)                                          */
#define RTC_CTL_SCIF_Msk                  (0x1UL)                   /*!< SCIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  PSCH  ========================================================== */
#define RTC_PSCH_PSC_Pos                  (0UL)                     /*!< PSC (Bit 0)                                           */
#define RTC_PSCH_PSC_Msk                  (0xfUL)                   /*!< PSC (Bitfield-Mask: 0x0f)                             */
/* =========================================================  PSCL  ========================================================== */
#define RTC_PSCL_PSC_Pos                  (0UL)                     /*!< PSC (Bit 0)                                           */
#define RTC_PSCL_PSC_Msk                  (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* =========================================================  DIVH  ========================================================== */
#define RTC_DIVH_DIV_Pos                  (0UL)                     /*!< DIV (Bit 0)                                           */
#define RTC_DIVH_DIV_Msk                  (0xfUL)                   /*!< DIV (Bitfield-Mask: 0x0f)                             */
/* =========================================================  DIVL  ========================================================== */
#define RTC_DIVL_DIV_Pos                  (0UL)                     /*!< DIV (Bit 0)                                           */
#define RTC_DIVL_DIV_Msk                  (0xffffUL)                /*!< DIV (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CNTH  ========================================================== */
#define RTC_CNTH_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define RTC_CNTH_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CNTL  ========================================================== */
#define RTC_CNTL_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define RTC_CNTL_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  ALRMH  ========================================================= */
#define RTC_ALRMH_ALRM_Pos                (0UL)                     /*!< ALRM (Bit 0)                                          */
#define RTC_ALRMH_ALRM_Msk                (0xffffUL)                /*!< ALRM (Bitfield-Mask: 0xffff)                          */
/* =========================================================  ALRML  ========================================================= */
#define RTC_ALRML_ALRM_Pos                (0UL)                     /*!< ALRM (Bit 0)                                          */
#define RTC_ALRML_ALRM_Msk                (0xffffUL)                /*!< ALRM (Bitfield-Mask: 0xffff)                          */


/* =========================================================================================================================== */
/* ================                                           SPI0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTL0  ========================================================== */
#define SPI0_CTL0_BDEN_Pos                (15UL)                    /*!< BDEN (Bit 15)                                         */
#define SPI0_CTL0_BDEN_Msk                (0x8000UL)                /*!< BDEN (Bitfield-Mask: 0x01)                            */
#define SPI0_CTL0_BDOEN_Pos               (14UL)                    /*!< BDOEN (Bit 14)                                        */
#define SPI0_CTL0_BDOEN_Msk               (0x4000UL)                /*!< BDOEN (Bitfield-Mask: 0x01)                           */
#define SPI0_CTL0_CRCEN_Pos               (13UL)                    /*!< CRCEN (Bit 13)                                        */
#define SPI0_CTL0_CRCEN_Msk               (0x2000UL)                /*!< CRCEN (Bitfield-Mask: 0x01)                           */
#define SPI0_CTL0_CRCNT_Pos               (12UL)                    /*!< CRCNT (Bit 12)                                        */
#define SPI0_CTL0_CRCNT_Msk               (0x1000UL)                /*!< CRCNT (Bitfield-Mask: 0x01)                           */
#define SPI0_CTL0_FF16_Pos                (11UL)                    /*!< FF16 (Bit 11)                                         */
#define SPI0_CTL0_FF16_Msk                (0x800UL)                 /*!< FF16 (Bitfield-Mask: 0x01)                            */
#define SPI0_CTL0_RO_Pos                  (10UL)                    /*!< RO (Bit 10)                                           */
#define SPI0_CTL0_RO_Msk                  (0x400UL)                 /*!< RO (Bitfield-Mask: 0x01)                              */
#define SPI0_CTL0_SWNSSEN_Pos             (9UL)                     /*!< SWNSSEN (Bit 9)                                       */
#define SPI0_CTL0_SWNSSEN_Msk             (0x200UL)                 /*!< SWNSSEN (Bitfield-Mask: 0x01)                         */
#define SPI0_CTL0_SWNSS_Pos               (8UL)                     /*!< SWNSS (Bit 8)                                         */
#define SPI0_CTL0_SWNSS_Msk               (0x100UL)                 /*!< SWNSS (Bitfield-Mask: 0x01)                           */
#define SPI0_CTL0_LF_Pos                  (7UL)                     /*!< LF (Bit 7)                                            */
#define SPI0_CTL0_LF_Msk                  (0x80UL)                  /*!< LF (Bitfield-Mask: 0x01)                              */
#define SPI0_CTL0_SPIEN_Pos               (6UL)                     /*!< SPIEN (Bit 6)                                         */
#define SPI0_CTL0_SPIEN_Msk               (0x40UL)                  /*!< SPIEN (Bitfield-Mask: 0x01)                           */
#define SPI0_CTL0_PSC_Pos                 (3UL)                     /*!< PSC (Bit 3)                                           */
#define SPI0_CTL0_PSC_Msk                 (0x38UL)                  /*!< PSC (Bitfield-Mask: 0x07)                             */
#define SPI0_CTL0_MSTMOD_Pos              (2UL)                     /*!< MSTMOD (Bit 2)                                        */
#define SPI0_CTL0_MSTMOD_Msk              (0x4UL)                   /*!< MSTMOD (Bitfield-Mask: 0x01)                          */
#define SPI0_CTL0_CKPL_Pos                (1UL)                     /*!< CKPL (Bit 1)                                          */
#define SPI0_CTL0_CKPL_Msk                (0x2UL)                   /*!< CKPL (Bitfield-Mask: 0x01)                            */
#define SPI0_CTL0_CKPH_Pos                (0UL)                     /*!< CKPH (Bit 0)                                          */
#define SPI0_CTL0_CKPH_Msk                (0x1UL)                   /*!< CKPH (Bitfield-Mask: 0x01)                            */
/* =========================================================  CTL1  ========================================================== */
#define SPI0_CTL1_TBEIE_Pos               (7UL)                     /*!< TBEIE (Bit 7)                                         */
#define SPI0_CTL1_TBEIE_Msk               (0x80UL)                  /*!< TBEIE (Bitfield-Mask: 0x01)                           */
#define SPI0_CTL1_RBNEIE_Pos              (6UL)                     /*!< RBNEIE (Bit 6)                                        */
#define SPI0_CTL1_RBNEIE_Msk              (0x40UL)                  /*!< RBNEIE (Bitfield-Mask: 0x01)                          */
#define SPI0_CTL1_ERRIE_Pos               (5UL)                     /*!< ERRIE (Bit 5)                                         */
#define SPI0_CTL1_ERRIE_Msk               (0x20UL)                  /*!< ERRIE (Bitfield-Mask: 0x01)                           */
#define SPI0_CTL1_TMOD_Pos                (4UL)                     /*!< TMOD (Bit 4)                                          */
#define SPI0_CTL1_TMOD_Msk                (0x10UL)                  /*!< TMOD (Bitfield-Mask: 0x01)                            */
#define SPI0_CTL1_NSSP_Pos                (3UL)                     /*!< NSSP (Bit 3)                                          */
#define SPI0_CTL1_NSSP_Msk                (0x8UL)                   /*!< NSSP (Bitfield-Mask: 0x01)                            */
#define SPI0_CTL1_NSSDRV_Pos              (2UL)                     /*!< NSSDRV (Bit 2)                                        */
#define SPI0_CTL1_NSSDRV_Msk              (0x4UL)                   /*!< NSSDRV (Bitfield-Mask: 0x01)                          */
#define SPI0_CTL1_DMATEN_Pos              (1UL)                     /*!< DMATEN (Bit 1)                                        */
#define SPI0_CTL1_DMATEN_Msk              (0x2UL)                   /*!< DMATEN (Bitfield-Mask: 0x01)                          */
#define SPI0_CTL1_DMAREN_Pos              (0UL)                     /*!< DMAREN (Bit 0)                                        */
#define SPI0_CTL1_DMAREN_Msk              (0x1UL)                   /*!< DMAREN (Bitfield-Mask: 0x01)                          */
/* =========================================================  STAT  ========================================================== */
#define SPI0_STAT_FERR_Pos                (8UL)                     /*!< FERR (Bit 8)                                          */
#define SPI0_STAT_FERR_Msk                (0x100UL)                 /*!< FERR (Bitfield-Mask: 0x01)                            */
#define SPI0_STAT_TRANS_Pos               (7UL)                     /*!< TRANS (Bit 7)                                         */
#define SPI0_STAT_TRANS_Msk               (0x80UL)                  /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define SPI0_STAT_RXORERR_Pos             (6UL)                     /*!< RXORERR (Bit 6)                                       */
#define SPI0_STAT_RXORERR_Msk             (0x40UL)                  /*!< RXORERR (Bitfield-Mask: 0x01)                         */
#define SPI0_STAT_CONFERR_Pos             (5UL)                     /*!< CONFERR (Bit 5)                                       */
#define SPI0_STAT_CONFERR_Msk             (0x20UL)                  /*!< CONFERR (Bitfield-Mask: 0x01)                         */
#define SPI0_STAT_CRCERR_Pos              (4UL)                     /*!< CRCERR (Bit 4)                                        */
#define SPI0_STAT_CRCERR_Msk              (0x10UL)                  /*!< CRCERR (Bitfield-Mask: 0x01)                          */
#define SPI0_STAT_TXURERR_Pos             (3UL)                     /*!< TXURERR (Bit 3)                                       */
#define SPI0_STAT_TXURERR_Msk             (0x8UL)                   /*!< TXURERR (Bitfield-Mask: 0x01)                         */
#define SPI0_STAT_I2SCH_Pos               (2UL)                     /*!< I2SCH (Bit 2)                                         */
#define SPI0_STAT_I2SCH_Msk               (0x4UL)                   /*!< I2SCH (Bitfield-Mask: 0x01)                           */
#define SPI0_STAT_TBE_Pos                 (1UL)                     /*!< TBE (Bit 1)                                           */
#define SPI0_STAT_TBE_Msk                 (0x2UL)                   /*!< TBE (Bitfield-Mask: 0x01)                             */
#define SPI0_STAT_RBNE_Pos                (0UL)                     /*!< RBNE (Bit 0)                                          */
#define SPI0_STAT_RBNE_Msk                (0x1UL)                   /*!< RBNE (Bitfield-Mask: 0x01)                            */
/* =========================================================  DATA  ========================================================== */
#define SPI0_DATA_SPI_DATA_Pos            (0UL)                     /*!< SPI_DATA (Bit 0)                                      */
#define SPI0_DATA_SPI_DATA_Msk            (0xffffUL)                /*!< SPI_DATA (Bitfield-Mask: 0xffff)                      */
/* ========================================================  CRCPOLY  ======================================================== */
#define SPI0_CRCPOLY_CRCPOLY_Pos          (0UL)                     /*!< CRCPOLY (Bit 0)                                       */
#define SPI0_CRCPOLY_CRCPOLY_Msk          (0xffffUL)                /*!< CRCPOLY (Bitfield-Mask: 0xffff)                       */
/* =========================================================  RCRC  ========================================================== */
#define SPI0_RCRC_RCRC_Pos                (0UL)                     /*!< RCRC (Bit 0)                                          */
#define SPI0_RCRC_RCRC_Msk                (0xffffUL)                /*!< RCRC (Bitfield-Mask: 0xffff)                          */
/* =========================================================  TCRC  ========================================================== */
#define SPI0_TCRC_TCRC_Pos                (0UL)                     /*!< TCRC (Bit 0)                                          */
#define SPI0_TCRC_TCRC_Msk                (0xffffUL)                /*!< TCRC (Bitfield-Mask: 0xffff)                          */
/* ========================================================  I2SCTL  ========================================================= */
#define SPI0_I2SCTL_I2SSEL_Pos            (11UL)                    /*!< I2SSEL (Bit 11)                                       */
#define SPI0_I2SCTL_I2SSEL_Msk            (0x800UL)                 /*!< I2SSEL (Bitfield-Mask: 0x01)                          */
#define SPI0_I2SCTL_I2SEN_Pos             (10UL)                    /*!< I2SEN (Bit 10)                                        */
#define SPI0_I2SCTL_I2SEN_Msk             (0x400UL)                 /*!< I2SEN (Bitfield-Mask: 0x01)                           */
#define SPI0_I2SCTL_I2SOPMOD_Pos          (8UL)                     /*!< I2SOPMOD (Bit 8)                                      */
#define SPI0_I2SCTL_I2SOPMOD_Msk          (0x300UL)                 /*!< I2SOPMOD (Bitfield-Mask: 0x03)                        */
#define SPI0_I2SCTL_PCMSMOD_Pos           (7UL)                     /*!< PCMSMOD (Bit 7)                                       */
#define SPI0_I2SCTL_PCMSMOD_Msk           (0x80UL)                  /*!< PCMSMOD (Bitfield-Mask: 0x01)                         */
#define SPI0_I2SCTL_I2SSTD_Pos            (4UL)                     /*!< I2SSTD (Bit 4)                                        */
#define SPI0_I2SCTL_I2SSTD_Msk            (0x30UL)                  /*!< I2SSTD (Bitfield-Mask: 0x03)                          */
#define SPI0_I2SCTL_CKPL_Pos              (3UL)                     /*!< CKPL (Bit 3)                                          */
#define SPI0_I2SCTL_CKPL_Msk              (0x8UL)                   /*!< CKPL (Bitfield-Mask: 0x01)                            */
#define SPI0_I2SCTL_DTLEN_Pos             (1UL)                     /*!< DTLEN (Bit 1)                                         */
#define SPI0_I2SCTL_DTLEN_Msk             (0x6UL)                   /*!< DTLEN (Bitfield-Mask: 0x03)                           */
#define SPI0_I2SCTL_CHLEN_Pos             (0UL)                     /*!< CHLEN (Bit 0)                                         */
#define SPI0_I2SCTL_CHLEN_Msk             (0x1UL)                   /*!< CHLEN (Bitfield-Mask: 0x01)                           */
/* ========================================================  I2SPSC  ========================================================= */
#define SPI0_I2SPSC_MCKOEN_Pos            (9UL)                     /*!< MCKOEN (Bit 9)                                        */
#define SPI0_I2SPSC_MCKOEN_Msk            (0x200UL)                 /*!< MCKOEN (Bitfield-Mask: 0x01)                          */
#define SPI0_I2SPSC_OF_Pos                (8UL)                     /*!< OF (Bit 8)                                            */
#define SPI0_I2SPSC_OF_Msk                (0x100UL)                 /*!< OF (Bitfield-Mask: 0x01)                              */
#define SPI0_I2SPSC_DIV_Pos               (0UL)                     /*!< DIV (Bit 0)                                           */
#define SPI0_I2SPSC_DIV_Msk               (0xffUL)                  /*!< DIV (Bitfield-Mask: 0xff)                             */


/* =========================================================================================================================== */
/* ================                                          TIMER0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTL0  ========================================================== */
#define TIMER0_CTL0_CKDIV_Pos             (8UL)                     /*!< CKDIV (Bit 8)                                         */
#define TIMER0_CTL0_CKDIV_Msk             (0x300UL)                 /*!< CKDIV (Bitfield-Mask: 0x03)                           */
#define TIMER0_CTL0_ARSE_Pos              (7UL)                     /*!< ARSE (Bit 7)                                          */
#define TIMER0_CTL0_ARSE_Msk              (0x80UL)                  /*!< ARSE (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL0_CAM_Pos               (5UL)                     /*!< CAM (Bit 5)                                           */
#define TIMER0_CTL0_CAM_Msk               (0x60UL)                  /*!< CAM (Bitfield-Mask: 0x03)                             */
#define TIMER0_CTL0_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define TIMER0_CTL0_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define TIMER0_CTL0_SPM_Pos               (3UL)                     /*!< SPM (Bit 3)                                           */
#define TIMER0_CTL0_SPM_Msk               (0x8UL)                   /*!< SPM (Bitfield-Mask: 0x01)                             */
#define TIMER0_CTL0_UPS_Pos               (2UL)                     /*!< UPS (Bit 2)                                           */
#define TIMER0_CTL0_UPS_Msk               (0x4UL)                   /*!< UPS (Bitfield-Mask: 0x01)                             */
#define TIMER0_CTL0_UPDIS_Pos             (1UL)                     /*!< UPDIS (Bit 1)                                         */
#define TIMER0_CTL0_UPDIS_Msk             (0x2UL)                   /*!< UPDIS (Bitfield-Mask: 0x01)                           */
#define TIMER0_CTL0_CEN_Pos               (0UL)                     /*!< CEN (Bit 0)                                           */
#define TIMER0_CTL0_CEN_Msk               (0x1UL)                   /*!< CEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  CTL1  ========================================================== */
#define TIMER0_CTL1_ISO3_Pos              (14UL)                    /*!< ISO3 (Bit 14)                                         */
#define TIMER0_CTL1_ISO3_Msk              (0x4000UL)                /*!< ISO3 (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL1_ISO2N_Pos             (13UL)                    /*!< ISO2N (Bit 13)                                        */
#define TIMER0_CTL1_ISO2N_Msk             (0x2000UL)                /*!< ISO2N (Bitfield-Mask: 0x01)                           */
#define TIMER0_CTL1_ISO2_Pos              (12UL)                    /*!< ISO2 (Bit 12)                                         */
#define TIMER0_CTL1_ISO2_Msk              (0x1000UL)                /*!< ISO2 (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL1_ISO1N_Pos             (11UL)                    /*!< ISO1N (Bit 11)                                        */
#define TIMER0_CTL1_ISO1N_Msk             (0x800UL)                 /*!< ISO1N (Bitfield-Mask: 0x01)                           */
#define TIMER0_CTL1_ISO1_Pos              (10UL)                    /*!< ISO1 (Bit 10)                                         */
#define TIMER0_CTL1_ISO1_Msk              (0x400UL)                 /*!< ISO1 (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL1_ISO0N_Pos             (9UL)                     /*!< ISO0N (Bit 9)                                         */
#define TIMER0_CTL1_ISO0N_Msk             (0x200UL)                 /*!< ISO0N (Bitfield-Mask: 0x01)                           */
#define TIMER0_CTL1_ISO0_Pos              (8UL)                     /*!< ISO0 (Bit 8)                                          */
#define TIMER0_CTL1_ISO0_Msk              (0x100UL)                 /*!< ISO0 (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL1_TI0S_Pos              (7UL)                     /*!< TI0S (Bit 7)                                          */
#define TIMER0_CTL1_TI0S_Msk              (0x80UL)                  /*!< TI0S (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL1_MMC_Pos               (4UL)                     /*!< MMC (Bit 4)                                           */
#define TIMER0_CTL1_MMC_Msk               (0x70UL)                  /*!< MMC (Bitfield-Mask: 0x07)                             */
#define TIMER0_CTL1_DMAS_Pos              (3UL)                     /*!< DMAS (Bit 3)                                          */
#define TIMER0_CTL1_DMAS_Msk              (0x8UL)                   /*!< DMAS (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL1_CCUC_Pos              (2UL)                     /*!< CCUC (Bit 2)                                          */
#define TIMER0_CTL1_CCUC_Msk              (0x4UL)                   /*!< CCUC (Bitfield-Mask: 0x01)                            */
#define TIMER0_CTL1_CCSE_Pos              (0UL)                     /*!< CCSE (Bit 0)                                          */
#define TIMER0_CTL1_CCSE_Msk              (0x1UL)                   /*!< CCSE (Bitfield-Mask: 0x01)                            */
/* =========================================================  SMCFG  ========================================================= */
#define TIMER0_SMCFG_ETP_Pos              (15UL)                    /*!< ETP (Bit 15)                                          */
#define TIMER0_SMCFG_ETP_Msk              (0x8000UL)                /*!< ETP (Bitfield-Mask: 0x01)                             */
#define TIMER0_SMCFG_SMC1_Pos             (14UL)                    /*!< SMC1 (Bit 14)                                         */
#define TIMER0_SMCFG_SMC1_Msk             (0x4000UL)                /*!< SMC1 (Bitfield-Mask: 0x01)                            */
#define TIMER0_SMCFG_ETPSC_Pos            (12UL)                    /*!< ETPSC (Bit 12)                                        */
#define TIMER0_SMCFG_ETPSC_Msk            (0x3000UL)                /*!< ETPSC (Bitfield-Mask: 0x03)                           */
#define TIMER0_SMCFG_ETFC_Pos             (8UL)                     /*!< ETFC (Bit 8)                                          */
#define TIMER0_SMCFG_ETFC_Msk             (0xf00UL)                 /*!< ETFC (Bitfield-Mask: 0x0f)                            */
#define TIMER0_SMCFG_MSM_Pos              (7UL)                     /*!< MSM (Bit 7)                                           */
#define TIMER0_SMCFG_MSM_Msk              (0x80UL)                  /*!< MSM (Bitfield-Mask: 0x01)                             */
#define TIMER0_SMCFG_TRGS_Pos             (4UL)                     /*!< TRGS (Bit 4)                                          */
#define TIMER0_SMCFG_TRGS_Msk             (0x70UL)                  /*!< TRGS (Bitfield-Mask: 0x07)                            */
#define TIMER0_SMCFG_SMC_Pos              (0UL)                     /*!< SMC (Bit 0)                                           */
#define TIMER0_SMCFG_SMC_Msk              (0x7UL)                   /*!< SMC (Bitfield-Mask: 0x07)                             */
/* =======================================================  DMAINTEN  ======================================================== */
#define TIMER0_DMAINTEN_TRGDEN_Pos        (14UL)                    /*!< TRGDEN (Bit 14)                                       */
#define TIMER0_DMAINTEN_TRGDEN_Msk        (0x4000UL)                /*!< TRGDEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_DMAINTEN_CMTDEN_Pos        (13UL)                    /*!< CMTDEN (Bit 13)                                       */
#define TIMER0_DMAINTEN_CMTDEN_Msk        (0x2000UL)                /*!< CMTDEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_DMAINTEN_CH3DEN_Pos        (12UL)                    /*!< CH3DEN (Bit 12)                                       */
#define TIMER0_DMAINTEN_CH3DEN_Msk        (0x1000UL)                /*!< CH3DEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_DMAINTEN_CH2DEN_Pos        (11UL)                    /*!< CH2DEN (Bit 11)                                       */
#define TIMER0_DMAINTEN_CH2DEN_Msk        (0x800UL)                 /*!< CH2DEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_DMAINTEN_CH1DEN_Pos        (10UL)                    /*!< CH1DEN (Bit 10)                                       */
#define TIMER0_DMAINTEN_CH1DEN_Msk        (0x400UL)                 /*!< CH1DEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_DMAINTEN_CH0DEN_Pos        (9UL)                     /*!< CH0DEN (Bit 9)                                        */
#define TIMER0_DMAINTEN_CH0DEN_Msk        (0x200UL)                 /*!< CH0DEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_DMAINTEN_UPDEN_Pos         (8UL)                     /*!< UPDEN (Bit 8)                                         */
#define TIMER0_DMAINTEN_UPDEN_Msk         (0x100UL)                 /*!< UPDEN (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_BRKIE_Pos         (7UL)                     /*!< BRKIE (Bit 7)                                         */
#define TIMER0_DMAINTEN_BRKIE_Msk         (0x80UL)                  /*!< BRKIE (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_TRGIE_Pos         (6UL)                     /*!< TRGIE (Bit 6)                                         */
#define TIMER0_DMAINTEN_TRGIE_Msk         (0x40UL)                  /*!< TRGIE (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_CMTIE_Pos         (5UL)                     /*!< CMTIE (Bit 5)                                         */
#define TIMER0_DMAINTEN_CMTIE_Msk         (0x20UL)                  /*!< CMTIE (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_CH3IE_Pos         (4UL)                     /*!< CH3IE (Bit 4)                                         */
#define TIMER0_DMAINTEN_CH3IE_Msk         (0x10UL)                  /*!< CH3IE (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_CH2IE_Pos         (3UL)                     /*!< CH2IE (Bit 3)                                         */
#define TIMER0_DMAINTEN_CH2IE_Msk         (0x8UL)                   /*!< CH2IE (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_CH1IE_Pos         (2UL)                     /*!< CH1IE (Bit 2)                                         */
#define TIMER0_DMAINTEN_CH1IE_Msk         (0x4UL)                   /*!< CH1IE (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_CH0IE_Pos         (1UL)                     /*!< CH0IE (Bit 1)                                         */
#define TIMER0_DMAINTEN_CH0IE_Msk         (0x2UL)                   /*!< CH0IE (Bitfield-Mask: 0x01)                           */
#define TIMER0_DMAINTEN_UPIE_Pos          (0UL)                     /*!< UPIE (Bit 0)                                          */
#define TIMER0_DMAINTEN_UPIE_Msk          (0x1UL)                   /*!< UPIE (Bitfield-Mask: 0x01)                            */
/* =========================================================  INTF  ========================================================== */
#define TIMER0_INTF_CH3OF_Pos             (12UL)                    /*!< CH3OF (Bit 12)                                        */
#define TIMER0_INTF_CH3OF_Msk             (0x1000UL)                /*!< CH3OF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CH2OF_Pos             (11UL)                    /*!< CH2OF (Bit 11)                                        */
#define TIMER0_INTF_CH2OF_Msk             (0x800UL)                 /*!< CH2OF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CH1OF_Pos             (10UL)                    /*!< CH1OF (Bit 10)                                        */
#define TIMER0_INTF_CH1OF_Msk             (0x400UL)                 /*!< CH1OF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CH0OF_Pos             (9UL)                     /*!< CH0OF (Bit 9)                                         */
#define TIMER0_INTF_CH0OF_Msk             (0x200UL)                 /*!< CH0OF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_BRKIF_Pos             (7UL)                     /*!< BRKIF (Bit 7)                                         */
#define TIMER0_INTF_BRKIF_Msk             (0x80UL)                  /*!< BRKIF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_TRGIF_Pos             (6UL)                     /*!< TRGIF (Bit 6)                                         */
#define TIMER0_INTF_TRGIF_Msk             (0x40UL)                  /*!< TRGIF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CMTIF_Pos             (5UL)                     /*!< CMTIF (Bit 5)                                         */
#define TIMER0_INTF_CMTIF_Msk             (0x20UL)                  /*!< CMTIF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CH3IF_Pos             (4UL)                     /*!< CH3IF (Bit 4)                                         */
#define TIMER0_INTF_CH3IF_Msk             (0x10UL)                  /*!< CH3IF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CH2IF_Pos             (3UL)                     /*!< CH2IF (Bit 3)                                         */
#define TIMER0_INTF_CH2IF_Msk             (0x8UL)                   /*!< CH2IF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CH1IF_Pos             (2UL)                     /*!< CH1IF (Bit 2)                                         */
#define TIMER0_INTF_CH1IF_Msk             (0x4UL)                   /*!< CH1IF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_CH0IF_Pos             (1UL)                     /*!< CH0IF (Bit 1)                                         */
#define TIMER0_INTF_CH0IF_Msk             (0x2UL)                   /*!< CH0IF (Bitfield-Mask: 0x01)                           */
#define TIMER0_INTF_UPIF_Pos              (0UL)                     /*!< UPIF (Bit 0)                                          */
#define TIMER0_INTF_UPIF_Msk              (0x1UL)                   /*!< UPIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  SWEVG  ========================================================= */
#define TIMER0_SWEVG_BRKG_Pos             (7UL)                     /*!< BRKG (Bit 7)                                          */
#define TIMER0_SWEVG_BRKG_Msk             (0x80UL)                  /*!< BRKG (Bitfield-Mask: 0x01)                            */
#define TIMER0_SWEVG_TRGG_Pos             (6UL)                     /*!< TRGG (Bit 6)                                          */
#define TIMER0_SWEVG_TRGG_Msk             (0x40UL)                  /*!< TRGG (Bitfield-Mask: 0x01)                            */
#define TIMER0_SWEVG_CMTG_Pos             (5UL)                     /*!< CMTG (Bit 5)                                          */
#define TIMER0_SWEVG_CMTG_Msk             (0x20UL)                  /*!< CMTG (Bitfield-Mask: 0x01)                            */
#define TIMER0_SWEVG_CH3G_Pos             (4UL)                     /*!< CH3G (Bit 4)                                          */
#define TIMER0_SWEVG_CH3G_Msk             (0x10UL)                  /*!< CH3G (Bitfield-Mask: 0x01)                            */
#define TIMER0_SWEVG_CH2G_Pos             (3UL)                     /*!< CH2G (Bit 3)                                          */
#define TIMER0_SWEVG_CH2G_Msk             (0x8UL)                   /*!< CH2G (Bitfield-Mask: 0x01)                            */
#define TIMER0_SWEVG_CH1G_Pos             (2UL)                     /*!< CH1G (Bit 2)                                          */
#define TIMER0_SWEVG_CH1G_Msk             (0x4UL)                   /*!< CH1G (Bitfield-Mask: 0x01)                            */
#define TIMER0_SWEVG_CH0G_Pos             (1UL)                     /*!< CH0G (Bit 1)                                          */
#define TIMER0_SWEVG_CH0G_Msk             (0x2UL)                   /*!< CH0G (Bitfield-Mask: 0x01)                            */
#define TIMER0_SWEVG_UPG_Pos              (0UL)                     /*!< UPG (Bit 0)                                           */
#define TIMER0_SWEVG_UPG_Msk              (0x1UL)                   /*!< UPG (Bitfield-Mask: 0x01)                             */
/* =====================================================  CHCTL0_Output  ===================================================== */
#define TIMER0_CHCTL0_Output_CH1COMCEN_Pos (15UL)                   /*!< CH1COMCEN (Bit 15)                                    */
#define TIMER0_CHCTL0_Output_CH1COMCEN_Msk (0x8000UL)               /*!< CH1COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL0_Output_CH1COMCTL_Pos (12UL)                   /*!< CH1COMCTL (Bit 12)                                    */
#define TIMER0_CHCTL0_Output_CH1COMCTL_Msk (0x7000UL)               /*!< CH1COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER0_CHCTL0_Output_CH1COMSEN_Pos (11UL)                   /*!< CH1COMSEN (Bit 11)                                    */
#define TIMER0_CHCTL0_Output_CH1COMSEN_Msk (0x800UL)                /*!< CH1COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL0_Output_CH1COMFEN_Pos (10UL)                   /*!< CH1COMFEN (Bit 10)                                    */
#define TIMER0_CHCTL0_Output_CH1COMFEN_Msk (0x400UL)                /*!< CH1COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL0_Output_CH1MS_Pos    (8UL)                     /*!< CH1MS (Bit 8)                                         */
#define TIMER0_CHCTL0_Output_CH1MS_Msk    (0x300UL)                 /*!< CH1MS (Bitfield-Mask: 0x03)                           */
#define TIMER0_CHCTL0_Output_CH0COMCEN_Pos (7UL)                    /*!< CH0COMCEN (Bit 7)                                     */
#define TIMER0_CHCTL0_Output_CH0COMCEN_Msk (0x80UL)                 /*!< CH0COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL0_Output_CH0COMCTL_Pos (4UL)                    /*!< CH0COMCTL (Bit 4)                                     */
#define TIMER0_CHCTL0_Output_CH0COMCTL_Msk (0x70UL)                 /*!< CH0COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER0_CHCTL0_Output_CH0COMSEN_Pos (3UL)                    /*!< CH0COMSEN (Bit 3)                                     */
#define TIMER0_CHCTL0_Output_CH0COMSEN_Msk (0x8UL)                  /*!< CH0COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL0_Output_CH0COMFEN_Pos (2UL)                    /*!< CH0COMFEN (Bit 2)                                     */
#define TIMER0_CHCTL0_Output_CH0COMFEN_Msk (0x4UL)                  /*!< CH0COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL0_Output_CH0MS_Pos    (0UL)                     /*!< CH0MS (Bit 0)                                         */
#define TIMER0_CHCTL0_Output_CH0MS_Msk    (0x3UL)                   /*!< CH0MS (Bitfield-Mask: 0x03)                           */
/* =====================================================  CHCTL0_Input  ====================================================== */
#define TIMER0_CHCTL0_Input_CH1CAPFLT_Pos (12UL)                    /*!< CH1CAPFLT (Bit 12)                                    */
#define TIMER0_CHCTL0_Input_CH1CAPFLT_Msk (0xf000UL)                /*!< CH1CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER0_CHCTL0_Input_CH1CAPPSC_Pos (10UL)                    /*!< CH1CAPPSC (Bit 10)                                    */
#define TIMER0_CHCTL0_Input_CH1CAPPSC_Msk (0xc00UL)                 /*!< CH1CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER0_CHCTL0_Input_CH1MS_Pos     (8UL)                     /*!< CH1MS (Bit 8)                                         */
#define TIMER0_CHCTL0_Input_CH1MS_Msk     (0x300UL)                 /*!< CH1MS (Bitfield-Mask: 0x03)                           */
#define TIMER0_CHCTL0_Input_CH0CAPFLT_Pos (4UL)                     /*!< CH0CAPFLT (Bit 4)                                     */
#define TIMER0_CHCTL0_Input_CH0CAPFLT_Msk (0xf0UL)                  /*!< CH0CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER0_CHCTL0_Input_CH0CAPPSC_Pos (2UL)                     /*!< CH0CAPPSC (Bit 2)                                     */
#define TIMER0_CHCTL0_Input_CH0CAPPSC_Msk (0xcUL)                   /*!< CH0CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER0_CHCTL0_Input_CH0MS_Pos     (0UL)                     /*!< CH0MS (Bit 0)                                         */
#define TIMER0_CHCTL0_Input_CH0MS_Msk     (0x3UL)                   /*!< CH0MS (Bitfield-Mask: 0x03)                           */
/* =====================================================  CHCTL1_Output  ===================================================== */
#define TIMER0_CHCTL1_Output_CH3COMCEN_Pos (15UL)                   /*!< CH3COMCEN (Bit 15)                                    */
#define TIMER0_CHCTL1_Output_CH3COMCEN_Msk (0x8000UL)               /*!< CH3COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL1_Output_CH3COMCTL_Pos (12UL)                   /*!< CH3COMCTL (Bit 12)                                    */
#define TIMER0_CHCTL1_Output_CH3COMCTL_Msk (0x7000UL)               /*!< CH3COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER0_CHCTL1_Output_CH3COMSEN_Pos (11UL)                   /*!< CH3COMSEN (Bit 11)                                    */
#define TIMER0_CHCTL1_Output_CH3COMSEN_Msk (0x800UL)                /*!< CH3COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL1_Output_CH3COMFEN_Pos (10UL)                   /*!< CH3COMFEN (Bit 10)                                    */
#define TIMER0_CHCTL1_Output_CH3COMFEN_Msk (0x400UL)                /*!< CH3COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL1_Output_CH3MS_Pos    (8UL)                     /*!< CH3MS (Bit 8)                                         */
#define TIMER0_CHCTL1_Output_CH3MS_Msk    (0x300UL)                 /*!< CH3MS (Bitfield-Mask: 0x03)                           */
#define TIMER0_CHCTL1_Output_CH2COMCEN_Pos (7UL)                    /*!< CH2COMCEN (Bit 7)                                     */
#define TIMER0_CHCTL1_Output_CH2COMCEN_Msk (0x80UL)                 /*!< CH2COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL1_Output_CH2COMCTL_Pos (4UL)                    /*!< CH2COMCTL (Bit 4)                                     */
#define TIMER0_CHCTL1_Output_CH2COMCTL_Msk (0x70UL)                 /*!< CH2COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER0_CHCTL1_Output_CH2COMSEN_Pos (3UL)                    /*!< CH2COMSEN (Bit 3)                                     */
#define TIMER0_CHCTL1_Output_CH2COMSEN_Msk (0x8UL)                  /*!< CH2COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL1_Output_CH2COMFEN_Pos (2UL)                    /*!< CH2COMFEN (Bit 2)                                     */
#define TIMER0_CHCTL1_Output_CH2COMFEN_Msk (0x4UL)                  /*!< CH2COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER0_CHCTL1_Output_CH2MS_Pos    (0UL)                     /*!< CH2MS (Bit 0)                                         */
#define TIMER0_CHCTL1_Output_CH2MS_Msk    (0x3UL)                   /*!< CH2MS (Bitfield-Mask: 0x03)                           */
/* =====================================================  CHCTL1_Input  ====================================================== */
#define TIMER0_CHCTL1_Input_CH3CAPFLT_Pos (12UL)                    /*!< CH3CAPFLT (Bit 12)                                    */
#define TIMER0_CHCTL1_Input_CH3CAPFLT_Msk (0xf000UL)                /*!< CH3CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER0_CHCTL1_Input_CH3CAPPSC_Pos (10UL)                    /*!< CH3CAPPSC (Bit 10)                                    */
#define TIMER0_CHCTL1_Input_CH3CAPPSC_Msk (0xc00UL)                 /*!< CH3CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER0_CHCTL1_Input_CH3MS_Pos     (8UL)                     /*!< CH3MS (Bit 8)                                         */
#define TIMER0_CHCTL1_Input_CH3MS_Msk     (0x300UL)                 /*!< CH3MS (Bitfield-Mask: 0x03)                           */
#define TIMER0_CHCTL1_Input_CH2CAPFLT_Pos (4UL)                     /*!< CH2CAPFLT (Bit 4)                                     */
#define TIMER0_CHCTL1_Input_CH2CAPFLT_Msk (0xf0UL)                  /*!< CH2CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER0_CHCTL1_Input_CH2CAPPSC_Pos (2UL)                     /*!< CH2CAPPSC (Bit 2)                                     */
#define TIMER0_CHCTL1_Input_CH2CAPPSC_Msk (0xcUL)                   /*!< CH2CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER0_CHCTL1_Input_CH2MS_Pos     (0UL)                     /*!< CH2MS (Bit 0)                                         */
#define TIMER0_CHCTL1_Input_CH2MS_Msk     (0x3UL)                   /*!< CH2MS (Bitfield-Mask: 0x03)                           */
/* ========================================================  CHCTL2  ========================================================= */
#define TIMER0_CHCTL2_CH3P_Pos            (13UL)                    /*!< CH3P (Bit 13)                                         */
#define TIMER0_CHCTL2_CH3P_Msk            (0x2000UL)                /*!< CH3P (Bitfield-Mask: 0x01)                            */
#define TIMER0_CHCTL2_CH3EN_Pos           (12UL)                    /*!< CH3EN (Bit 12)                                        */
#define TIMER0_CHCTL2_CH3EN_Msk           (0x1000UL)                /*!< CH3EN (Bitfield-Mask: 0x01)                           */
#define TIMER0_CHCTL2_CH2NP_Pos           (11UL)                    /*!< CH2NP (Bit 11)                                        */
#define TIMER0_CHCTL2_CH2NP_Msk           (0x800UL)                 /*!< CH2NP (Bitfield-Mask: 0x01)                           */
#define TIMER0_CHCTL2_CH2NEN_Pos          (10UL)                    /*!< CH2NEN (Bit 10)                                       */
#define TIMER0_CHCTL2_CH2NEN_Msk          (0x400UL)                 /*!< CH2NEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_CHCTL2_CH2P_Pos            (9UL)                     /*!< CH2P (Bit 9)                                          */
#define TIMER0_CHCTL2_CH2P_Msk            (0x200UL)                 /*!< CH2P (Bitfield-Mask: 0x01)                            */
#define TIMER0_CHCTL2_CH2EN_Pos           (8UL)                     /*!< CH2EN (Bit 8)                                         */
#define TIMER0_CHCTL2_CH2EN_Msk           (0x100UL)                 /*!< CH2EN (Bitfield-Mask: 0x01)                           */
#define TIMER0_CHCTL2_CH1NP_Pos           (7UL)                     /*!< CH1NP (Bit 7)                                         */
#define TIMER0_CHCTL2_CH1NP_Msk           (0x80UL)                  /*!< CH1NP (Bitfield-Mask: 0x01)                           */
#define TIMER0_CHCTL2_CH1NEN_Pos          (6UL)                     /*!< CH1NEN (Bit 6)                                        */
#define TIMER0_CHCTL2_CH1NEN_Msk          (0x40UL)                  /*!< CH1NEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_CHCTL2_CH1P_Pos            (5UL)                     /*!< CH1P (Bit 5)                                          */
#define TIMER0_CHCTL2_CH1P_Msk            (0x20UL)                  /*!< CH1P (Bitfield-Mask: 0x01)                            */
#define TIMER0_CHCTL2_CH1EN_Pos           (4UL)                     /*!< CH1EN (Bit 4)                                         */
#define TIMER0_CHCTL2_CH1EN_Msk           (0x10UL)                  /*!< CH1EN (Bitfield-Mask: 0x01)                           */
#define TIMER0_CHCTL2_CH0NP_Pos           (3UL)                     /*!< CH0NP (Bit 3)                                         */
#define TIMER0_CHCTL2_CH0NP_Msk           (0x8UL)                   /*!< CH0NP (Bitfield-Mask: 0x01)                           */
#define TIMER0_CHCTL2_CH0NEN_Pos          (2UL)                     /*!< CH0NEN (Bit 2)                                        */
#define TIMER0_CHCTL2_CH0NEN_Msk          (0x4UL)                   /*!< CH0NEN (Bitfield-Mask: 0x01)                          */
#define TIMER0_CHCTL2_CH0P_Pos            (1UL)                     /*!< CH0P (Bit 1)                                          */
#define TIMER0_CHCTL2_CH0P_Msk            (0x2UL)                   /*!< CH0P (Bitfield-Mask: 0x01)                            */
#define TIMER0_CHCTL2_CH0EN_Pos           (0UL)                     /*!< CH0EN (Bit 0)                                         */
#define TIMER0_CHCTL2_CH0EN_Msk           (0x1UL)                   /*!< CH0EN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CNT  ========================================================== */
#define TIMER0_CNT_CNT_Pos                (0UL)                     /*!< CNT (Bit 0)                                           */
#define TIMER0_CNT_CNT_Msk                (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define TIMER0_PSC_PSC_Pos                (0UL)                     /*!< PSC (Bit 0)                                           */
#define TIMER0_PSC_PSC_Msk                (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CAR  ========================================================== */
#define TIMER0_CAR_CARL_Pos               (0UL)                     /*!< CARL (Bit 0)                                          */
#define TIMER0_CAR_CARL_Msk               (0xffffUL)                /*!< CARL (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CREP  ========================================================== */
#define TIMER0_CREP_CREP_Pos              (0UL)                     /*!< CREP (Bit 0)                                          */
#define TIMER0_CREP_CREP_Msk              (0xffUL)                  /*!< CREP (Bitfield-Mask: 0xff)                            */
/* =========================================================  CH0CV  ========================================================= */
#define TIMER0_CH0CV_CH0VAL_Pos           (0UL)                     /*!< CH0VAL (Bit 0)                                        */
#define TIMER0_CH0CV_CH0VAL_Msk           (0xffffUL)                /*!< CH0VAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CH1CV  ========================================================= */
#define TIMER0_CH1CV_CH1VAL_Pos           (0UL)                     /*!< CH1VAL (Bit 0)                                        */
#define TIMER0_CH1CV_CH1VAL_Msk           (0xffffUL)                /*!< CH1VAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CH2CV  ========================================================= */
#define TIMER0_CH2CV_CH2VAL_Pos           (0UL)                     /*!< CH2VAL (Bit 0)                                        */
#define TIMER0_CH2CV_CH2VAL_Msk           (0xffffUL)                /*!< CH2VAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CH3CV  ========================================================= */
#define TIMER0_CH3CV_CH3VAL_Pos           (0UL)                     /*!< CH3VAL (Bit 0)                                        */
#define TIMER0_CH3CV_CH3VAL_Msk           (0xffffUL)                /*!< CH3VAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CCHP  ========================================================== */
#define TIMER0_CCHP_POEN_Pos              (15UL)                    /*!< POEN (Bit 15)                                         */
#define TIMER0_CCHP_POEN_Msk              (0x8000UL)                /*!< POEN (Bitfield-Mask: 0x01)                            */
#define TIMER0_CCHP_OAEN_Pos              (14UL)                    /*!< OAEN (Bit 14)                                         */
#define TIMER0_CCHP_OAEN_Msk              (0x4000UL)                /*!< OAEN (Bitfield-Mask: 0x01)                            */
#define TIMER0_CCHP_BRKP_Pos              (13UL)                    /*!< BRKP (Bit 13)                                         */
#define TIMER0_CCHP_BRKP_Msk              (0x2000UL)                /*!< BRKP (Bitfield-Mask: 0x01)                            */
#define TIMER0_CCHP_BRKEN_Pos             (12UL)                    /*!< BRKEN (Bit 12)                                        */
#define TIMER0_CCHP_BRKEN_Msk             (0x1000UL)                /*!< BRKEN (Bitfield-Mask: 0x01)                           */
#define TIMER0_CCHP_ROS_Pos               (11UL)                    /*!< ROS (Bit 11)                                          */
#define TIMER0_CCHP_ROS_Msk               (0x800UL)                 /*!< ROS (Bitfield-Mask: 0x01)                             */
#define TIMER0_CCHP_IOS_Pos               (10UL)                    /*!< IOS (Bit 10)                                          */
#define TIMER0_CCHP_IOS_Msk               (0x400UL)                 /*!< IOS (Bitfield-Mask: 0x01)                             */
#define TIMER0_CCHP_PROT_Pos              (8UL)                     /*!< PROT (Bit 8)                                          */
#define TIMER0_CCHP_PROT_Msk              (0x300UL)                 /*!< PROT (Bitfield-Mask: 0x03)                            */
#define TIMER0_CCHP_DTCFG_Pos             (0UL)                     /*!< DTCFG (Bit 0)                                         */
#define TIMER0_CCHP_DTCFG_Msk             (0xffUL)                  /*!< DTCFG (Bitfield-Mask: 0xff)                           */
/* ========================================================  DMACFG  ========================================================= */
#define TIMER0_DMACFG_DMATC_Pos           (8UL)                     /*!< DMATC (Bit 8)                                         */
#define TIMER0_DMACFG_DMATC_Msk           (0x1f00UL)                /*!< DMATC (Bitfield-Mask: 0x1f)                           */
#define TIMER0_DMACFG_DMATA_Pos           (0UL)                     /*!< DMATA (Bit 0)                                         */
#define TIMER0_DMACFG_DMATA_Msk           (0x1fUL)                  /*!< DMATA (Bitfield-Mask: 0x1f)                           */
/* =========================================================  DMATB  ========================================================= */
#define TIMER0_DMATB_DMATB_Pos            (0UL)                     /*!< DMATB (Bit 0)                                         */
#define TIMER0_DMATB_DMATB_Msk            (0xffffUL)                /*!< DMATB (Bitfield-Mask: 0xffff)                         */


/* =========================================================================================================================== */
/* ================                                          TIMER1                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTL0  ========================================================== */
#define TIMER1_CTL0_CKDIV_Pos             (8UL)                     /*!< CKDIV (Bit 8)                                         */
#define TIMER1_CTL0_CKDIV_Msk             (0x300UL)                 /*!< CKDIV (Bitfield-Mask: 0x03)                           */
#define TIMER1_CTL0_ARSE_Pos              (7UL)                     /*!< ARSE (Bit 7)                                          */
#define TIMER1_CTL0_ARSE_Msk              (0x80UL)                  /*!< ARSE (Bitfield-Mask: 0x01)                            */
#define TIMER1_CTL0_CAM_Pos               (5UL)                     /*!< CAM (Bit 5)                                           */
#define TIMER1_CTL0_CAM_Msk               (0x60UL)                  /*!< CAM (Bitfield-Mask: 0x03)                             */
#define TIMER1_CTL0_DIR_Pos               (4UL)                     /*!< DIR (Bit 4)                                           */
#define TIMER1_CTL0_DIR_Msk               (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define TIMER1_CTL0_SPM_Pos               (3UL)                     /*!< SPM (Bit 3)                                           */
#define TIMER1_CTL0_SPM_Msk               (0x8UL)                   /*!< SPM (Bitfield-Mask: 0x01)                             */
#define TIMER1_CTL0_UPS_Pos               (2UL)                     /*!< UPS (Bit 2)                                           */
#define TIMER1_CTL0_UPS_Msk               (0x4UL)                   /*!< UPS (Bitfield-Mask: 0x01)                             */
#define TIMER1_CTL0_UPDIS_Pos             (1UL)                     /*!< UPDIS (Bit 1)                                         */
#define TIMER1_CTL0_UPDIS_Msk             (0x2UL)                   /*!< UPDIS (Bitfield-Mask: 0x01)                           */
#define TIMER1_CTL0_CEN_Pos               (0UL)                     /*!< CEN (Bit 0)                                           */
#define TIMER1_CTL0_CEN_Msk               (0x1UL)                   /*!< CEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  CTL1  ========================================================== */
#define TIMER1_CTL1_TI0S_Pos              (7UL)                     /*!< TI0S (Bit 7)                                          */
#define TIMER1_CTL1_TI0S_Msk              (0x80UL)                  /*!< TI0S (Bitfield-Mask: 0x01)                            */
#define TIMER1_CTL1_MMC_Pos               (4UL)                     /*!< MMC (Bit 4)                                           */
#define TIMER1_CTL1_MMC_Msk               (0x70UL)                  /*!< MMC (Bitfield-Mask: 0x07)                             */
#define TIMER1_CTL1_DMAS_Pos              (3UL)                     /*!< DMAS (Bit 3)                                          */
#define TIMER1_CTL1_DMAS_Msk              (0x8UL)                   /*!< DMAS (Bitfield-Mask: 0x01)                            */
/* =========================================================  SMCFG  ========================================================= */
#define TIMER1_SMCFG_ETP_Pos              (15UL)                    /*!< ETP (Bit 15)                                          */
#define TIMER1_SMCFG_ETP_Msk              (0x8000UL)                /*!< ETP (Bitfield-Mask: 0x01)                             */
#define TIMER1_SMCFG_SMC1_Pos             (14UL)                    /*!< SMC1 (Bit 14)                                         */
#define TIMER1_SMCFG_SMC1_Msk             (0x4000UL)                /*!< SMC1 (Bitfield-Mask: 0x01)                            */
#define TIMER1_SMCFG_ETPSC_Pos            (12UL)                    /*!< ETPSC (Bit 12)                                        */
#define TIMER1_SMCFG_ETPSC_Msk            (0x3000UL)                /*!< ETPSC (Bitfield-Mask: 0x03)                           */
#define TIMER1_SMCFG_ETFC_Pos             (8UL)                     /*!< ETFC (Bit 8)                                          */
#define TIMER1_SMCFG_ETFC_Msk             (0xf00UL)                 /*!< ETFC (Bitfield-Mask: 0x0f)                            */
#define TIMER1_SMCFG_MSM_Pos              (7UL)                     /*!< MSM (Bit 7)                                           */
#define TIMER1_SMCFG_MSM_Msk              (0x80UL)                  /*!< MSM (Bitfield-Mask: 0x01)                             */
#define TIMER1_SMCFG_TRGS_Pos             (4UL)                     /*!< TRGS (Bit 4)                                          */
#define TIMER1_SMCFG_TRGS_Msk             (0x70UL)                  /*!< TRGS (Bitfield-Mask: 0x07)                            */
#define TIMER1_SMCFG_SMC_Pos              (0UL)                     /*!< SMC (Bit 0)                                           */
#define TIMER1_SMCFG_SMC_Msk              (0x7UL)                   /*!< SMC (Bitfield-Mask: 0x07)                             */
/* =======================================================  DMAINTEN  ======================================================== */
#define TIMER1_DMAINTEN_TRGDEN_Pos        (14UL)                    /*!< TRGDEN (Bit 14)                                       */
#define TIMER1_DMAINTEN_TRGDEN_Msk        (0x4000UL)                /*!< TRGDEN (Bitfield-Mask: 0x01)                          */
#define TIMER1_DMAINTEN_CH3DEN_Pos        (12UL)                    /*!< CH3DEN (Bit 12)                                       */
#define TIMER1_DMAINTEN_CH3DEN_Msk        (0x1000UL)                /*!< CH3DEN (Bitfield-Mask: 0x01)                          */
#define TIMER1_DMAINTEN_CH2DEN_Pos        (11UL)                    /*!< CH2DEN (Bit 11)                                       */
#define TIMER1_DMAINTEN_CH2DEN_Msk        (0x800UL)                 /*!< CH2DEN (Bitfield-Mask: 0x01)                          */
#define TIMER1_DMAINTEN_CH1DEN_Pos        (10UL)                    /*!< CH1DEN (Bit 10)                                       */
#define TIMER1_DMAINTEN_CH1DEN_Msk        (0x400UL)                 /*!< CH1DEN (Bitfield-Mask: 0x01)                          */
#define TIMER1_DMAINTEN_CH0DEN_Pos        (9UL)                     /*!< CH0DEN (Bit 9)                                        */
#define TIMER1_DMAINTEN_CH0DEN_Msk        (0x200UL)                 /*!< CH0DEN (Bitfield-Mask: 0x01)                          */
#define TIMER1_DMAINTEN_UPDEN_Pos         (8UL)                     /*!< UPDEN (Bit 8)                                         */
#define TIMER1_DMAINTEN_UPDEN_Msk         (0x100UL)                 /*!< UPDEN (Bitfield-Mask: 0x01)                           */
#define TIMER1_DMAINTEN_TRGIE_Pos         (6UL)                     /*!< TRGIE (Bit 6)                                         */
#define TIMER1_DMAINTEN_TRGIE_Msk         (0x40UL)                  /*!< TRGIE (Bitfield-Mask: 0x01)                           */
#define TIMER1_DMAINTEN_CH3IE_Pos         (4UL)                     /*!< CH3IE (Bit 4)                                         */
#define TIMER1_DMAINTEN_CH3IE_Msk         (0x10UL)                  /*!< CH3IE (Bitfield-Mask: 0x01)                           */
#define TIMER1_DMAINTEN_CH2IE_Pos         (3UL)                     /*!< CH2IE (Bit 3)                                         */
#define TIMER1_DMAINTEN_CH2IE_Msk         (0x8UL)                   /*!< CH2IE (Bitfield-Mask: 0x01)                           */
#define TIMER1_DMAINTEN_CH1IE_Pos         (2UL)                     /*!< CH1IE (Bit 2)                                         */
#define TIMER1_DMAINTEN_CH1IE_Msk         (0x4UL)                   /*!< CH1IE (Bitfield-Mask: 0x01)                           */
#define TIMER1_DMAINTEN_CH0IE_Pos         (1UL)                     /*!< CH0IE (Bit 1)                                         */
#define TIMER1_DMAINTEN_CH0IE_Msk         (0x2UL)                   /*!< CH0IE (Bitfield-Mask: 0x01)                           */
#define TIMER1_DMAINTEN_UPIE_Pos          (0UL)                     /*!< UPIE (Bit 0)                                          */
#define TIMER1_DMAINTEN_UPIE_Msk          (0x1UL)                   /*!< UPIE (Bitfield-Mask: 0x01)                            */
/* =========================================================  INTF  ========================================================== */
#define TIMER1_INTF_CH3OF_Pos             (12UL)                    /*!< CH3OF (Bit 12)                                        */
#define TIMER1_INTF_CH3OF_Msk             (0x1000UL)                /*!< CH3OF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_CH2OF_Pos             (11UL)                    /*!< CH2OF (Bit 11)                                        */
#define TIMER1_INTF_CH2OF_Msk             (0x800UL)                 /*!< CH2OF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_CH1OF_Pos             (10UL)                    /*!< CH1OF (Bit 10)                                        */
#define TIMER1_INTF_CH1OF_Msk             (0x400UL)                 /*!< CH1OF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_CH0OF_Pos             (9UL)                     /*!< CH0OF (Bit 9)                                         */
#define TIMER1_INTF_CH0OF_Msk             (0x200UL)                 /*!< CH0OF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_TRGIF_Pos             (6UL)                     /*!< TRGIF (Bit 6)                                         */
#define TIMER1_INTF_TRGIF_Msk             (0x40UL)                  /*!< TRGIF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_CH3IF_Pos             (4UL)                     /*!< CH3IF (Bit 4)                                         */
#define TIMER1_INTF_CH3IF_Msk             (0x10UL)                  /*!< CH3IF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_CH2IF_Pos             (3UL)                     /*!< CH2IF (Bit 3)                                         */
#define TIMER1_INTF_CH2IF_Msk             (0x8UL)                   /*!< CH2IF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_CH1IF_Pos             (2UL)                     /*!< CH1IF (Bit 2)                                         */
#define TIMER1_INTF_CH1IF_Msk             (0x4UL)                   /*!< CH1IF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_CH0IF_Pos             (1UL)                     /*!< CH0IF (Bit 1)                                         */
#define TIMER1_INTF_CH0IF_Msk             (0x2UL)                   /*!< CH0IF (Bitfield-Mask: 0x01)                           */
#define TIMER1_INTF_UPIF_Pos              (0UL)                     /*!< UPIF (Bit 0)                                          */
#define TIMER1_INTF_UPIF_Msk              (0x1UL)                   /*!< UPIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  SWEVG  ========================================================= */
#define TIMER1_SWEVG_TRGG_Pos             (6UL)                     /*!< TRGG (Bit 6)                                          */
#define TIMER1_SWEVG_TRGG_Msk             (0x40UL)                  /*!< TRGG (Bitfield-Mask: 0x01)                            */
#define TIMER1_SWEVG_CH3G_Pos             (4UL)                     /*!< CH3G (Bit 4)                                          */
#define TIMER1_SWEVG_CH3G_Msk             (0x10UL)                  /*!< CH3G (Bitfield-Mask: 0x01)                            */
#define TIMER1_SWEVG_CH2G_Pos             (3UL)                     /*!< CH2G (Bit 3)                                          */
#define TIMER1_SWEVG_CH2G_Msk             (0x8UL)                   /*!< CH2G (Bitfield-Mask: 0x01)                            */
#define TIMER1_SWEVG_CH1G_Pos             (2UL)                     /*!< CH1G (Bit 2)                                          */
#define TIMER1_SWEVG_CH1G_Msk             (0x4UL)                   /*!< CH1G (Bitfield-Mask: 0x01)                            */
#define TIMER1_SWEVG_CH0G_Pos             (1UL)                     /*!< CH0G (Bit 1)                                          */
#define TIMER1_SWEVG_CH0G_Msk             (0x2UL)                   /*!< CH0G (Bitfield-Mask: 0x01)                            */
#define TIMER1_SWEVG_UPG_Pos              (0UL)                     /*!< UPG (Bit 0)                                           */
#define TIMER1_SWEVG_UPG_Msk              (0x1UL)                   /*!< UPG (Bitfield-Mask: 0x01)                             */
/* =====================================================  CHCTL0_Output  ===================================================== */
#define TIMER1_CHCTL0_Output_CH1COMCEN_Pos (15UL)                   /*!< CH1COMCEN (Bit 15)                                    */
#define TIMER1_CHCTL0_Output_CH1COMCEN_Msk (0x8000UL)               /*!< CH1COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL0_Output_CH1COMCTL_Pos (12UL)                   /*!< CH1COMCTL (Bit 12)                                    */
#define TIMER1_CHCTL0_Output_CH1COMCTL_Msk (0x7000UL)               /*!< CH1COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER1_CHCTL0_Output_CH1COMSEN_Pos (11UL)                   /*!< CH1COMSEN (Bit 11)                                    */
#define TIMER1_CHCTL0_Output_CH1COMSEN_Msk (0x800UL)                /*!< CH1COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL0_Output_CH1COMFEN_Pos (10UL)                   /*!< CH1COMFEN (Bit 10)                                    */
#define TIMER1_CHCTL0_Output_CH1COMFEN_Msk (0x400UL)                /*!< CH1COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL0_Output_CH1MS_Pos    (8UL)                     /*!< CH1MS (Bit 8)                                         */
#define TIMER1_CHCTL0_Output_CH1MS_Msk    (0x300UL)                 /*!< CH1MS (Bitfield-Mask: 0x03)                           */
#define TIMER1_CHCTL0_Output_CH0COMCEN_Pos (7UL)                    /*!< CH0COMCEN (Bit 7)                                     */
#define TIMER1_CHCTL0_Output_CH0COMCEN_Msk (0x80UL)                 /*!< CH0COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL0_Output_CH0COMCTL_Pos (4UL)                    /*!< CH0COMCTL (Bit 4)                                     */
#define TIMER1_CHCTL0_Output_CH0COMCTL_Msk (0x70UL)                 /*!< CH0COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER1_CHCTL0_Output_CH0COMSEN_Pos (3UL)                    /*!< CH0COMSEN (Bit 3)                                     */
#define TIMER1_CHCTL0_Output_CH0COMSEN_Msk (0x8UL)                  /*!< CH0COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL0_Output_CH0COMFEN_Pos (2UL)                    /*!< CH0COMFEN (Bit 2)                                     */
#define TIMER1_CHCTL0_Output_CH0COMFEN_Msk (0x4UL)                  /*!< CH0COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL0_Output_CH0MS_Pos    (0UL)                     /*!< CH0MS (Bit 0)                                         */
#define TIMER1_CHCTL0_Output_CH0MS_Msk    (0x3UL)                   /*!< CH0MS (Bitfield-Mask: 0x03)                           */
/* =====================================================  CHCTL0_Input  ====================================================== */
#define TIMER1_CHCTL0_Input_CH1CAPFLT_Pos (12UL)                    /*!< CH1CAPFLT (Bit 12)                                    */
#define TIMER1_CHCTL0_Input_CH1CAPFLT_Msk (0xf000UL)                /*!< CH1CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER1_CHCTL0_Input_CH1CAPPSC_Pos (10UL)                    /*!< CH1CAPPSC (Bit 10)                                    */
#define TIMER1_CHCTL0_Input_CH1CAPPSC_Msk (0xc00UL)                 /*!< CH1CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER1_CHCTL0_Input_CH1MS_Pos     (8UL)                     /*!< CH1MS (Bit 8)                                         */
#define TIMER1_CHCTL0_Input_CH1MS_Msk     (0x300UL)                 /*!< CH1MS (Bitfield-Mask: 0x03)                           */
#define TIMER1_CHCTL0_Input_CH0CAPFLT_Pos (4UL)                     /*!< CH0CAPFLT (Bit 4)                                     */
#define TIMER1_CHCTL0_Input_CH0CAPFLT_Msk (0xf0UL)                  /*!< CH0CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER1_CHCTL0_Input_CH0CAPPSC_Pos (2UL)                     /*!< CH0CAPPSC (Bit 2)                                     */
#define TIMER1_CHCTL0_Input_CH0CAPPSC_Msk (0xcUL)                   /*!< CH0CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER1_CHCTL0_Input_CH0MS_Pos     (0UL)                     /*!< CH0MS (Bit 0)                                         */
#define TIMER1_CHCTL0_Input_CH0MS_Msk     (0x3UL)                   /*!< CH0MS (Bitfield-Mask: 0x03)                           */
/* =====================================================  CHCTL1_Output  ===================================================== */
#define TIMER1_CHCTL1_Output_CH3COMCEN_Pos (15UL)                   /*!< CH3COMCEN (Bit 15)                                    */
#define TIMER1_CHCTL1_Output_CH3COMCEN_Msk (0x8000UL)               /*!< CH3COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL1_Output_CH3COMCTL_Pos (12UL)                   /*!< CH3COMCTL (Bit 12)                                    */
#define TIMER1_CHCTL1_Output_CH3COMCTL_Msk (0x7000UL)               /*!< CH3COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER1_CHCTL1_Output_CH3COMSEN_Pos (11UL)                   /*!< CH3COMSEN (Bit 11)                                    */
#define TIMER1_CHCTL1_Output_CH3COMSEN_Msk (0x800UL)                /*!< CH3COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL1_Output_CH3COMFEN_Pos (10UL)                   /*!< CH3COMFEN (Bit 10)                                    */
#define TIMER1_CHCTL1_Output_CH3COMFEN_Msk (0x400UL)                /*!< CH3COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL1_Output_CH3MS_Pos    (8UL)                     /*!< CH3MS (Bit 8)                                         */
#define TIMER1_CHCTL1_Output_CH3MS_Msk    (0x300UL)                 /*!< CH3MS (Bitfield-Mask: 0x03)                           */
#define TIMER1_CHCTL1_Output_CH2COMCEN_Pos (7UL)                    /*!< CH2COMCEN (Bit 7)                                     */
#define TIMER1_CHCTL1_Output_CH2COMCEN_Msk (0x80UL)                 /*!< CH2COMCEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL1_Output_CH2COMCTL_Pos (4UL)                    /*!< CH2COMCTL (Bit 4)                                     */
#define TIMER1_CHCTL1_Output_CH2COMCTL_Msk (0x70UL)                 /*!< CH2COMCTL (Bitfield-Mask: 0x07)                       */
#define TIMER1_CHCTL1_Output_CH2COMSEN_Pos (3UL)                    /*!< CH2COMSEN (Bit 3)                                     */
#define TIMER1_CHCTL1_Output_CH2COMSEN_Msk (0x8UL)                  /*!< CH2COMSEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL1_Output_CH2COMFEN_Pos (2UL)                    /*!< CH2COMFEN (Bit 2)                                     */
#define TIMER1_CHCTL1_Output_CH2COMFEN_Msk (0x4UL)                  /*!< CH2COMFEN (Bitfield-Mask: 0x01)                       */
#define TIMER1_CHCTL1_Output_CH2MS_Pos    (0UL)                     /*!< CH2MS (Bit 0)                                         */
#define TIMER1_CHCTL1_Output_CH2MS_Msk    (0x3UL)                   /*!< CH2MS (Bitfield-Mask: 0x03)                           */
/* =====================================================  CHCTL1_Input  ====================================================== */
#define TIMER1_CHCTL1_Input_CH3CAPFLT_Pos (12UL)                    /*!< CH3CAPFLT (Bit 12)                                    */
#define TIMER1_CHCTL1_Input_CH3CAPFLT_Msk (0xf000UL)                /*!< CH3CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER1_CHCTL1_Input_CH3CAPPSC_Pos (10UL)                    /*!< CH3CAPPSC (Bit 10)                                    */
#define TIMER1_CHCTL1_Input_CH3CAPPSC_Msk (0xc00UL)                 /*!< CH3CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER1_CHCTL1_Input_CH3MS_Pos     (8UL)                     /*!< CH3MS (Bit 8)                                         */
#define TIMER1_CHCTL1_Input_CH3MS_Msk     (0x300UL)                 /*!< CH3MS (Bitfield-Mask: 0x03)                           */
#define TIMER1_CHCTL1_Input_CH2CAPFLT_Pos (4UL)                     /*!< CH2CAPFLT (Bit 4)                                     */
#define TIMER1_CHCTL1_Input_CH2CAPFLT_Msk (0xf0UL)                  /*!< CH2CAPFLT (Bitfield-Mask: 0x0f)                       */
#define TIMER1_CHCTL1_Input_CH2CAPPSC_Pos (2UL)                     /*!< CH2CAPPSC (Bit 2)                                     */
#define TIMER1_CHCTL1_Input_CH2CAPPSC_Msk (0xcUL)                   /*!< CH2CAPPSC (Bitfield-Mask: 0x03)                       */
#define TIMER1_CHCTL1_Input_CH2MS_Pos     (0UL)                     /*!< CH2MS (Bit 0)                                         */
#define TIMER1_CHCTL1_Input_CH2MS_Msk     (0x3UL)                   /*!< CH2MS (Bitfield-Mask: 0x03)                           */
/* ========================================================  CHCTL2  ========================================================= */
#define TIMER1_CHCTL2_CH3P_Pos            (13UL)                    /*!< CH3P (Bit 13)                                         */
#define TIMER1_CHCTL2_CH3P_Msk            (0x2000UL)                /*!< CH3P (Bitfield-Mask: 0x01)                            */
#define TIMER1_CHCTL2_CH3EN_Pos           (12UL)                    /*!< CH3EN (Bit 12)                                        */
#define TIMER1_CHCTL2_CH3EN_Msk           (0x1000UL)                /*!< CH3EN (Bitfield-Mask: 0x01)                           */
#define TIMER1_CHCTL2_CH2P_Pos            (9UL)                     /*!< CH2P (Bit 9)                                          */
#define TIMER1_CHCTL2_CH2P_Msk            (0x200UL)                 /*!< CH2P (Bitfield-Mask: 0x01)                            */
#define TIMER1_CHCTL2_CH2EN_Pos           (8UL)                     /*!< CH2EN (Bit 8)                                         */
#define TIMER1_CHCTL2_CH2EN_Msk           (0x100UL)                 /*!< CH2EN (Bitfield-Mask: 0x01)                           */
#define TIMER1_CHCTL2_CH1P_Pos            (5UL)                     /*!< CH1P (Bit 5)                                          */
#define TIMER1_CHCTL2_CH1P_Msk            (0x20UL)                  /*!< CH1P (Bitfield-Mask: 0x01)                            */
#define TIMER1_CHCTL2_CH1EN_Pos           (4UL)                     /*!< CH1EN (Bit 4)                                         */
#define TIMER1_CHCTL2_CH1EN_Msk           (0x10UL)                  /*!< CH1EN (Bitfield-Mask: 0x01)                           */
#define TIMER1_CHCTL2_CH0P_Pos            (1UL)                     /*!< CH0P (Bit 1)                                          */
#define TIMER1_CHCTL2_CH0P_Msk            (0x2UL)                   /*!< CH0P (Bitfield-Mask: 0x01)                            */
#define TIMER1_CHCTL2_CH0EN_Pos           (0UL)                     /*!< CH0EN (Bit 0)                                         */
#define TIMER1_CHCTL2_CH0EN_Msk           (0x1UL)                   /*!< CH0EN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CNT  ========================================================== */
#define TIMER1_CNT_CNT_Pos                (0UL)                     /*!< CNT (Bit 0)                                           */
#define TIMER1_CNT_CNT_Msk                (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define TIMER1_PSC_PSC_Pos                (0UL)                     /*!< PSC (Bit 0)                                           */
#define TIMER1_PSC_PSC_Msk                (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CAR  ========================================================== */
#define TIMER1_CAR_CARL_Pos               (0UL)                     /*!< CARL (Bit 0)                                          */
#define TIMER1_CAR_CARL_Msk               (0xffffUL)                /*!< CARL (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CH0CV  ========================================================= */
#define TIMER1_CH0CV_CH0VAL_Pos           (0UL)                     /*!< CH0VAL (Bit 0)                                        */
#define TIMER1_CH0CV_CH0VAL_Msk           (0xffffUL)                /*!< CH0VAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CH1CV  ========================================================= */
#define TIMER1_CH1CV_CH1VAL_Pos           (0UL)                     /*!< CH1VAL (Bit 0)                                        */
#define TIMER1_CH1CV_CH1VAL_Msk           (0xffffUL)                /*!< CH1VAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CH2CV  ========================================================= */
#define TIMER1_CH2CV_CH2VAL_Pos           (0UL)                     /*!< CH2VAL (Bit 0)                                        */
#define TIMER1_CH2CV_CH2VAL_Msk           (0xffffUL)                /*!< CH2VAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CH3CV  ========================================================= */
#define TIMER1_CH3CV_CH3VAL_Pos           (0UL)                     /*!< CH3VAL (Bit 0)                                        */
#define TIMER1_CH3CV_CH3VAL_Msk           (0xffffUL)                /*!< CH3VAL (Bitfield-Mask: 0xffff)                        */
/* ========================================================  DMACFG  ========================================================= */
#define TIMER1_DMACFG_DMATC_Pos           (8UL)                     /*!< DMATC (Bit 8)                                         */
#define TIMER1_DMACFG_DMATC_Msk           (0x1f00UL)                /*!< DMATC (Bitfield-Mask: 0x1f)                           */
#define TIMER1_DMACFG_DMATA_Pos           (0UL)                     /*!< DMATA (Bit 0)                                         */
#define TIMER1_DMACFG_DMATA_Msk           (0x1fUL)                  /*!< DMATA (Bitfield-Mask: 0x1f)                           */
/* =========================================================  DMATB  ========================================================= */
#define TIMER1_DMATB_DMATB_Pos            (0UL)                     /*!< DMATB (Bit 0)                                         */
#define TIMER1_DMATB_DMATB_Msk            (0xffffUL)                /*!< DMATB (Bitfield-Mask: 0xffff)                         */


/* =========================================================================================================================== */
/* ================                                          TIMER5                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTL0  ========================================================== */
#define TIMER5_CTL0_ARSE_Pos              (7UL)                     /*!< ARSE (Bit 7)                                          */
#define TIMER5_CTL0_ARSE_Msk              (0x80UL)                  /*!< ARSE (Bitfield-Mask: 0x01)                            */
#define TIMER5_CTL0_SPM_Pos               (3UL)                     /*!< SPM (Bit 3)                                           */
#define TIMER5_CTL0_SPM_Msk               (0x8UL)                   /*!< SPM (Bitfield-Mask: 0x01)                             */
#define TIMER5_CTL0_UPS_Pos               (2UL)                     /*!< UPS (Bit 2)                                           */
#define TIMER5_CTL0_UPS_Msk               (0x4UL)                   /*!< UPS (Bitfield-Mask: 0x01)                             */
#define TIMER5_CTL0_UPDIS_Pos             (1UL)                     /*!< UPDIS (Bit 1)                                         */
#define TIMER5_CTL0_UPDIS_Msk             (0x2UL)                   /*!< UPDIS (Bitfield-Mask: 0x01)                           */
#define TIMER5_CTL0_CEN_Pos               (0UL)                     /*!< CEN (Bit 0)                                           */
#define TIMER5_CTL0_CEN_Msk               (0x1UL)                   /*!< CEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  CTL1  ========================================================== */
#define TIMER5_CTL1_MMC_Pos               (4UL)                     /*!< MMC (Bit 4)                                           */
#define TIMER5_CTL1_MMC_Msk               (0x70UL)                  /*!< MMC (Bitfield-Mask: 0x07)                             */
/* =======================================================  DMAINTEN  ======================================================== */
#define TIMER5_DMAINTEN_UPDEN_Pos         (8UL)                     /*!< UPDEN (Bit 8)                                         */
#define TIMER5_DMAINTEN_UPDEN_Msk         (0x100UL)                 /*!< UPDEN (Bitfield-Mask: 0x01)                           */
#define TIMER5_DMAINTEN_UPIE_Pos          (0UL)                     /*!< UPIE (Bit 0)                                          */
#define TIMER5_DMAINTEN_UPIE_Msk          (0x1UL)                   /*!< UPIE (Bitfield-Mask: 0x01)                            */
/* =========================================================  INTF  ========================================================== */
#define TIMER5_INTF_UPIF_Pos              (0UL)                     /*!< UPIF (Bit 0)                                          */
#define TIMER5_INTF_UPIF_Msk              (0x1UL)                   /*!< UPIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  SWEVG  ========================================================= */
#define TIMER5_SWEVG_UPG_Pos              (0UL)                     /*!< UPG (Bit 0)                                           */
#define TIMER5_SWEVG_UPG_Msk              (0x1UL)                   /*!< UPG (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CNT  ========================================================== */
#define TIMER5_CNT_CNT_Pos                (0UL)                     /*!< CNT (Bit 0)                                           */
#define TIMER5_CNT_CNT_Msk                (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define TIMER5_PSC_PSC_Pos                (0UL)                     /*!< PSC (Bit 0)                                           */
#define TIMER5_PSC_PSC_Msk                (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CAR  ========================================================== */
#define TIMER5_CAR_CARL_Pos               (0UL)                     /*!< CARL (Bit 0)                                          */
#define TIMER5_CAR_CARL_Msk               (0xffffUL)                /*!< CARL (Bitfield-Mask: 0xffff)                          */


/* =========================================================================================================================== */
/* ================                                          USART                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  STAT  ========================================================== */
#define USART_STAT_CTSF_Pos              (9UL)                     /*!< CTSF (Bit 9)                                          */
#define USART_STAT_CTSF_Msk              (0x200UL)                 /*!< CTSF (Bitfield-Mask: 0x01)                            */
#define USART_STAT_LBDF_Pos              (8UL)                     /*!< LBDF (Bit 8)                                          */
#define USART_STAT_LBDF_Msk              (0x100UL)                 /*!< LBDF (Bitfield-Mask: 0x01)                            */
#define USART_STAT_TBE_Pos               (7UL)                     /*!< TBE (Bit 7)                                           */
#define USART_STAT_TBE_Msk               (0x80UL)                  /*!< TBE (Bitfield-Mask: 0x01)                             */
#define USART_STAT_TC_Pos                (6UL)                     /*!< TC (Bit 6)                                            */
#define USART_STAT_TC_Msk                (0x40UL)                  /*!< TC (Bitfield-Mask: 0x01)                              */
#define USART_STAT_RBNE_Pos              (5UL)                     /*!< RBNE (Bit 5)                                          */
#define USART_STAT_RBNE_Msk              (0x20UL)                  /*!< RBNE (Bitfield-Mask: 0x01)                            */
#define USART_STAT_IDLEF_Pos             (4UL)                     /*!< IDLEF (Bit 4)                                         */
#define USART_STAT_IDLEF_Msk             (0x10UL)                  /*!< IDLEF (Bitfield-Mask: 0x01)                           */
#define USART_STAT_ORERR_Pos             (3UL)                     /*!< ORERR (Bit 3)                                         */
#define USART_STAT_ORERR_Msk             (0x8UL)                   /*!< ORERR (Bitfield-Mask: 0x01)                           */
#define USART_STAT_NERR_Pos              (2UL)                     /*!< NERR (Bit 2)                                          */
#define USART_STAT_NERR_Msk              (0x4UL)                   /*!< NERR (Bitfield-Mask: 0x01)                            */
#define USART_STAT_FERR_Pos              (1UL)                     /*!< FERR (Bit 1)                                          */
#define USART_STAT_FERR_Msk              (0x2UL)                   /*!< FERR (Bitfield-Mask: 0x01)                            */
#define USART_STAT_PERR_Pos              (0UL)                     /*!< PERR (Bit 0)                                          */
#define USART_STAT_PERR_Msk              (0x1UL)                   /*!< PERR (Bitfield-Mask: 0x01)                            */
/* =========================================================  DATA  ========================================================== */
#define USART_DATA_DATA_Pos              (0UL)                     /*!< DATA (Bit 0)                                          */
#define USART_DATA_DATA_Msk              (0x1ffUL)                 /*!< DATA (Bitfield-Mask: 0x1ff)                           */
/* =========================================================  BAUD  ========================================================== */
#define USART_BAUD_INTDIV_Pos            (4UL)                     /*!< INTDIV (Bit 4)                                        */
#define USART_BAUD_INTDIV_Msk            (0xfff0UL)                /*!< INTDIV (Bitfield-Mask: 0xfff)                         */
#define USART_BAUD_FRADIV_Pos            (0UL)                     /*!< FRADIV (Bit 0)                                        */
#define USART_BAUD_FRADIV_Msk            (0xfUL)                   /*!< FRADIV (Bitfield-Mask: 0x0f)                          */
/* =========================================================  CTL0  ========================================================== */
#define USART_CTL0_UEN_Pos               (13UL)                    /*!< UEN (Bit 13)                                          */
#define USART_CTL0_UEN_Msk               (0x2000UL)                /*!< UEN (Bitfield-Mask: 0x01)                             */
#define USART_CTL0_WL_Pos                (12UL)                    /*!< WL (Bit 12)                                           */
#define USART_CTL0_WL_Msk                (0x1000UL)                /*!< WL (Bitfield-Mask: 0x01)                              */
#define USART_CTL0_WM_Pos                (11UL)                    /*!< WM (Bit 11)                                           */
#define USART_CTL0_WM_Msk                (0x800UL)                 /*!< WM (Bitfield-Mask: 0x01)                              */
#define USART_CTL0_PCEN_Pos              (10UL)                    /*!< PCEN (Bit 10)                                         */
#define USART_CTL0_PCEN_Msk              (0x400UL)                 /*!< PCEN (Bitfield-Mask: 0x01)                            */
#define USART_CTL0_PM_Pos                (9UL)                     /*!< PM (Bit 9)                                            */
#define USART_CTL0_PM_Msk                (0x200UL)                 /*!< PM (Bitfield-Mask: 0x01)                              */
#define USART_CTL0_PERRIE_Pos            (8UL)                     /*!< PERRIE (Bit 8)                                        */
#define USART_CTL0_PERRIE_Msk            (0x100UL)                 /*!< PERRIE (Bitfield-Mask: 0x01)                          */
#define USART_CTL0_TBEIE_Pos             (7UL)                     /*!< TBEIE (Bit 7)                                         */
#define USART_CTL0_TBEIE_Msk             (0x80UL)                  /*!< TBEIE (Bitfield-Mask: 0x01)                           */
#define USART_CTL0_TCIE_Pos              (6UL)                     /*!< TCIE (Bit 6)                                          */
#define USART_CTL0_TCIE_Msk              (0x40UL)                  /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define USART_CTL0_RBNEIE_Pos            (5UL)                     /*!< RBNEIE (Bit 5)                                        */
#define USART_CTL0_RBNEIE_Msk            (0x20UL)                  /*!< RBNEIE (Bitfield-Mask: 0x01)                          */
#define USART_CTL0_IDLEIE_Pos            (4UL)                     /*!< IDLEIE (Bit 4)                                        */
#define USART_CTL0_IDLEIE_Msk            (0x10UL)                  /*!< IDLEIE (Bitfield-Mask: 0x01)                          */
#define USART_CTL0_TEN_Pos               (3UL)                     /*!< TEN (Bit 3)                                           */
#define USART_CTL0_TEN_Msk               (0x8UL)                   /*!< TEN (Bitfield-Mask: 0x01)                             */
#define USART_CTL0_REN_Pos               (2UL)                     /*!< REN (Bit 2)                                           */
#define USART_CTL0_REN_Msk               (0x4UL)                   /*!< REN (Bitfield-Mask: 0x01)                             */
#define USART_CTL0_RWU_Pos               (1UL)                     /*!< RWU (Bit 1)                                           */
#define USART_CTL0_RWU_Msk               (0x2UL)                   /*!< RWU (Bitfield-Mask: 0x01)                             */
#define USART_CTL0_SBKCMD_Pos            (0UL)                     /*!< SBKCMD (Bit 0)                                        */
#define USART_CTL0_SBKCMD_Msk            (0x1UL)                   /*!< SBKCMD (Bitfield-Mask: 0x01)                          */
/* =========================================================  CTL1  ========================================================== */
#define USART_CTL1_LMEN_Pos              (14UL)                    /*!< LMEN (Bit 14)                                         */
#define USART_CTL1_LMEN_Msk              (0x4000UL)                /*!< LMEN (Bitfield-Mask: 0x01)                            */
#define USART_CTL1_STB_Pos               (12UL)                    /*!< STB (Bit 12)                                          */
#define USART_CTL1_STB_Msk               (0x3000UL)                /*!< STB (Bitfield-Mask: 0x03)                             */
#define USART_CTL1_CKEN_Pos              (11UL)                    /*!< CKEN (Bit 11)                                         */
#define USART_CTL1_CKEN_Msk              (0x800UL)                 /*!< CKEN (Bitfield-Mask: 0x01)                            */
#define USART_CTL1_CPL_Pos               (10UL)                    /*!< CPL (Bit 10)                                          */
#define USART_CTL1_CPL_Msk               (0x400UL)                 /*!< CPL (Bitfield-Mask: 0x01)                             */
#define USART_CTL1_CPH_Pos               (9UL)                     /*!< CPH (Bit 9)                                           */
#define USART_CTL1_CPH_Msk               (0x200UL)                 /*!< CPH (Bitfield-Mask: 0x01)                             */
#define USART_CTL1_CLEN_Pos              (8UL)                     /*!< CLEN (Bit 8)                                          */
#define USART_CTL1_CLEN_Msk              (0x100UL)                 /*!< CLEN (Bitfield-Mask: 0x01)                            */
#define USART_CTL1_LBDIE_Pos             (6UL)                     /*!< LBDIE (Bit 6)                                         */
#define USART_CTL1_LBDIE_Msk             (0x40UL)                  /*!< LBDIE (Bitfield-Mask: 0x01)                           */
#define USART_CTL1_LBLEN_Pos             (5UL)                     /*!< LBLEN (Bit 5)                                         */
#define USART_CTL1_LBLEN_Msk             (0x20UL)                  /*!< LBLEN (Bitfield-Mask: 0x01)                           */
#define USART_CTL1_ADDR_Pos              (0UL)                     /*!< ADDR (Bit 0)                                          */
#define USART_CTL1_ADDR_Msk              (0xfUL)                   /*!< ADDR (Bitfield-Mask: 0x0f)                            */
/* =========================================================  CTL2  ========================================================== */
#define USART_CTL2_CTSIE_Pos             (10UL)                    /*!< CTSIE (Bit 10)                                        */
#define USART_CTL2_CTSIE_Msk             (0x400UL)                 /*!< CTSIE (Bitfield-Mask: 0x01)                           */
#define USART_CTL2_CTSEN_Pos             (9UL)                     /*!< CTSEN (Bit 9)                                         */
#define USART_CTL2_CTSEN_Msk             (0x200UL)                 /*!< CTSEN (Bitfield-Mask: 0x01)                           */
#define USART_CTL2_RTSEN_Pos             (8UL)                     /*!< RTSEN (Bit 8)                                         */
#define USART_CTL2_RTSEN_Msk             (0x100UL)                 /*!< RTSEN (Bitfield-Mask: 0x01)                           */
#define USART_CTL2_DENT_Pos              (7UL)                     /*!< DENT (Bit 7)                                          */
#define USART_CTL2_DENT_Msk              (0x80UL)                  /*!< DENT (Bitfield-Mask: 0x01)                            */
#define USART_CTL2_DENR_Pos              (6UL)                     /*!< DENR (Bit 6)                                          */
#define USART_CTL2_DENR_Msk              (0x40UL)                  /*!< DENR (Bitfield-Mask: 0x01)                            */
#define USART_CTL2_SCEN_Pos              (5UL)                     /*!< SCEN (Bit 5)                                          */
#define USART_CTL2_SCEN_Msk              (0x20UL)                  /*!< SCEN (Bitfield-Mask: 0x01)                            */
#define USART_CTL2_NKEN_Pos              (4UL)                     /*!< NKEN (Bit 4)                                          */
#define USART_CTL2_NKEN_Msk              (0x10UL)                  /*!< NKEN (Bitfield-Mask: 0x01)                            */
#define USART_CTL2_HDEN_Pos              (3UL)                     /*!< HDEN (Bit 3)                                          */
#define USART_CTL2_HDEN_Msk              (0x8UL)                   /*!< HDEN (Bitfield-Mask: 0x01)                            */
#define USART_CTL2_IRLP_Pos              (2UL)                     /*!< IRLP (Bit 2)                                          */
#define USART_CTL2_IRLP_Msk              (0x4UL)                   /*!< IRLP (Bitfield-Mask: 0x01)                            */
#define USART_CTL2_IREN_Pos              (1UL)                     /*!< IREN (Bit 1)                                          */
#define USART_CTL2_IREN_Msk              (0x2UL)                   /*!< IREN (Bitfield-Mask: 0x01)                            */
#define USART_CTL2_ERRIE_Pos             (0UL)                     /*!< ERRIE (Bit 0)                                         */
#define USART_CTL2_ERRIE_Msk             (0x1UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  GP  =========================================================== */
#define USART_GP_GUAT_Pos                (8UL)                     /*!< GUAT (Bit 8)                                          */
#define USART_GP_GUAT_Msk                (0xff00UL)                /*!< GUAT (Bitfield-Mask: 0xff)                            */
#define USART_GP_PSC_Pos                 (0UL)                     /*!< PSC (Bit 0)                                           */
#define USART_GP_PSC_Msk                 (0xffUL)                  /*!< PSC (Bitfield-Mask: 0xff)                             */


/* =========================================================================================================================== */
/* ================                                           UART                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  STAT  ========================================================== */
#define UART_STAT_LBDF_Pos               (8UL)                     /*!< LBDF (Bit 8)                                          */
#define UART_STAT_LBDF_Msk               (0x100UL)                 /*!< LBDF (Bitfield-Mask: 0x01)                            */
#define UART_STAT_TBE_Pos                (7UL)                     /*!< TBE (Bit 7)                                           */
#define UART_STAT_TBE_Msk                (0x80UL)                  /*!< TBE (Bitfield-Mask: 0x01)                             */
#define UART_STAT_TC_Pos                 (6UL)                     /*!< TC (Bit 6)                                            */
#define UART_STAT_TC_Msk                 (0x40UL)                  /*!< TC (Bitfield-Mask: 0x01)                              */
#define UART_STAT_RBNE_Pos               (5UL)                     /*!< RBNE (Bit 5)                                          */
#define UART_STAT_RBNE_Msk               (0x20UL)                  /*!< RBNE (Bitfield-Mask: 0x01)                            */
#define UART_STAT_IDLEF_Pos              (4UL)                     /*!< IDLEF (Bit 4)                                         */
#define UART_STAT_IDLEF_Msk              (0x10UL)                  /*!< IDLEF (Bitfield-Mask: 0x01)                           */
#define UART_STAT_ORERR_Pos              (3UL)                     /*!< ORERR (Bit 3)                                         */
#define UART_STAT_ORERR_Msk              (0x8UL)                   /*!< ORERR (Bitfield-Mask: 0x01)                           */
#define UART_STAT_NERR_Pos               (2UL)                     /*!< NERR (Bit 2)                                          */
#define UART_STAT_NERR_Msk               (0x4UL)                   /*!< NERR (Bitfield-Mask: 0x01)                            */
#define UART_STAT_FERR_Pos               (1UL)                     /*!< FERR (Bit 1)                                          */
#define UART_STAT_FERR_Msk               (0x2UL)                   /*!< FERR (Bitfield-Mask: 0x01)                            */
#define UART_STAT_PERR_Pos               (0UL)                     /*!< PERR (Bit 0)                                          */
#define UART_STAT_PERR_Msk               (0x1UL)                   /*!< PERR (Bitfield-Mask: 0x01)                            */
/* =========================================================  DATA  ========================================================== */
#define UART_DATA_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define UART_DATA_DATA_Msk               (0x1ffUL)                 /*!< DATA (Bitfield-Mask: 0x1ff)                           */
/* =========================================================  BAUD  ========================================================== */
#define UART_BAUD_INTDIV_Pos             (4UL)                     /*!< INTDIV (Bit 4)                                        */
#define UART_BAUD_INTDIV_Msk             (0xfff0UL)                /*!< INTDIV (Bitfield-Mask: 0xfff)                         */
#define UART_BAUD_FRADIV_Pos             (0UL)                     /*!< FRADIV (Bit 0)                                        */
#define UART_BAUD_FRADIV_Msk             (0xfUL)                   /*!< FRADIV (Bitfield-Mask: 0x0f)                          */
/* =========================================================  CTL0  ========================================================== */
#define UART_CTL0_UEN_Pos                (13UL)                    /*!< UEN (Bit 13)                                          */
#define UART_CTL0_UEN_Msk                (0x2000UL)                /*!< UEN (Bitfield-Mask: 0x01)                             */
#define UART_CTL0_WL_Pos                 (12UL)                    /*!< WL (Bit 12)                                           */
#define UART_CTL0_WL_Msk                 (0x1000UL)                /*!< WL (Bitfield-Mask: 0x01)                              */
#define UART_CTL0_WM_Pos                 (11UL)                    /*!< WM (Bit 11)                                           */
#define UART_CTL0_WM_Msk                 (0x800UL)                 /*!< WM (Bitfield-Mask: 0x01)                              */
#define UART_CTL0_PCEN_Pos               (10UL)                    /*!< PCEN (Bit 10)                                         */
#define UART_CTL0_PCEN_Msk               (0x400UL)                 /*!< PCEN (Bitfield-Mask: 0x01)                            */
#define UART_CTL0_PM_Pos                 (9UL)                     /*!< PM (Bit 9)                                            */
#define UART_CTL0_PM_Msk                 (0x200UL)                 /*!< PM (Bitfield-Mask: 0x01)                              */
#define UART_CTL0_PERRIE_Pos             (8UL)                     /*!< PERRIE (Bit 8)                                        */
#define UART_CTL0_PERRIE_Msk             (0x100UL)                 /*!< PERRIE (Bitfield-Mask: 0x01)                          */
#define UART_CTL0_TBEIE_Pos              (7UL)                     /*!< TBEIE (Bit 7)                                         */
#define UART_CTL0_TBEIE_Msk              (0x80UL)                  /*!< TBEIE (Bitfield-Mask: 0x01)                           */
#define UART_CTL0_TCIE_Pos               (6UL)                     /*!< TCIE (Bit 6)                                          */
#define UART_CTL0_TCIE_Msk               (0x40UL)                  /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define UART_CTL0_RBNEIE_Pos             (5UL)                     /*!< RBNEIE (Bit 5)                                        */
#define UART_CTL0_RBNEIE_Msk             (0x20UL)                  /*!< RBNEIE (Bitfield-Mask: 0x01)                          */
#define UART_CTL0_IDLEIE_Pos             (4UL)                     /*!< IDLEIE (Bit 4)                                        */
#define UART_CTL0_IDLEIE_Msk             (0x10UL)                  /*!< IDLEIE (Bitfield-Mask: 0x01)                          */
#define UART_CTL0_TEN_Pos                (3UL)                     /*!< TEN (Bit 3)                                           */
#define UART_CTL0_TEN_Msk                (0x8UL)                   /*!< TEN (Bitfield-Mask: 0x01)                             */
#define UART_CTL0_REN_Pos                (2UL)                     /*!< REN (Bit 2)                                           */
#define UART_CTL0_REN_Msk                (0x4UL)                   /*!< REN (Bitfield-Mask: 0x01)                             */
#define UART_CTL0_RWU_Pos                (1UL)                     /*!< RWU (Bit 1)                                           */
#define UART_CTL0_RWU_Msk                (0x2UL)                   /*!< RWU (Bitfield-Mask: 0x01)                             */
#define UART_CTL0_SBKCMD_Pos             (0UL)                     /*!< SBKCMD (Bit 0)                                        */
#define UART_CTL0_SBKCMD_Msk             (0x1UL)                   /*!< SBKCMD (Bitfield-Mask: 0x01)                          */
/* =========================================================  CTL1  ========================================================== */
#define UART_CTL1_LMEN_Pos               (14UL)                    /*!< LMEN (Bit 14)                                         */
#define UART_CTL1_LMEN_Msk               (0x4000UL)                /*!< LMEN (Bitfield-Mask: 0x01)                            */
#define UART_CTL1_STB_Pos                (12UL)                    /*!< STB (Bit 12)                                          */
#define UART_CTL1_STB_Msk                (0x3000UL)                /*!< STB (Bitfield-Mask: 0x03)                             */
#define UART_CTL1_LBDIE_Pos              (6UL)                     /*!< LBDIE (Bit 6)                                         */
#define UART_CTL1_LBDIE_Msk              (0x40UL)                  /*!< LBDIE (Bitfield-Mask: 0x01)                           */
#define UART_CTL1_LBLEN_Pos              (5UL)                     /*!< LBLEN (Bit 5)                                         */
#define UART_CTL1_LBLEN_Msk              (0x20UL)                  /*!< LBLEN (Bitfield-Mask: 0x01)                           */
#define UART_CTL1_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
#define UART_CTL1_ADDR_Msk               (0xfUL)                   /*!< ADDR (Bitfield-Mask: 0x0f)                            */
/* =========================================================  CTL2  ========================================================== */
#define UART_CTL2_DENT_Pos               (7UL)                     /*!< DENT (Bit 7)                                          */
#define UART_CTL2_DENT_Msk               (0x80UL)                  /*!< DENT (Bitfield-Mask: 0x01)                            */
#define UART_CTL2_DENR_Pos               (6UL)                     /*!< DENR (Bit 6)                                          */
#define UART_CTL2_DENR_Msk               (0x40UL)                  /*!< DENR (Bitfield-Mask: 0x01)                            */
#define UART_CTL2_HDEN_Pos               (3UL)                     /*!< HDEN (Bit 3)                                          */
#define UART_CTL2_HDEN_Msk               (0x8UL)                   /*!< HDEN (Bitfield-Mask: 0x01)                            */
#define UART_CTL2_IRLP_Pos               (2UL)                     /*!< IRLP (Bit 2)                                          */
#define UART_CTL2_IRLP_Msk               (0x4UL)                   /*!< IRLP (Bitfield-Mask: 0x01)                            */
#define UART_CTL2_IREN_Pos               (1UL)                     /*!< IREN (Bit 1)                                          */
#define UART_CTL2_IREN_Msk               (0x2UL)                   /*!< IREN (Bitfield-Mask: 0x01)                            */
#define UART_CTL2_ERRIE_Pos              (0UL)                     /*!< ERRIE (Bit 0)                                         */
#define UART_CTL2_ERRIE_Msk              (0x1UL)                   /*!< ERRIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  GP  =========================================================== */
#define UART_GP_PSC_Pos                  (0UL)                     /*!< PSC (Bit 0)                                           */
#define UART_GP_PSC_Msk                  (0xffUL)                  /*!< PSC (Bitfield-Mask: 0xff)                             */


/* =========================================================================================================================== */
/* ================                                       USBFS_GLOBAL                                        ================ */
/* =========================================================================================================================== */

/* ========================================================  GOTGCS  ========================================================= */
#define USBFS_GLOBAL_GOTGCS_SRPS_Pos      (0UL)                     /*!< SRPS (Bit 0)                                          */
#define USBFS_GLOBAL_GOTGCS_SRPS_Msk      (0x1UL)                   /*!< SRPS (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GOTGCS_SRPREQ_Pos    (1UL)                     /*!< SRPREQ (Bit 1)                                        */
#define USBFS_GLOBAL_GOTGCS_SRPREQ_Msk    (0x2UL)                   /*!< SRPREQ (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGCS_HNPS_Pos      (8UL)                     /*!< HNPS (Bit 8)                                          */
#define USBFS_GLOBAL_GOTGCS_HNPS_Msk      (0x100UL)                 /*!< HNPS (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GOTGCS_HNPREQ_Pos    (9UL)                     /*!< HNPREQ (Bit 9)                                        */
#define USBFS_GLOBAL_GOTGCS_HNPREQ_Msk    (0x200UL)                 /*!< HNPREQ (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGCS_HHNPEN_Pos    (10UL)                    /*!< HHNPEN (Bit 10)                                       */
#define USBFS_GLOBAL_GOTGCS_HHNPEN_Msk    (0x400UL)                 /*!< HHNPEN (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGCS_DHNPEN_Pos    (11UL)                    /*!< DHNPEN (Bit 11)                                       */
#define USBFS_GLOBAL_GOTGCS_DHNPEN_Msk    (0x800UL)                 /*!< DHNPEN (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGCS_IDPS_Pos      (16UL)                    /*!< IDPS (Bit 16)                                         */
#define USBFS_GLOBAL_GOTGCS_IDPS_Msk      (0x10000UL)               /*!< IDPS (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GOTGCS_DI_Pos        (17UL)                    /*!< DI (Bit 17)                                           */
#define USBFS_GLOBAL_GOTGCS_DI_Msk        (0x20000UL)               /*!< DI (Bitfield-Mask: 0x01)                              */
#define USBFS_GLOBAL_GOTGCS_ASV_Pos       (18UL)                    /*!< ASV (Bit 18)                                          */
#define USBFS_GLOBAL_GOTGCS_ASV_Msk       (0x40000UL)               /*!< ASV (Bitfield-Mask: 0x01)                             */
#define USBFS_GLOBAL_GOTGCS_BSV_Pos       (19UL)                    /*!< BSV (Bit 19)                                          */
#define USBFS_GLOBAL_GOTGCS_BSV_Msk       (0x80000UL)               /*!< BSV (Bitfield-Mask: 0x01)                             */
/* =======================================================  GOTGINTF  ======================================================== */
#define USBFS_GLOBAL_GOTGINTF_SESEND_Pos  (2UL)                     /*!< SESEND (Bit 2)                                        */
#define USBFS_GLOBAL_GOTGINTF_SESEND_Msk  (0x4UL)                   /*!< SESEND (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGINTF_SRPEND_Pos  (8UL)                     /*!< SRPEND (Bit 8)                                        */
#define USBFS_GLOBAL_GOTGINTF_SRPEND_Msk  (0x100UL)                 /*!< SRPEND (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGINTF_HNPEND_Pos  (9UL)                     /*!< HNPEND (Bit 9)                                        */
#define USBFS_GLOBAL_GOTGINTF_HNPEND_Msk  (0x200UL)                 /*!< HNPEND (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGINTF_HNPDET_Pos  (17UL)                    /*!< HNPDET (Bit 17)                                       */
#define USBFS_GLOBAL_GOTGINTF_HNPDET_Msk  (0x20000UL)               /*!< HNPDET (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GOTGINTF_ADTO_Pos    (18UL)                    /*!< ADTO (Bit 18)                                         */
#define USBFS_GLOBAL_GOTGINTF_ADTO_Msk    (0x40000UL)               /*!< ADTO (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GOTGINTF_DF_Pos      (19UL)                    /*!< DF (Bit 19)                                           */
#define USBFS_GLOBAL_GOTGINTF_DF_Msk      (0x80000UL)               /*!< DF (Bitfield-Mask: 0x01)                              */
/* ========================================================  GAHBCS  ========================================================= */
#define USBFS_GLOBAL_GAHBCS_GINTEN_Pos    (0UL)                     /*!< GINTEN (Bit 0)                                        */
#define USBFS_GLOBAL_GAHBCS_GINTEN_Msk    (0x1UL)                   /*!< GINTEN (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GAHBCS_TXFTH_Pos     (7UL)                     /*!< TXFTH (Bit 7)                                         */
#define USBFS_GLOBAL_GAHBCS_TXFTH_Msk     (0x80UL)                  /*!< TXFTH (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GAHBCS_PTXFTH_Pos    (8UL)                     /*!< PTXFTH (Bit 8)                                        */
#define USBFS_GLOBAL_GAHBCS_PTXFTH_Msk    (0x100UL)                 /*!< PTXFTH (Bitfield-Mask: 0x01)                          */
/* ========================================================  GUSBCS  ========================================================= */
#define USBFS_GLOBAL_GUSBCS_TOC_Pos       (0UL)                     /*!< TOC (Bit 0)                                           */
#define USBFS_GLOBAL_GUSBCS_TOC_Msk       (0x7UL)                   /*!< TOC (Bitfield-Mask: 0x07)                             */
#define USBFS_GLOBAL_GUSBCS_SRPCEN_Pos    (8UL)                     /*!< SRPCEN (Bit 8)                                        */
#define USBFS_GLOBAL_GUSBCS_SRPCEN_Msk    (0x100UL)                 /*!< SRPCEN (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GUSBCS_HNPCEN_Pos    (9UL)                     /*!< HNPCEN (Bit 9)                                        */
#define USBFS_GLOBAL_GUSBCS_HNPCEN_Msk    (0x200UL)                 /*!< HNPCEN (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GUSBCS_UTT_Pos       (10UL)                    /*!< UTT (Bit 10)                                          */
#define USBFS_GLOBAL_GUSBCS_UTT_Msk       (0x3c00UL)                /*!< UTT (Bitfield-Mask: 0x0f)                             */
#define USBFS_GLOBAL_GUSBCS_FHM_Pos       (29UL)                    /*!< FHM (Bit 29)                                          */
#define USBFS_GLOBAL_GUSBCS_FHM_Msk       (0x20000000UL)            /*!< FHM (Bitfield-Mask: 0x01)                             */
#define USBFS_GLOBAL_GUSBCS_FDM_Pos       (30UL)                    /*!< FDM (Bit 30)                                          */
#define USBFS_GLOBAL_GUSBCS_FDM_Msk       (0x40000000UL)            /*!< FDM (Bitfield-Mask: 0x01)                             */
/* ========================================================  GRSTCTL  ======================================================== */
#define USBFS_GLOBAL_GRSTCTL_CSRST_Pos    (0UL)                     /*!< CSRST (Bit 0)                                         */
#define USBFS_GLOBAL_GRSTCTL_CSRST_Msk    (0x1UL)                   /*!< CSRST (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GRSTCTL_HCSRST_Pos   (1UL)                     /*!< HCSRST (Bit 1)                                        */
#define USBFS_GLOBAL_GRSTCTL_HCSRST_Msk   (0x2UL)                   /*!< HCSRST (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GRSTCTL_HFCRST_Pos   (2UL)                     /*!< HFCRST (Bit 2)                                        */
#define USBFS_GLOBAL_GRSTCTL_HFCRST_Msk   (0x4UL)                   /*!< HFCRST (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GRSTCTL_RXFF_Pos     (4UL)                     /*!< RXFF (Bit 4)                                          */
#define USBFS_GLOBAL_GRSTCTL_RXFF_Msk     (0x10UL)                  /*!< RXFF (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GRSTCTL_TXFF_Pos     (5UL)                     /*!< TXFF (Bit 5)                                          */
#define USBFS_GLOBAL_GRSTCTL_TXFF_Msk     (0x20UL)                  /*!< TXFF (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GRSTCTL_TXFNUM_Pos   (6UL)                     /*!< TXFNUM (Bit 6)                                        */
#define USBFS_GLOBAL_GRSTCTL_TXFNUM_Msk   (0x7c0UL)                 /*!< TXFNUM (Bitfield-Mask: 0x1f)                          */
/* =========================================================  GINTF  ========================================================= */
#define USBFS_GLOBAL_GINTF_COPM_Pos       (0UL)                     /*!< COPM (Bit 0)                                          */
#define USBFS_GLOBAL_GINTF_COPM_Msk       (0x1UL)                   /*!< COPM (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTF_MFIF_Pos       (1UL)                     /*!< MFIF (Bit 1)                                          */
#define USBFS_GLOBAL_GINTF_MFIF_Msk       (0x2UL)                   /*!< MFIF (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTF_OTGIF_Pos      (2UL)                     /*!< OTGIF (Bit 2)                                         */
#define USBFS_GLOBAL_GINTF_OTGIF_Msk      (0x4UL)                   /*!< OTGIF (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTF_SOF_Pos        (3UL)                     /*!< SOF (Bit 3)                                           */
#define USBFS_GLOBAL_GINTF_SOF_Msk        (0x8UL)                   /*!< SOF (Bitfield-Mask: 0x01)                             */
#define USBFS_GLOBAL_GINTF_RXFNEIF_Pos    (4UL)                     /*!< RXFNEIF (Bit 4)                                       */
#define USBFS_GLOBAL_GINTF_RXFNEIF_Msk    (0x10UL)                  /*!< RXFNEIF (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTF_NPTXFEIF_Pos   (5UL)                     /*!< NPTXFEIF (Bit 5)                                      */
#define USBFS_GLOBAL_GINTF_NPTXFEIF_Msk   (0x20UL)                  /*!< NPTXFEIF (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GINTF_GNPINAK_Pos    (6UL)                     /*!< GNPINAK (Bit 6)                                       */
#define USBFS_GLOBAL_GINTF_GNPINAK_Msk    (0x40UL)                  /*!< GNPINAK (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTF_GONAK_Pos      (7UL)                     /*!< GONAK (Bit 7)                                         */
#define USBFS_GLOBAL_GINTF_GONAK_Msk      (0x80UL)                  /*!< GONAK (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTF_ESP_Pos        (10UL)                    /*!< ESP (Bit 10)                                          */
#define USBFS_GLOBAL_GINTF_ESP_Msk        (0x400UL)                 /*!< ESP (Bitfield-Mask: 0x01)                             */
#define USBFS_GLOBAL_GINTF_SP_Pos         (11UL)                    /*!< SP (Bit 11)                                           */
#define USBFS_GLOBAL_GINTF_SP_Msk         (0x800UL)                 /*!< SP (Bitfield-Mask: 0x01)                              */
#define USBFS_GLOBAL_GINTF_RST_Pos        (12UL)                    /*!< RST (Bit 12)                                          */
#define USBFS_GLOBAL_GINTF_RST_Msk        (0x1000UL)                /*!< RST (Bitfield-Mask: 0x01)                             */
#define USBFS_GLOBAL_GINTF_ENUMF_Pos      (13UL)                    /*!< ENUMF (Bit 13)                                        */
#define USBFS_GLOBAL_GINTF_ENUMF_Msk      (0x2000UL)                /*!< ENUMF (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTF_ISOOPDIF_Pos   (14UL)                    /*!< ISOOPDIF (Bit 14)                                     */
#define USBFS_GLOBAL_GINTF_ISOOPDIF_Msk   (0x4000UL)                /*!< ISOOPDIF (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GINTF_EOPFIF_Pos     (15UL)                    /*!< EOPFIF (Bit 15)                                       */
#define USBFS_GLOBAL_GINTF_EOPFIF_Msk     (0x8000UL)                /*!< EOPFIF (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GINTF_IEPIF_Pos      (18UL)                    /*!< IEPIF (Bit 18)                                        */
#define USBFS_GLOBAL_GINTF_IEPIF_Msk      (0x40000UL)               /*!< IEPIF (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTF_OEPIF_Pos      (19UL)                    /*!< OEPIF (Bit 19)                                        */
#define USBFS_GLOBAL_GINTF_OEPIF_Msk      (0x80000UL)               /*!< OEPIF (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTF_ISOINCIF_Pos   (20UL)                    /*!< ISOINCIF (Bit 20)                                     */
#define USBFS_GLOBAL_GINTF_ISOINCIF_Msk   (0x100000UL)              /*!< ISOINCIF (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GINTF_PXNCIF_ISOONCIF_Pos (21UL)               /*!< PXNCIF_ISOONCIF (Bit 21)                              */
#define USBFS_GLOBAL_GINTF_PXNCIF_ISOONCIF_Msk (0x200000UL)         /*!< PXNCIF_ISOONCIF (Bitfield-Mask: 0x01)                 */
#define USBFS_GLOBAL_GINTF_HPIF_Pos       (24UL)                    /*!< HPIF (Bit 24)                                         */
#define USBFS_GLOBAL_GINTF_HPIF_Msk       (0x1000000UL)             /*!< HPIF (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTF_HCIF_Pos       (25UL)                    /*!< HCIF (Bit 25)                                         */
#define USBFS_GLOBAL_GINTF_HCIF_Msk       (0x2000000UL)             /*!< HCIF (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTF_PTXFEIF_Pos    (26UL)                    /*!< PTXFEIF (Bit 26)                                      */
#define USBFS_GLOBAL_GINTF_PTXFEIF_Msk    (0x4000000UL)             /*!< PTXFEIF (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTF_IDPSC_Pos      (28UL)                    /*!< IDPSC (Bit 28)                                        */
#define USBFS_GLOBAL_GINTF_IDPSC_Msk      (0x10000000UL)            /*!< IDPSC (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTF_DISCIF_Pos     (29UL)                    /*!< DISCIF (Bit 29)                                       */
#define USBFS_GLOBAL_GINTF_DISCIF_Msk     (0x20000000UL)            /*!< DISCIF (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GINTF_SESIF_Pos      (30UL)                    /*!< SESIF (Bit 30)                                        */
#define USBFS_GLOBAL_GINTF_SESIF_Msk      (0x40000000UL)            /*!< SESIF (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTF_WKUPIF_Pos     (31UL)                    /*!< WKUPIF (Bit 31)                                       */
#define USBFS_GLOBAL_GINTF_WKUPIF_Msk     (0x80000000UL)            /*!< WKUPIF (Bitfield-Mask: 0x01)                          */
/* ========================================================  GINTEN  ========================================================= */
#define USBFS_GLOBAL_GINTEN_MFIE_Pos      (1UL)                     /*!< MFIE (Bit 1)                                          */
#define USBFS_GLOBAL_GINTEN_MFIE_Msk      (0x2UL)                   /*!< MFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTEN_OTGIE_Pos     (2UL)                     /*!< OTGIE (Bit 2)                                         */
#define USBFS_GLOBAL_GINTEN_OTGIE_Msk     (0x4UL)                   /*!< OTGIE (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTEN_SOFIE_Pos     (3UL)                     /*!< SOFIE (Bit 3)                                         */
#define USBFS_GLOBAL_GINTEN_SOFIE_Msk     (0x8UL)                   /*!< SOFIE (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTEN_RXFNEIE_Pos   (4UL)                     /*!< RXFNEIE (Bit 4)                                       */
#define USBFS_GLOBAL_GINTEN_RXFNEIE_Msk   (0x10UL)                  /*!< RXFNEIE (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTEN_NPTXFEIE_Pos  (5UL)                     /*!< NPTXFEIE (Bit 5)                                      */
#define USBFS_GLOBAL_GINTEN_NPTXFEIE_Msk  (0x20UL)                  /*!< NPTXFEIE (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GINTEN_GNPINAKIE_Pos (6UL)                     /*!< GNPINAKIE (Bit 6)                                     */
#define USBFS_GLOBAL_GINTEN_GNPINAKIE_Msk (0x40UL)                  /*!< GNPINAKIE (Bitfield-Mask: 0x01)                       */
#define USBFS_GLOBAL_GINTEN_GONAKIE_Pos   (7UL)                     /*!< GONAKIE (Bit 7)                                       */
#define USBFS_GLOBAL_GINTEN_GONAKIE_Msk   (0x80UL)                  /*!< GONAKIE (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTEN_ESPIE_Pos     (10UL)                    /*!< ESPIE (Bit 10)                                        */
#define USBFS_GLOBAL_GINTEN_ESPIE_Msk     (0x400UL)                 /*!< ESPIE (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTEN_SPIE_Pos      (11UL)                    /*!< SPIE (Bit 11)                                         */
#define USBFS_GLOBAL_GINTEN_SPIE_Msk      (0x800UL)                 /*!< SPIE (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTEN_RSTIE_Pos     (12UL)                    /*!< RSTIE (Bit 12)                                        */
#define USBFS_GLOBAL_GINTEN_RSTIE_Msk     (0x1000UL)                /*!< RSTIE (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTEN_ENUMFIE_Pos   (13UL)                    /*!< ENUMFIE (Bit 13)                                      */
#define USBFS_GLOBAL_GINTEN_ENUMFIE_Msk   (0x2000UL)                /*!< ENUMFIE (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTEN_ISOOPDIE_Pos  (14UL)                    /*!< ISOOPDIE (Bit 14)                                     */
#define USBFS_GLOBAL_GINTEN_ISOOPDIE_Msk  (0x4000UL)                /*!< ISOOPDIE (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GINTEN_EOPFIE_Pos    (15UL)                    /*!< EOPFIE (Bit 15)                                       */
#define USBFS_GLOBAL_GINTEN_EOPFIE_Msk    (0x8000UL)                /*!< EOPFIE (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GINTEN_IEPIE_Pos     (18UL)                    /*!< IEPIE (Bit 18)                                        */
#define USBFS_GLOBAL_GINTEN_IEPIE_Msk     (0x40000UL)               /*!< IEPIE (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTEN_OEPIE_Pos     (19UL)                    /*!< OEPIE (Bit 19)                                        */
#define USBFS_GLOBAL_GINTEN_OEPIE_Msk     (0x80000UL)               /*!< OEPIE (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTEN_ISOINCIE_Pos  (20UL)                    /*!< ISOINCIE (Bit 20)                                     */
#define USBFS_GLOBAL_GINTEN_ISOINCIE_Msk  (0x100000UL)              /*!< ISOINCIE (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GINTEN_PXNCIE_ISOONCIE_Pos (21UL)              /*!< PXNCIE_ISOONCIE (Bit 21)                              */
#define USBFS_GLOBAL_GINTEN_PXNCIE_ISOONCIE_Msk (0x200000UL)        /*!< PXNCIE_ISOONCIE (Bitfield-Mask: 0x01)                 */
#define USBFS_GLOBAL_GINTEN_HPIE_Pos      (24UL)                    /*!< HPIE (Bit 24)                                         */
#define USBFS_GLOBAL_GINTEN_HPIE_Msk      (0x1000000UL)             /*!< HPIE (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTEN_HCIE_Pos      (25UL)                    /*!< HCIE (Bit 25)                                         */
#define USBFS_GLOBAL_GINTEN_HCIE_Msk      (0x2000000UL)             /*!< HCIE (Bitfield-Mask: 0x01)                            */
#define USBFS_GLOBAL_GINTEN_PTXFEIE_Pos   (26UL)                    /*!< PTXFEIE (Bit 26)                                      */
#define USBFS_GLOBAL_GINTEN_PTXFEIE_Msk   (0x4000000UL)             /*!< PTXFEIE (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTEN_IDPSCIE_Pos   (28UL)                    /*!< IDPSCIE (Bit 28)                                      */
#define USBFS_GLOBAL_GINTEN_IDPSCIE_Msk   (0x10000000UL)            /*!< IDPSCIE (Bitfield-Mask: 0x01)                         */
#define USBFS_GLOBAL_GINTEN_DISCIE_Pos    (29UL)                    /*!< DISCIE (Bit 29)                                       */
#define USBFS_GLOBAL_GINTEN_DISCIE_Msk    (0x20000000UL)            /*!< DISCIE (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GINTEN_SESIE_Pos     (30UL)                    /*!< SESIE (Bit 30)                                        */
#define USBFS_GLOBAL_GINTEN_SESIE_Msk     (0x40000000UL)            /*!< SESIE (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GINTEN_WKUPIE_Pos    (31UL)                    /*!< WKUPIE (Bit 31)                                       */
#define USBFS_GLOBAL_GINTEN_WKUPIE_Msk    (0x80000000UL)            /*!< WKUPIE (Bitfield-Mask: 0x01)                          */
/* ====================================================  GRSTATR_Device  ===================================================== */
#define USBFS_GLOBAL_GRSTATR_Device_EPNUM_Pos (0UL)                 /*!< EPNUM (Bit 0)                                         */
#define USBFS_GLOBAL_GRSTATR_Device_EPNUM_Msk (0xfUL)               /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_GLOBAL_GRSTATR_Device_BCOUNT_Pos (4UL)                /*!< BCOUNT (Bit 4)                                        */
#define USBFS_GLOBAL_GRSTATR_Device_BCOUNT_Msk (0x7ff0UL)           /*!< BCOUNT (Bitfield-Mask: 0x7ff)                         */
#define USBFS_GLOBAL_GRSTATR_Device_DPID_Pos (15UL)                 /*!< DPID (Bit 15)                                         */
#define USBFS_GLOBAL_GRSTATR_Device_DPID_Msk (0x18000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
#define USBFS_GLOBAL_GRSTATR_Device_RPCKST_Pos (17UL)               /*!< RPCKST (Bit 17)                                       */
#define USBFS_GLOBAL_GRSTATR_Device_RPCKST_Msk (0x1e0000UL)         /*!< RPCKST (Bitfield-Mask: 0x0f)                          */
/* =====================================================  GRSTATR_Host  ====================================================== */
#define USBFS_GLOBAL_GRSTATR_Host_CNUM_Pos (0UL)                    /*!< CNUM (Bit 0)                                          */
#define USBFS_GLOBAL_GRSTATR_Host_CNUM_Msk (0xfUL)                  /*!< CNUM (Bitfield-Mask: 0x0f)                            */
#define USBFS_GLOBAL_GRSTATR_Host_BCOUNT_Pos (4UL)                  /*!< BCOUNT (Bit 4)                                        */
#define USBFS_GLOBAL_GRSTATR_Host_BCOUNT_Msk (0x7ff0UL)             /*!< BCOUNT (Bitfield-Mask: 0x7ff)                         */
#define USBFS_GLOBAL_GRSTATR_Host_DPID_Pos (15UL)                   /*!< DPID (Bit 15)                                         */
#define USBFS_GLOBAL_GRSTATR_Host_DPID_Msk (0x18000UL)              /*!< DPID (Bitfield-Mask: 0x03)                            */
#define USBFS_GLOBAL_GRSTATR_Host_RPCKST_Pos (17UL)                 /*!< RPCKST (Bit 17)                                       */
#define USBFS_GLOBAL_GRSTATR_Host_RPCKST_Msk (0x1e0000UL)           /*!< RPCKST (Bitfield-Mask: 0x0f)                          */
/* ====================================================  GRSTATP_Device  ===================================================== */
#define USBFS_GLOBAL_GRSTATP_Device_EPNUM_Pos (0UL)                 /*!< EPNUM (Bit 0)                                         */
#define USBFS_GLOBAL_GRSTATP_Device_EPNUM_Msk (0xfUL)               /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_GLOBAL_GRSTATP_Device_BCOUNT_Pos (4UL)                /*!< BCOUNT (Bit 4)                                        */
#define USBFS_GLOBAL_GRSTATP_Device_BCOUNT_Msk (0x7ff0UL)           /*!< BCOUNT (Bitfield-Mask: 0x7ff)                         */
#define USBFS_GLOBAL_GRSTATP_Device_DPID_Pos (15UL)                 /*!< DPID (Bit 15)                                         */
#define USBFS_GLOBAL_GRSTATP_Device_DPID_Msk (0x18000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
#define USBFS_GLOBAL_GRSTATP_Device_RPCKST_Pos (17UL)               /*!< RPCKST (Bit 17)                                       */
#define USBFS_GLOBAL_GRSTATP_Device_RPCKST_Msk (0x1e0000UL)         /*!< RPCKST (Bitfield-Mask: 0x0f)                          */
/* =====================================================  GRSTATP_Host  ====================================================== */
#define USBFS_GLOBAL_GRSTATP_Host_CNUM_Pos (0UL)                    /*!< CNUM (Bit 0)                                          */
#define USBFS_GLOBAL_GRSTATP_Host_CNUM_Msk (0xfUL)                  /*!< CNUM (Bitfield-Mask: 0x0f)                            */
#define USBFS_GLOBAL_GRSTATP_Host_BCOUNT_Pos (4UL)                  /*!< BCOUNT (Bit 4)                                        */
#define USBFS_GLOBAL_GRSTATP_Host_BCOUNT_Msk (0x7ff0UL)             /*!< BCOUNT (Bitfield-Mask: 0x7ff)                         */
#define USBFS_GLOBAL_GRSTATP_Host_DPID_Pos (15UL)                   /*!< DPID (Bit 15)                                         */
#define USBFS_GLOBAL_GRSTATP_Host_DPID_Msk (0x18000UL)              /*!< DPID (Bitfield-Mask: 0x03)                            */
#define USBFS_GLOBAL_GRSTATP_Host_RPCKST_Pos (17UL)                 /*!< RPCKST (Bit 17)                                       */
#define USBFS_GLOBAL_GRSTATP_Host_RPCKST_Msk (0x1e0000UL)           /*!< RPCKST (Bitfield-Mask: 0x0f)                          */
/* ========================================================  GRFLEN  ========================================================= */
#define USBFS_GLOBAL_GRFLEN_RXFD_Pos      (0UL)                     /*!< RXFD (Bit 0)                                          */
#define USBFS_GLOBAL_GRFLEN_RXFD_Msk      (0xffffUL)                /*!< RXFD (Bitfield-Mask: 0xffff)                          */
/* =======================================================  HNPTFLEN  ======================================================== */
#define USBFS_GLOBAL_HNPTFLEN_HNPTXRSAR_Pos (0UL)                   /*!< HNPTXRSAR (Bit 0)                                     */
#define USBFS_GLOBAL_HNPTFLEN_HNPTXRSAR_Msk (0xffffUL)              /*!< HNPTXRSAR (Bitfield-Mask: 0xffff)                     */
#define USBFS_GLOBAL_HNPTFLEN_HNPTXFD_Pos (16UL)                    /*!< HNPTXFD (Bit 16)                                      */
#define USBFS_GLOBAL_HNPTFLEN_HNPTXFD_Msk (0xffff0000UL)            /*!< HNPTXFD (Bitfield-Mask: 0xffff)                       */
/* ======================================================  DIEP0TFLEN  ======================================================= */
#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXFD_Pos (16UL)                 /*!< IEP0TXFD (Bit 16)                                     */
#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXFD_Msk (0xffff0000UL)         /*!< IEP0TXFD (Bitfield-Mask: 0xffff)                      */
#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXRSAR_Pos (0UL)                /*!< IEP0TXRSAR (Bit 0)                                    */
#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXRSAR_Msk (0xffffUL)           /*!< IEP0TXRSAR (Bitfield-Mask: 0xffff)                    */
/* ======================================================  HNPTFQSTAT  ======================================================= */
#define USBFS_GLOBAL_HNPTFQSTAT_NPTXFS_Pos (0UL)                    /*!< NPTXFS (Bit 0)                                        */
#define USBFS_GLOBAL_HNPTFQSTAT_NPTXFS_Msk (0xffffUL)               /*!< NPTXFS (Bitfield-Mask: 0xffff)                        */
#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQS_Pos (16UL)                  /*!< NPTXRQS (Bit 16)                                      */
#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQS_Msk (0xff0000UL)            /*!< NPTXRQS (Bitfield-Mask: 0xff)                         */
#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQTOP_Pos (24UL)                /*!< NPTXRQTOP (Bit 24)                                    */
#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQTOP_Msk (0x7f000000UL)        /*!< NPTXRQTOP (Bitfield-Mask: 0x7f)                       */
/* =========================================================  GCCFG  ========================================================= */
#define USBFS_GLOBAL_GCCFG_PWRON_Pos      (16UL)                    /*!< PWRON (Bit 16)                                        */
#define USBFS_GLOBAL_GCCFG_PWRON_Msk      (0x10000UL)               /*!< PWRON (Bitfield-Mask: 0x01)                           */
#define USBFS_GLOBAL_GCCFG_VBUSACEN_Pos   (18UL)                    /*!< VBUSACEN (Bit 18)                                     */
#define USBFS_GLOBAL_GCCFG_VBUSACEN_Msk   (0x40000UL)               /*!< VBUSACEN (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GCCFG_VBUSBCEN_Pos   (19UL)                    /*!< VBUSBCEN (Bit 19)                                     */
#define USBFS_GLOBAL_GCCFG_VBUSBCEN_Msk   (0x80000UL)               /*!< VBUSBCEN (Bitfield-Mask: 0x01)                        */
#define USBFS_GLOBAL_GCCFG_SOFOEN_Pos     (20UL)                    /*!< SOFOEN (Bit 20)                                       */
#define USBFS_GLOBAL_GCCFG_SOFOEN_Msk     (0x100000UL)              /*!< SOFOEN (Bitfield-Mask: 0x01)                          */
#define USBFS_GLOBAL_GCCFG_VBUSIG_Pos     (21UL)                    /*!< VBUSIG (Bit 21)                                       */
#define USBFS_GLOBAL_GCCFG_VBUSIG_Msk     (0x200000UL)              /*!< VBUSIG (Bitfield-Mask: 0x01)                          */
/* ==========================================================  CID  ========================================================== */
#define USBFS_GLOBAL_CID_CID_Pos          (0UL)                     /*!< CID (Bit 0)                                           */
#define USBFS_GLOBAL_CID_CID_Msk          (0xffffffffUL)            /*!< CID (Bitfield-Mask: 0xffffffff)                       */
/* ========================================================  HPTFLEN  ======================================================== */
#define USBFS_GLOBAL_HPTFLEN_HPTXFSAR_Pos (0UL)                     /*!< HPTXFSAR (Bit 0)                                      */
#define USBFS_GLOBAL_HPTFLEN_HPTXFSAR_Msk (0xffffUL)                /*!< HPTXFSAR (Bitfield-Mask: 0xffff)                      */
#define USBFS_GLOBAL_HPTFLEN_HPTXFD_Pos   (16UL)                    /*!< HPTXFD (Bit 16)                                       */
#define USBFS_GLOBAL_HPTFLEN_HPTXFD_Msk   (0xffff0000UL)            /*!< HPTXFD (Bitfield-Mask: 0xffff)                        */
/* ======================================================  DIEP1TFLEN  ======================================================= */
#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXRSAR_Pos (0UL)                 /*!< IEPTXRSAR (Bit 0)                                     */
#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXRSAR_Msk (0xffffUL)            /*!< IEPTXRSAR (Bitfield-Mask: 0xffff)                     */
#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXFD_Pos (16UL)                  /*!< IEPTXFD (Bit 16)                                      */
#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXFD_Msk (0xffff0000UL)          /*!< IEPTXFD (Bitfield-Mask: 0xffff)                       */
/* ======================================================  DIEP2TFLEN  ======================================================= */
#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXRSAR_Pos (0UL)                 /*!< IEPTXRSAR (Bit 0)                                     */
#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXRSAR_Msk (0xffffUL)            /*!< IEPTXRSAR (Bitfield-Mask: 0xffff)                     */
#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXFD_Pos (16UL)                  /*!< IEPTXFD (Bit 16)                                      */
#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXFD_Msk (0xffff0000UL)          /*!< IEPTXFD (Bitfield-Mask: 0xffff)                       */
/* ======================================================  DIEP3TFLEN  ======================================================= */
#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXRSAR_Pos (0UL)                 /*!< IEPTXRSAR (Bit 0)                                     */
#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXRSAR_Msk (0xffffUL)            /*!< IEPTXRSAR (Bitfield-Mask: 0xffff)                     */
#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXFD_Pos (16UL)                  /*!< IEPTXFD (Bit 16)                                      */
#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXFD_Msk (0xffff0000UL)          /*!< IEPTXFD (Bitfield-Mask: 0xffff)                       */


/* =========================================================================================================================== */
/* ================                                        USBFS_HOST                                         ================ */
/* =========================================================================================================================== */

/* =========================================================  HCTL  ========================================================== */
#define USBFS_HOST_HCTL_CLKSEL_Pos        (0UL)                     /*!< CLKSEL (Bit 0)                                        */
#define USBFS_HOST_HCTL_CLKSEL_Msk        (0x3UL)                   /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
/* ==========================================================  HFT  ========================================================== */
#define USBFS_HOST_HFT_FRI_Pos            (0UL)                     /*!< FRI (Bit 0)                                           */
#define USBFS_HOST_HFT_FRI_Msk            (0xffffUL)                /*!< FRI (Bitfield-Mask: 0xffff)                           */
/* ========================================================  HFINFR  ========================================================= */
#define USBFS_HOST_HFINFR_FRNUM_Pos       (0UL)                     /*!< FRNUM (Bit 0)                                         */
#define USBFS_HOST_HFINFR_FRNUM_Msk       (0xffffUL)                /*!< FRNUM (Bitfield-Mask: 0xffff)                         */
#define USBFS_HOST_HFINFR_FRT_Pos         (16UL)                    /*!< FRT (Bit 16)                                          */
#define USBFS_HOST_HFINFR_FRT_Msk         (0xffff0000UL)            /*!< FRT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  HPTFQSTAT  ======================================================= */
#define USBFS_HOST_HPTFQSTAT_PTXFS_Pos    (0UL)                     /*!< PTXFS (Bit 0)                                         */
#define USBFS_HOST_HPTFQSTAT_PTXFS_Msk    (0xffffUL)                /*!< PTXFS (Bitfield-Mask: 0xffff)                         */
#define USBFS_HOST_HPTFQSTAT_PTXREQS_Pos  (16UL)                    /*!< PTXREQS (Bit 16)                                      */
#define USBFS_HOST_HPTFQSTAT_PTXREQS_Msk  (0xff0000UL)              /*!< PTXREQS (Bitfield-Mask: 0xff)                         */
#define USBFS_HOST_HPTFQSTAT_PTXREQT_Pos  (24UL)                    /*!< PTXREQT (Bit 24)                                      */
#define USBFS_HOST_HPTFQSTAT_PTXREQT_Msk  (0xff000000UL)            /*!< PTXREQT (Bitfield-Mask: 0xff)                         */
/* ========================================================  HACHINT  ======================================================== */
#define USBFS_HOST_HACHINT_HACHINT_Pos    (0UL)                     /*!< HACHINT (Bit 0)                                       */
#define USBFS_HOST_HACHINT_HACHINT_Msk    (0xffUL)                  /*!< HACHINT (Bitfield-Mask: 0xff)                         */
/* =======================================================  HACHINTEN  ======================================================= */
#define USBFS_HOST_HACHINTEN_CINTEN_Pos   (0UL)                     /*!< CINTEN (Bit 0)                                        */
#define USBFS_HOST_HACHINTEN_CINTEN_Msk   (0xffUL)                  /*!< CINTEN (Bitfield-Mask: 0xff)                          */
/* =========================================================  HPCS  ========================================================== */
#define USBFS_HOST_HPCS_PCST_Pos          (0UL)                     /*!< PCST (Bit 0)                                          */
#define USBFS_HOST_HPCS_PCST_Msk          (0x1UL)                   /*!< PCST (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HPCS_PCD_Pos           (1UL)                     /*!< PCD (Bit 1)                                           */
#define USBFS_HOST_HPCS_PCD_Msk           (0x2UL)                   /*!< PCD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HPCS_PE_Pos            (2UL)                     /*!< PE (Bit 2)                                            */
#define USBFS_HOST_HPCS_PE_Msk            (0x4UL)                   /*!< PE (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HPCS_PEDC_Pos          (3UL)                     /*!< PEDC (Bit 3)                                          */
#define USBFS_HOST_HPCS_PEDC_Msk          (0x8UL)                   /*!< PEDC (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HPCS_PREM_Pos          (6UL)                     /*!< PREM (Bit 6)                                          */
#define USBFS_HOST_HPCS_PREM_Msk          (0x40UL)                  /*!< PREM (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HPCS_PSP_Pos           (7UL)                     /*!< PSP (Bit 7)                                           */
#define USBFS_HOST_HPCS_PSP_Msk           (0x80UL)                  /*!< PSP (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HPCS_PRST_Pos          (8UL)                     /*!< PRST (Bit 8)                                          */
#define USBFS_HOST_HPCS_PRST_Msk          (0x100UL)                 /*!< PRST (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HPCS_PLST_Pos          (10UL)                    /*!< PLST (Bit 10)                                         */
#define USBFS_HOST_HPCS_PLST_Msk          (0xc00UL)                 /*!< PLST (Bitfield-Mask: 0x03)                            */
#define USBFS_HOST_HPCS_PP_Pos            (12UL)                    /*!< PP (Bit 12)                                           */
#define USBFS_HOST_HPCS_PP_Msk            (0x1000UL)                /*!< PP (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HPCS_PS_Pos            (17UL)                    /*!< PS (Bit 17)                                           */
#define USBFS_HOST_HPCS_PS_Msk            (0x60000UL)               /*!< PS (Bitfield-Mask: 0x03)                              */
/* ========================================================  HCH0CTL  ======================================================== */
#define USBFS_HOST_HCH0CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH0CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH0CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH0CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH0CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH0CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH0CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH0CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH0CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH0CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH0CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH0CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH0CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH0CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH0CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH0CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH0CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH0CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  HCH1CTL  ======================================================== */
#define USBFS_HOST_HCH1CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH1CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH1CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH1CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH1CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH1CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH1CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH1CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH1CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH1CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH1CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH1CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH1CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH1CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH1CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH1CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH1CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH1CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  HCH2CTL  ======================================================== */
#define USBFS_HOST_HCH2CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH2CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH2CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH2CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH2CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH2CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH2CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH2CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH2CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH2CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH2CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH2CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH2CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH2CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH2CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH2CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH2CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH2CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  HCH3CTL  ======================================================== */
#define USBFS_HOST_HCH3CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH3CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH3CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH3CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH3CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH3CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH3CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH3CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH3CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH3CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH3CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH3CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH3CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH3CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH3CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH3CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH3CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH3CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  HCH4CTL  ======================================================== */
#define USBFS_HOST_HCH4CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH4CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH4CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH4CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH4CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH4CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH4CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH4CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH4CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH4CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH4CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH4CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH4CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH4CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH4CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH4CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH4CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH4CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  HCH5CTL  ======================================================== */
#define USBFS_HOST_HCH5CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH5CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH5CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH5CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH5CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH5CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH5CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH5CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH5CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH5CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH5CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH5CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH5CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH5CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH5CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH5CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH5CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH5CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  HCH6CTL  ======================================================== */
#define USBFS_HOST_HCH6CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH6CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH6CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH6CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH6CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH6CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH6CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH6CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH6CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH6CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH6CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH6CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH6CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH6CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH6CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH6CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH6CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH6CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  HCH7CTL  ======================================================== */
#define USBFS_HOST_HCH7CTL_MPL_Pos        (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_HOST_HCH7CTL_MPL_Msk        (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
#define USBFS_HOST_HCH7CTL_EPNUM_Pos      (11UL)                    /*!< EPNUM (Bit 11)                                        */
#define USBFS_HOST_HCH7CTL_EPNUM_Msk      (0x7800UL)                /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
#define USBFS_HOST_HCH7CTL_EPDIR_Pos      (15UL)                    /*!< EPDIR (Bit 15)                                        */
#define USBFS_HOST_HCH7CTL_EPDIR_Msk      (0x8000UL)                /*!< EPDIR (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH7CTL_LSD_Pos        (17UL)                    /*!< LSD (Bit 17)                                          */
#define USBFS_HOST_HCH7CTL_LSD_Msk        (0x20000UL)               /*!< LSD (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH7CTL_EPTYPE_Pos     (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_HOST_HCH7CTL_EPTYPE_Msk     (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_HOST_HCH7CTL_DAR_Pos        (22UL)                    /*!< DAR (Bit 22)                                          */
#define USBFS_HOST_HCH7CTL_DAR_Msk        (0x1fc00000UL)            /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_HOST_HCH7CTL_ODDFRM_Pos     (29UL)                    /*!< ODDFRM (Bit 29)                                       */
#define USBFS_HOST_HCH7CTL_ODDFRM_Msk     (0x20000000UL)            /*!< ODDFRM (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH7CTL_CDIS_Pos       (30UL)                    /*!< CDIS (Bit 30)                                         */
#define USBFS_HOST_HCH7CTL_CDIS_Msk       (0x40000000UL)            /*!< CDIS (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH7CTL_CEN_Pos        (31UL)                    /*!< CEN (Bit 31)                                          */
#define USBFS_HOST_HCH7CTL_CEN_Msk        (0x80000000UL)            /*!< CEN (Bitfield-Mask: 0x01)                             */
/* =======================================================  HCH0INTF  ======================================================== */
#define USBFS_HOST_HCH0INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH0INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH0INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH0INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH0INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH0INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH0INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH0INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH0INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH0INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH0INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH0INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH0INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH0INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH0INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH0INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH0INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH0INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH1INTF  ======================================================== */
#define USBFS_HOST_HCH1INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH1INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH1INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH1INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH1INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH1INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH1INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH1INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH1INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH1INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH1INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH1INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH1INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH1INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH1INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH1INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH1INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH1INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH2INTF  ======================================================== */
#define USBFS_HOST_HCH2INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH2INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH2INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH2INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH2INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH2INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH2INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH2INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH2INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH2INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH2INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH2INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH2INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH2INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH2INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH2INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH2INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH2INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH3INTF  ======================================================== */
#define USBFS_HOST_HCH3INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH3INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH3INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH3INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH3INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH3INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH3INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH3INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH3INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH3INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH3INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH3INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH3INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH3INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH3INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH3INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH3INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH3INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH4INTF  ======================================================== */
#define USBFS_HOST_HCH4INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH4INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH4INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH4INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH4INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH4INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH4INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH4INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH4INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH4INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH4INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH4INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH4INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH4INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH4INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH4INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH4INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH4INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH5INTF  ======================================================== */
#define USBFS_HOST_HCH5INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH5INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH5INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH5INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH5INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH5INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH5INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH5INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH5INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH5INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH5INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH5INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH5INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH5INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH5INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH5INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH5INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH5INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH6INTF  ======================================================== */
#define USBFS_HOST_HCH6INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH6INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH6INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH6INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH6INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH6INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH6INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH6INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH6INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH6INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH6INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH6INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH6INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH6INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH6INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH6INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH6INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH6INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH7INTF  ======================================================== */
#define USBFS_HOST_HCH7INTF_TF_Pos        (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_HOST_HCH7INTF_TF_Msk        (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH7INTF_CH_Pos        (1UL)                     /*!< CH (Bit 1)                                            */
#define USBFS_HOST_HCH7INTF_CH_Msk        (0x2UL)                   /*!< CH (Bitfield-Mask: 0x01)                              */
#define USBFS_HOST_HCH7INTF_STALL_Pos     (3UL)                     /*!< STALL (Bit 3)                                         */
#define USBFS_HOST_HCH7INTF_STALL_Msk     (0x8UL)                   /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH7INTF_NAK_Pos       (4UL)                     /*!< NAK (Bit 4)                                           */
#define USBFS_HOST_HCH7INTF_NAK_Msk       (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH7INTF_ACK_Pos       (5UL)                     /*!< ACK (Bit 5)                                           */
#define USBFS_HOST_HCH7INTF_ACK_Msk       (0x20UL)                  /*!< ACK (Bitfield-Mask: 0x01)                             */
#define USBFS_HOST_HCH7INTF_USBER_Pos     (7UL)                     /*!< USBER (Bit 7)                                         */
#define USBFS_HOST_HCH7INTF_USBER_Msk     (0x80UL)                  /*!< USBER (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH7INTF_BBER_Pos      (8UL)                     /*!< BBER (Bit 8)                                          */
#define USBFS_HOST_HCH7INTF_BBER_Msk      (0x100UL)                 /*!< BBER (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH7INTF_REQOVR_Pos    (9UL)                     /*!< REQOVR (Bit 9)                                        */
#define USBFS_HOST_HCH7INTF_REQOVR_Msk    (0x200UL)                 /*!< REQOVR (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH7INTF_DTER_Pos      (10UL)                    /*!< DTER (Bit 10)                                         */
#define USBFS_HOST_HCH7INTF_DTER_Msk      (0x400UL)                 /*!< DTER (Bitfield-Mask: 0x01)                            */
/* =======================================================  HCH0INTEN  ======================================================= */
#define USBFS_HOST_HCH0INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH0INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH0INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH0INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH0INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH0INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH0INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH0INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH0INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH0INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH0INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH0INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH0INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH0INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH0INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH0INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH0INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH0INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* =======================================================  HCH1INTEN  ======================================================= */
#define USBFS_HOST_HCH1INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH1INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH1INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH1INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH1INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH1INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH1INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH1INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH1INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH1INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH1INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH1INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH1INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH1INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH1INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH1INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH1INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH1INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* =======================================================  HCH2INTEN  ======================================================= */
#define USBFS_HOST_HCH2INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH2INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH2INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH2INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH2INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH2INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH2INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH2INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH2INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH2INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH2INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH2INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH2INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH2INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH2INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH2INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH2INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH2INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* =======================================================  HCH3INTEN  ======================================================= */
#define USBFS_HOST_HCH3INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH3INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH3INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH3INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH3INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH3INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH3INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH3INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH3INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH3INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH3INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH3INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH3INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH3INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH3INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH3INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH3INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH3INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* =======================================================  HCH4INTEN  ======================================================= */
#define USBFS_HOST_HCH4INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH4INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH4INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH4INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH4INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH4INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH4INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH4INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH4INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH4INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH4INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH4INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH4INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH4INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH4INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH4INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH4INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH4INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* =======================================================  HCH5INTEN  ======================================================= */
#define USBFS_HOST_HCH5INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH5INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH5INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH5INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH5INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH5INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH5INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH5INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH5INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH5INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH5INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH5INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH5INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH5INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH5INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH5INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH5INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH5INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* =======================================================  HCH6INTEN  ======================================================= */
#define USBFS_HOST_HCH6INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH6INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH6INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH6INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH6INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH6INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH6INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH6INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH6INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH6INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH6INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH6INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH6INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH6INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH6INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH6INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH6INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH6INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* =======================================================  HCH7INTEN  ======================================================= */
#define USBFS_HOST_HCH7INTEN_TFIE_Pos     (0UL)                     /*!< TFIE (Bit 0)                                          */
#define USBFS_HOST_HCH7INTEN_TFIE_Msk     (0x1UL)                   /*!< TFIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH7INTEN_CHIE_Pos     (1UL)                     /*!< CHIE (Bit 1)                                          */
#define USBFS_HOST_HCH7INTEN_CHIE_Msk     (0x2UL)                   /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define USBFS_HOST_HCH7INTEN_STALLIE_Pos  (3UL)                     /*!< STALLIE (Bit 3)                                       */
#define USBFS_HOST_HCH7INTEN_STALLIE_Msk  (0x8UL)                   /*!< STALLIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH7INTEN_NAKIE_Pos    (4UL)                     /*!< NAKIE (Bit 4)                                         */
#define USBFS_HOST_HCH7INTEN_NAKIE_Msk    (0x10UL)                  /*!< NAKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH7INTEN_ACKIE_Pos    (5UL)                     /*!< ACKIE (Bit 5)                                         */
#define USBFS_HOST_HCH7INTEN_ACKIE_Msk    (0x20UL)                  /*!< ACKIE (Bitfield-Mask: 0x01)                           */
#define USBFS_HOST_HCH7INTEN_USBERIE_Pos  (7UL)                     /*!< USBERIE (Bit 7)                                       */
#define USBFS_HOST_HCH7INTEN_USBERIE_Msk  (0x80UL)                  /*!< USBERIE (Bitfield-Mask: 0x01)                         */
#define USBFS_HOST_HCH7INTEN_BBERIE_Pos   (8UL)                     /*!< BBERIE (Bit 8)                                        */
#define USBFS_HOST_HCH7INTEN_BBERIE_Msk   (0x100UL)                 /*!< BBERIE (Bitfield-Mask: 0x01)                          */
#define USBFS_HOST_HCH7INTEN_REQOVRIE_Pos (9UL)                     /*!< REQOVRIE (Bit 9)                                      */
#define USBFS_HOST_HCH7INTEN_REQOVRIE_Msk (0x200UL)                 /*!< REQOVRIE (Bitfield-Mask: 0x01)                        */
#define USBFS_HOST_HCH7INTEN_DTERIE_Pos   (10UL)                    /*!< DTERIE (Bit 10)                                       */
#define USBFS_HOST_HCH7INTEN_DTERIE_Msk   (0x400UL)                 /*!< DTERIE (Bitfield-Mask: 0x01)                          */
/* ========================================================  HCH0LEN  ======================================================== */
#define USBFS_HOST_HCH0LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH0LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH0LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH0LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH0LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH0LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
/* ========================================================  HCH1LEN  ======================================================== */
#define USBFS_HOST_HCH1LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH1LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH1LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH1LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH1LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH1LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
/* ========================================================  HCH2LEN  ======================================================== */
#define USBFS_HOST_HCH2LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH2LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH2LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH2LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH2LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH2LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
/* ========================================================  HCH3LEN  ======================================================== */
#define USBFS_HOST_HCH3LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH3LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH3LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH3LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH3LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH3LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
/* ========================================================  HCH4LEN  ======================================================== */
#define USBFS_HOST_HCH4LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH4LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH4LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH4LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH4LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH4LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
/* ========================================================  HCH5LEN  ======================================================== */
#define USBFS_HOST_HCH5LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH5LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH5LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH5LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH5LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH5LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
/* ========================================================  HCH6LEN  ======================================================== */
#define USBFS_HOST_HCH6LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH6LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH6LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH6LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH6LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH6LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */
/* ========================================================  HCH7LEN  ======================================================== */
#define USBFS_HOST_HCH7LEN_TLEN_Pos       (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_HOST_HCH7LEN_TLEN_Msk       (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
#define USBFS_HOST_HCH7LEN_PCNT_Pos       (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_HOST_HCH7LEN_PCNT_Msk       (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_HOST_HCH7LEN_DPID_Pos       (29UL)                    /*!< DPID (Bit 29)                                         */
#define USBFS_HOST_HCH7LEN_DPID_Msk       (0x60000000UL)            /*!< DPID (Bitfield-Mask: 0x03)                            */


/* =========================================================================================================================== */
/* ================                                       USBFS_DEVICE                                        ================ */
/* =========================================================================================================================== */

/* =========================================================  DCFG  ========================================================== */
#define USBFS_DEVICE_DCFG_DS_Pos          (0UL)                     /*!< DS (Bit 0)                                            */
#define USBFS_DEVICE_DCFG_DS_Msk          (0x3UL)                   /*!< DS (Bitfield-Mask: 0x03)                              */
#define USBFS_DEVICE_DCFG_NZLSOH_Pos      (2UL)                     /*!< NZLSOH (Bit 2)                                        */
#define USBFS_DEVICE_DCFG_NZLSOH_Msk      (0x4UL)                   /*!< NZLSOH (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DCFG_DAR_Pos         (4UL)                     /*!< DAR (Bit 4)                                           */
#define USBFS_DEVICE_DCFG_DAR_Msk         (0x7f0UL)                 /*!< DAR (Bitfield-Mask: 0x7f)                             */
#define USBFS_DEVICE_DCFG_EOPFT_Pos       (11UL)                    /*!< EOPFT (Bit 11)                                        */
#define USBFS_DEVICE_DCFG_EOPFT_Msk       (0x1800UL)                /*!< EOPFT (Bitfield-Mask: 0x03)                           */
/* =========================================================  DCTL  ========================================================== */
#define USBFS_DEVICE_DCTL_RWKUP_Pos       (0UL)                     /*!< RWKUP (Bit 0)                                         */
#define USBFS_DEVICE_DCTL_RWKUP_Msk       (0x1UL)                   /*!< RWKUP (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DCTL_SD_Pos          (1UL)                     /*!< SD (Bit 1)                                            */
#define USBFS_DEVICE_DCTL_SD_Msk          (0x2UL)                   /*!< SD (Bitfield-Mask: 0x01)                              */
#define USBFS_DEVICE_DCTL_GINS_Pos        (2UL)                     /*!< GINS (Bit 2)                                          */
#define USBFS_DEVICE_DCTL_GINS_Msk        (0x4UL)                   /*!< GINS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DCTL_GONS_Pos        (3UL)                     /*!< GONS (Bit 3)                                          */
#define USBFS_DEVICE_DCTL_GONS_Msk        (0x8UL)                   /*!< GONS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DCTL_SGINAK_Pos      (7UL)                     /*!< SGINAK (Bit 7)                                        */
#define USBFS_DEVICE_DCTL_SGINAK_Msk      (0x80UL)                  /*!< SGINAK (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DCTL_CGINAK_Pos      (8UL)                     /*!< CGINAK (Bit 8)                                        */
#define USBFS_DEVICE_DCTL_CGINAK_Msk      (0x100UL)                 /*!< CGINAK (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DCTL_SGONAK_Pos      (9UL)                     /*!< SGONAK (Bit 9)                                        */
#define USBFS_DEVICE_DCTL_SGONAK_Msk      (0x200UL)                 /*!< SGONAK (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DCTL_CGONAK_Pos      (10UL)                    /*!< CGONAK (Bit 10)                                       */
#define USBFS_DEVICE_DCTL_CGONAK_Msk      (0x400UL)                 /*!< CGONAK (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DCTL_POIF_Pos        (11UL)                    /*!< POIF (Bit 11)                                         */
#define USBFS_DEVICE_DCTL_POIF_Msk        (0x800UL)                 /*!< POIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  DSTAT  ========================================================= */
#define USBFS_DEVICE_DSTAT_SPST_Pos       (0UL)                     /*!< SPST (Bit 0)                                          */
#define USBFS_DEVICE_DSTAT_SPST_Msk       (0x1UL)                   /*!< SPST (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DSTAT_ES_Pos         (1UL)                     /*!< ES (Bit 1)                                            */
#define USBFS_DEVICE_DSTAT_ES_Msk         (0x6UL)                   /*!< ES (Bitfield-Mask: 0x03)                              */
#define USBFS_DEVICE_DSTAT_FNRSOF_Pos     (8UL)                     /*!< FNRSOF (Bit 8)                                        */
#define USBFS_DEVICE_DSTAT_FNRSOF_Msk     (0x3fff00UL)              /*!< FNRSOF (Bitfield-Mask: 0x3fff)                        */
/* =======================================================  DIEPINTEN  ======================================================= */
#define USBFS_DEVICE_DIEPINTEN_TFEN_Pos   (0UL)                     /*!< TFEN (Bit 0)                                          */
#define USBFS_DEVICE_DIEPINTEN_TFEN_Msk   (0x1UL)                   /*!< TFEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEPINTEN_EPDISEN_Pos (1UL)                    /*!< EPDISEN (Bit 1)                                       */
#define USBFS_DEVICE_DIEPINTEN_EPDISEN_Msk (0x2UL)                  /*!< EPDISEN (Bitfield-Mask: 0x01)                         */
#define USBFS_DEVICE_DIEPINTEN_CITOEN_Pos (3UL)                     /*!< CITOEN (Bit 3)                                        */
#define USBFS_DEVICE_DIEPINTEN_CITOEN_Msk (0x8UL)                   /*!< CITOEN (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DIEPINTEN_EPTXFUDEN_Pos (4UL)                  /*!< EPTXFUDEN (Bit 4)                                     */
#define USBFS_DEVICE_DIEPINTEN_EPTXFUDEN_Msk (0x10UL)               /*!< EPTXFUDEN (Bitfield-Mask: 0x01)                       */
#define USBFS_DEVICE_DIEPINTEN_IEPNEEN_Pos (6UL)                    /*!< IEPNEEN (Bit 6)                                       */
#define USBFS_DEVICE_DIEPINTEN_IEPNEEN_Msk (0x40UL)                 /*!< IEPNEEN (Bitfield-Mask: 0x01)                         */
/* =======================================================  DOEPINTEN  ======================================================= */
#define USBFS_DEVICE_DOEPINTEN_TFEN_Pos   (0UL)                     /*!< TFEN (Bit 0)                                          */
#define USBFS_DEVICE_DOEPINTEN_TFEN_Msk   (0x1UL)                   /*!< TFEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEPINTEN_EPDISEN_Pos (1UL)                    /*!< EPDISEN (Bit 1)                                       */
#define USBFS_DEVICE_DOEPINTEN_EPDISEN_Msk (0x2UL)                  /*!< EPDISEN (Bitfield-Mask: 0x01)                         */
#define USBFS_DEVICE_DOEPINTEN_STPFEN_Pos (3UL)                     /*!< STPFEN (Bit 3)                                        */
#define USBFS_DEVICE_DOEPINTEN_STPFEN_Msk (0x8UL)                   /*!< STPFEN (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DOEPINTEN_EPRXFOVREN_Pos (4UL)                 /*!< EPRXFOVREN (Bit 4)                                    */
#define USBFS_DEVICE_DOEPINTEN_EPRXFOVREN_Msk (0x10UL)              /*!< EPRXFOVREN (Bitfield-Mask: 0x01)                      */
#define USBFS_DEVICE_DOEPINTEN_BTBSTPEN_Pos (6UL)                   /*!< BTBSTPEN (Bit 6)                                      */
#define USBFS_DEVICE_DOEPINTEN_BTBSTPEN_Msk (0x40UL)                /*!< BTBSTPEN (Bitfield-Mask: 0x01)                        */
/* ========================================================  DAEPINT  ======================================================== */
#define USBFS_DEVICE_DAEPINT_IEPITB_Pos   (0UL)                     /*!< IEPITB (Bit 0)                                        */
#define USBFS_DEVICE_DAEPINT_IEPITB_Msk   (0xfUL)                   /*!< IEPITB (Bitfield-Mask: 0x0f)                          */
#define USBFS_DEVICE_DAEPINT_OEPITB_Pos   (16UL)                    /*!< OEPITB (Bit 16)                                       */
#define USBFS_DEVICE_DAEPINT_OEPITB_Msk   (0xf0000UL)               /*!< OEPITB (Bitfield-Mask: 0x0f)                          */
/* =======================================================  DAEPINTEN  ======================================================= */
#define USBFS_DEVICE_DAEPINTEN_IEPIE_Pos  (0UL)                     /*!< IEPIE (Bit 0)                                         */
#define USBFS_DEVICE_DAEPINTEN_IEPIE_Msk  (0xfUL)                   /*!< IEPIE (Bitfield-Mask: 0x0f)                           */
#define USBFS_DEVICE_DAEPINTEN_OEPIE_Pos  (16UL)                    /*!< OEPIE (Bit 16)                                        */
#define USBFS_DEVICE_DAEPINTEN_OEPIE_Msk  (0xf0000UL)               /*!< OEPIE (Bitfield-Mask: 0x0f)                           */
/* ========================================================  DVBUSDT  ======================================================== */
#define USBFS_DEVICE_DVBUSDT_DVBUSDT_Pos  (0UL)                     /*!< DVBUSDT (Bit 0)                                       */
#define USBFS_DEVICE_DVBUSDT_DVBUSDT_Msk  (0xffffUL)                /*!< DVBUSDT (Bitfield-Mask: 0xffff)                       */
/* ========================================================  DVBUSPT  ======================================================== */
#define USBFS_DEVICE_DVBUSPT_DVBUSPT_Pos  (0UL)                     /*!< DVBUSPT (Bit 0)                                       */
#define USBFS_DEVICE_DVBUSPT_DVBUSPT_Msk  (0xfffUL)                 /*!< DVBUSPT (Bitfield-Mask: 0xfff)                        */
/* ======================================================  DIEPFEINTEN  ====================================================== */
#define USBFS_DEVICE_DIEPFEINTEN_IEPTXFEIE_Pos (0UL)                /*!< IEPTXFEIE (Bit 0)                                     */
#define USBFS_DEVICE_DIEPFEINTEN_IEPTXFEIE_Msk (0xfUL)              /*!< IEPTXFEIE (Bitfield-Mask: 0x0f)                       */
/* =======================================================  DIEP0CTL  ======================================================== */
#define USBFS_DEVICE_DIEP0CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DIEP0CTL_MPL_Msk     (0x3UL)                   /*!< MPL (Bitfield-Mask: 0x03)                             */
#define USBFS_DEVICE_DIEP0CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DIEP0CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP0CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DIEP0CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP0CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DIEP0CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DIEP0CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DIEP0CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP0CTL_TXFNUM_Pos  (22UL)                    /*!< TXFNUM (Bit 22)                                       */
#define USBFS_DEVICE_DIEP0CTL_TXFNUM_Msk  (0x3c00000UL)             /*!< TXFNUM (Bitfield-Mask: 0x0f)                          */
#define USBFS_DEVICE_DIEP0CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DIEP0CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP0CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DIEP0CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP0CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DIEP0CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DIEP0CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DIEP0CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
/* =======================================================  DIEP1CTL  ======================================================== */
#define USBFS_DEVICE_DIEP1CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DIEP1CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP1CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DIEP1CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DIEP1CTL_SD1PID_SODDFRM_Pos (29UL)             /*!< SD1PID_SODDFRM (Bit 29)                               */
#define USBFS_DEVICE_DIEP1CTL_SD1PID_SODDFRM_Msk (0x20000000UL)     /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01)                  */
#define USBFS_DEVICE_DIEP1CTL_SD0PID_SEVENFRM_Pos (28UL)            /*!< SD0PID_SEVENFRM (Bit 28)                              */
#define USBFS_DEVICE_DIEP1CTL_SD0PID_SEVENFRM_Msk (0x10000000UL)    /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01)                 */
#define USBFS_DEVICE_DIEP1CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DIEP1CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP1CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DIEP1CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP1CTL_TXFNUM_Pos  (22UL)                    /*!< TXFNUM (Bit 22)                                       */
#define USBFS_DEVICE_DIEP1CTL_TXFNUM_Msk  (0x3c00000UL)             /*!< TXFNUM (Bitfield-Mask: 0x0f)                          */
#define USBFS_DEVICE_DIEP1CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DIEP1CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP1CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DIEP1CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DIEP1CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DIEP1CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP1CTL_EOFRM_DPID_Pos (16UL)                 /*!< EOFRM_DPID (Bit 16)                                   */
#define USBFS_DEVICE_DIEP1CTL_EOFRM_DPID_Msk (0x10000UL)            /*!< EOFRM_DPID (Bitfield-Mask: 0x01)                      */
#define USBFS_DEVICE_DIEP1CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DIEP1CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP1CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DIEP1CTL_MPL_Msk     (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
/* =======================================================  DIEP2CTL  ======================================================== */
#define USBFS_DEVICE_DIEP2CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DIEP2CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP2CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DIEP2CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DIEP2CTL_SD1PID_SODDFRM_Pos (29UL)             /*!< SD1PID_SODDFRM (Bit 29)                               */
#define USBFS_DEVICE_DIEP2CTL_SD1PID_SODDFRM_Msk (0x20000000UL)     /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01)                  */
#define USBFS_DEVICE_DIEP2CTL_SD0PID_SEVENFRM_Pos (28UL)            /*!< SD0PID_SEVENFRM (Bit 28)                              */
#define USBFS_DEVICE_DIEP2CTL_SD0PID_SEVENFRM_Msk (0x10000000UL)    /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01)                 */
#define USBFS_DEVICE_DIEP2CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DIEP2CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP2CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DIEP2CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP2CTL_TXFNUM_Pos  (22UL)                    /*!< TXFNUM (Bit 22)                                       */
#define USBFS_DEVICE_DIEP2CTL_TXFNUM_Msk  (0x3c00000UL)             /*!< TXFNUM (Bitfield-Mask: 0x0f)                          */
#define USBFS_DEVICE_DIEP2CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DIEP2CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP2CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DIEP2CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DIEP2CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DIEP2CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP2CTL_EOFRM_DPID_Pos (16UL)                 /*!< EOFRM_DPID (Bit 16)                                   */
#define USBFS_DEVICE_DIEP2CTL_EOFRM_DPID_Msk (0x10000UL)            /*!< EOFRM_DPID (Bitfield-Mask: 0x01)                      */
#define USBFS_DEVICE_DIEP2CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DIEP2CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP2CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DIEP2CTL_MPL_Msk     (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
/* =======================================================  DIEP3CTL  ======================================================== */
#define USBFS_DEVICE_DIEP3CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DIEP3CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP3CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DIEP3CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DIEP3CTL_SD1PID_SODDFRM_Pos (29UL)             /*!< SD1PID_SODDFRM (Bit 29)                               */
#define USBFS_DEVICE_DIEP3CTL_SD1PID_SODDFRM_Msk (0x20000000UL)     /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01)                  */
#define USBFS_DEVICE_DIEP3CTL_SD0PID_SEVENFRM_Pos (28UL)            /*!< SD0PID_SEVENFRM (Bit 28)                              */
#define USBFS_DEVICE_DIEP3CTL_SD0PID_SEVENFRM_Msk (0x10000000UL)    /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01)                 */
#define USBFS_DEVICE_DIEP3CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DIEP3CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP3CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DIEP3CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP3CTL_TXFNUM_Pos  (22UL)                    /*!< TXFNUM (Bit 22)                                       */
#define USBFS_DEVICE_DIEP3CTL_TXFNUM_Msk  (0x3c00000UL)             /*!< TXFNUM (Bitfield-Mask: 0x0f)                          */
#define USBFS_DEVICE_DIEP3CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DIEP3CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP3CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DIEP3CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DIEP3CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DIEP3CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP3CTL_EOFRM_DPID_Pos (16UL)                 /*!< EOFRM_DPID (Bit 16)                                   */
#define USBFS_DEVICE_DIEP3CTL_EOFRM_DPID_Msk (0x10000UL)            /*!< EOFRM_DPID (Bitfield-Mask: 0x01)                      */
#define USBFS_DEVICE_DIEP3CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DIEP3CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP3CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DIEP3CTL_MPL_Msk     (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
/* =======================================================  DOEP0CTL  ======================================================== */
#define USBFS_DEVICE_DOEP0CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DOEP0CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP0CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DOEP0CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DOEP0CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DOEP0CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP0CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DOEP0CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP0CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DOEP0CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP0CTL_SNOOP_Pos   (20UL)                    /*!< SNOOP (Bit 20)                                        */
#define USBFS_DEVICE_DOEP0CTL_SNOOP_Msk   (0x100000UL)              /*!< SNOOP (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP0CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DOEP0CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DOEP0CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DOEP0CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP0CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DOEP0CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP0CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DOEP0CTL_MPL_Msk     (0x3UL)                   /*!< MPL (Bitfield-Mask: 0x03)                             */
/* =======================================================  DOEP1CTL  ======================================================== */
#define USBFS_DEVICE_DOEP1CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DOEP1CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP1CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DOEP1CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DOEP1CTL_SD1PID_SODDFRM_Pos (29UL)             /*!< SD1PID_SODDFRM (Bit 29)                               */
#define USBFS_DEVICE_DOEP1CTL_SD1PID_SODDFRM_Msk (0x20000000UL)     /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01)                  */
#define USBFS_DEVICE_DOEP1CTL_SD0PID_SEVENFRM_Pos (28UL)            /*!< SD0PID_SEVENFRM (Bit 28)                              */
#define USBFS_DEVICE_DOEP1CTL_SD0PID_SEVENFRM_Msk (0x10000000UL)    /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01)                 */
#define USBFS_DEVICE_DOEP1CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DOEP1CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP1CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DOEP1CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP1CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DOEP1CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP1CTL_SNOOP_Pos   (20UL)                    /*!< SNOOP (Bit 20)                                        */
#define USBFS_DEVICE_DOEP1CTL_SNOOP_Msk   (0x100000UL)              /*!< SNOOP (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP1CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DOEP1CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DOEP1CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DOEP1CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP1CTL_EOFRM_DPID_Pos (16UL)                 /*!< EOFRM_DPID (Bit 16)                                   */
#define USBFS_DEVICE_DOEP1CTL_EOFRM_DPID_Msk (0x10000UL)            /*!< EOFRM_DPID (Bitfield-Mask: 0x01)                      */
#define USBFS_DEVICE_DOEP1CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DOEP1CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP1CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DOEP1CTL_MPL_Msk     (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
/* =======================================================  DOEP2CTL  ======================================================== */
#define USBFS_DEVICE_DOEP2CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DOEP2CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP2CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DOEP2CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DOEP2CTL_SD1PID_SODDFRM_Pos (29UL)             /*!< SD1PID_SODDFRM (Bit 29)                               */
#define USBFS_DEVICE_DOEP2CTL_SD1PID_SODDFRM_Msk (0x20000000UL)     /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01)                  */
#define USBFS_DEVICE_DOEP2CTL_SD0PID_SEVENFRM_Pos (28UL)            /*!< SD0PID_SEVENFRM (Bit 28)                              */
#define USBFS_DEVICE_DOEP2CTL_SD0PID_SEVENFRM_Msk (0x10000000UL)    /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01)                 */
#define USBFS_DEVICE_DOEP2CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DOEP2CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP2CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DOEP2CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP2CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DOEP2CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP2CTL_SNOOP_Pos   (20UL)                    /*!< SNOOP (Bit 20)                                        */
#define USBFS_DEVICE_DOEP2CTL_SNOOP_Msk   (0x100000UL)              /*!< SNOOP (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP2CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DOEP2CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DOEP2CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DOEP2CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP2CTL_EOFRM_DPID_Pos (16UL)                 /*!< EOFRM_DPID (Bit 16)                                   */
#define USBFS_DEVICE_DOEP2CTL_EOFRM_DPID_Msk (0x10000UL)            /*!< EOFRM_DPID (Bitfield-Mask: 0x01)                      */
#define USBFS_DEVICE_DOEP2CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DOEP2CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP2CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DOEP2CTL_MPL_Msk     (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
/* =======================================================  DOEP3CTL  ======================================================== */
#define USBFS_DEVICE_DOEP3CTL_EPEN_Pos    (31UL)                    /*!< EPEN (Bit 31)                                         */
#define USBFS_DEVICE_DOEP3CTL_EPEN_Msk    (0x80000000UL)            /*!< EPEN (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP3CTL_EPD_Pos     (30UL)                    /*!< EPD (Bit 30)                                          */
#define USBFS_DEVICE_DOEP3CTL_EPD_Msk     (0x40000000UL)            /*!< EPD (Bitfield-Mask: 0x01)                             */
#define USBFS_DEVICE_DOEP3CTL_SD1PID_SODDFRM_Pos (29UL)             /*!< SD1PID_SODDFRM (Bit 29)                               */
#define USBFS_DEVICE_DOEP3CTL_SD1PID_SODDFRM_Msk (0x20000000UL)     /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01)                  */
#define USBFS_DEVICE_DOEP3CTL_SD0PID_SEVENFRM_Pos (28UL)            /*!< SD0PID_SEVENFRM (Bit 28)                              */
#define USBFS_DEVICE_DOEP3CTL_SD0PID_SEVENFRM_Msk (0x10000000UL)    /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01)                 */
#define USBFS_DEVICE_DOEP3CTL_SNAK_Pos    (27UL)                    /*!< SNAK (Bit 27)                                         */
#define USBFS_DEVICE_DOEP3CTL_SNAK_Msk    (0x8000000UL)             /*!< SNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP3CTL_CNAK_Pos    (26UL)                    /*!< CNAK (Bit 26)                                         */
#define USBFS_DEVICE_DOEP3CTL_CNAK_Msk    (0x4000000UL)             /*!< CNAK (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP3CTL_STALL_Pos   (21UL)                    /*!< STALL (Bit 21)                                        */
#define USBFS_DEVICE_DOEP3CTL_STALL_Msk   (0x200000UL)              /*!< STALL (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP3CTL_SNOOP_Pos   (20UL)                    /*!< SNOOP (Bit 20)                                        */
#define USBFS_DEVICE_DOEP3CTL_SNOOP_Msk   (0x100000UL)              /*!< SNOOP (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP3CTL_EPTYPE_Pos  (18UL)                    /*!< EPTYPE (Bit 18)                                       */
#define USBFS_DEVICE_DOEP3CTL_EPTYPE_Msk  (0xc0000UL)               /*!< EPTYPE (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DOEP3CTL_NAKS_Pos    (17UL)                    /*!< NAKS (Bit 17)                                         */
#define USBFS_DEVICE_DOEP3CTL_NAKS_Msk    (0x20000UL)               /*!< NAKS (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP3CTL_EOFRM_DPID_Pos (16UL)                 /*!< EOFRM_DPID (Bit 16)                                   */
#define USBFS_DEVICE_DOEP3CTL_EOFRM_DPID_Msk (0x10000UL)            /*!< EOFRM_DPID (Bitfield-Mask: 0x01)                      */
#define USBFS_DEVICE_DOEP3CTL_EPACT_Pos   (15UL)                    /*!< EPACT (Bit 15)                                        */
#define USBFS_DEVICE_DOEP3CTL_EPACT_Msk   (0x8000UL)                /*!< EPACT (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP3CTL_MPL_Pos     (0UL)                     /*!< MPL (Bit 0)                                           */
#define USBFS_DEVICE_DOEP3CTL_MPL_Msk     (0x7ffUL)                 /*!< MPL (Bitfield-Mask: 0x7ff)                            */
/* =======================================================  DIEP0INTF  ======================================================= */
#define USBFS_DEVICE_DIEP0INTF_TXFE_Pos   (7UL)                     /*!< TXFE (Bit 7)                                          */
#define USBFS_DEVICE_DIEP0INTF_TXFE_Msk   (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP0INTF_IEPNE_Pos  (6UL)                     /*!< IEPNE (Bit 6)                                         */
#define USBFS_DEVICE_DIEP0INTF_IEPNE_Msk  (0x40UL)                  /*!< IEPNE (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP0INTF_EPTXFUD_Pos (4UL)                    /*!< EPTXFUD (Bit 4)                                       */
#define USBFS_DEVICE_DIEP0INTF_EPTXFUD_Msk (0x10UL)                 /*!< EPTXFUD (Bitfield-Mask: 0x01)                         */
#define USBFS_DEVICE_DIEP0INTF_CITO_Pos   (3UL)                     /*!< CITO (Bit 3)                                          */
#define USBFS_DEVICE_DIEP0INTF_CITO_Msk   (0x8UL)                   /*!< CITO (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP0INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DIEP0INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP0INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DIEP0INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DIEP1INTF  ======================================================= */
#define USBFS_DEVICE_DIEP1INTF_TXFE_Pos   (7UL)                     /*!< TXFE (Bit 7)                                          */
#define USBFS_DEVICE_DIEP1INTF_TXFE_Msk   (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP1INTF_IEPNE_Pos  (6UL)                     /*!< IEPNE (Bit 6)                                         */
#define USBFS_DEVICE_DIEP1INTF_IEPNE_Msk  (0x40UL)                  /*!< IEPNE (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP1INTF_EPTXFUD_Pos (4UL)                    /*!< EPTXFUD (Bit 4)                                       */
#define USBFS_DEVICE_DIEP1INTF_EPTXFUD_Msk (0x10UL)                 /*!< EPTXFUD (Bitfield-Mask: 0x01)                         */
#define USBFS_DEVICE_DIEP1INTF_CITO_Pos   (3UL)                     /*!< CITO (Bit 3)                                          */
#define USBFS_DEVICE_DIEP1INTF_CITO_Msk   (0x8UL)                   /*!< CITO (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP1INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DIEP1INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP1INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DIEP1INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DIEP2INTF  ======================================================= */
#define USBFS_DEVICE_DIEP2INTF_TXFE_Pos   (7UL)                     /*!< TXFE (Bit 7)                                          */
#define USBFS_DEVICE_DIEP2INTF_TXFE_Msk   (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP2INTF_IEPNE_Pos  (6UL)                     /*!< IEPNE (Bit 6)                                         */
#define USBFS_DEVICE_DIEP2INTF_IEPNE_Msk  (0x40UL)                  /*!< IEPNE (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP2INTF_EPTXFUD_Pos (4UL)                    /*!< EPTXFUD (Bit 4)                                       */
#define USBFS_DEVICE_DIEP2INTF_EPTXFUD_Msk (0x10UL)                 /*!< EPTXFUD (Bitfield-Mask: 0x01)                         */
#define USBFS_DEVICE_DIEP2INTF_CITO_Pos   (3UL)                     /*!< CITO (Bit 3)                                          */
#define USBFS_DEVICE_DIEP2INTF_CITO_Msk   (0x8UL)                   /*!< CITO (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP2INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DIEP2INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP2INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DIEP2INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DIEP3INTF  ======================================================= */
#define USBFS_DEVICE_DIEP3INTF_TXFE_Pos   (7UL)                     /*!< TXFE (Bit 7)                                          */
#define USBFS_DEVICE_DIEP3INTF_TXFE_Msk   (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP3INTF_IEPNE_Pos  (6UL)                     /*!< IEPNE (Bit 6)                                         */
#define USBFS_DEVICE_DIEP3INTF_IEPNE_Msk  (0x40UL)                  /*!< IEPNE (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP3INTF_EPTXFUD_Pos (4UL)                    /*!< EPTXFUD (Bit 4)                                       */
#define USBFS_DEVICE_DIEP3INTF_EPTXFUD_Msk (0x10UL)                 /*!< EPTXFUD (Bitfield-Mask: 0x01)                         */
#define USBFS_DEVICE_DIEP3INTF_CITO_Pos   (3UL)                     /*!< CITO (Bit 3)                                          */
#define USBFS_DEVICE_DIEP3INTF_CITO_Msk   (0x8UL)                   /*!< CITO (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DIEP3INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DIEP3INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DIEP3INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DIEP3INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DOEP0INTF  ======================================================= */
#define USBFS_DEVICE_DOEP0INTF_BTBSTP_Pos (6UL)                     /*!< BTBSTP (Bit 6)                                        */
#define USBFS_DEVICE_DOEP0INTF_BTBSTP_Msk (0x40UL)                  /*!< BTBSTP (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DOEP0INTF_EPRXFOVR_Pos (4UL)                   /*!< EPRXFOVR (Bit 4)                                      */
#define USBFS_DEVICE_DOEP0INTF_EPRXFOVR_Msk (0x10UL)                /*!< EPRXFOVR (Bitfield-Mask: 0x01)                        */
#define USBFS_DEVICE_DOEP0INTF_STPF_Pos   (3UL)                     /*!< STPF (Bit 3)                                          */
#define USBFS_DEVICE_DOEP0INTF_STPF_Msk   (0x8UL)                   /*!< STPF (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP0INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DOEP0INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP0INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DOEP0INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DOEP1INTF  ======================================================= */
#define USBFS_DEVICE_DOEP1INTF_BTBSTP_Pos (6UL)                     /*!< BTBSTP (Bit 6)                                        */
#define USBFS_DEVICE_DOEP1INTF_BTBSTP_Msk (0x40UL)                  /*!< BTBSTP (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DOEP1INTF_EPRXFOVR_Pos (4UL)                   /*!< EPRXFOVR (Bit 4)                                      */
#define USBFS_DEVICE_DOEP1INTF_EPRXFOVR_Msk (0x10UL)                /*!< EPRXFOVR (Bitfield-Mask: 0x01)                        */
#define USBFS_DEVICE_DOEP1INTF_STPF_Pos   (3UL)                     /*!< STPF (Bit 3)                                          */
#define USBFS_DEVICE_DOEP1INTF_STPF_Msk   (0x8UL)                   /*!< STPF (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP1INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DOEP1INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP1INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DOEP1INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DOEP2INTF  ======================================================= */
#define USBFS_DEVICE_DOEP2INTF_BTBSTP_Pos (6UL)                     /*!< BTBSTP (Bit 6)                                        */
#define USBFS_DEVICE_DOEP2INTF_BTBSTP_Msk (0x40UL)                  /*!< BTBSTP (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DOEP2INTF_EPRXFOVR_Pos (4UL)                   /*!< EPRXFOVR (Bit 4)                                      */
#define USBFS_DEVICE_DOEP2INTF_EPRXFOVR_Msk (0x10UL)                /*!< EPRXFOVR (Bitfield-Mask: 0x01)                        */
#define USBFS_DEVICE_DOEP2INTF_STPF_Pos   (3UL)                     /*!< STPF (Bit 3)                                          */
#define USBFS_DEVICE_DOEP2INTF_STPF_Msk   (0x8UL)                   /*!< STPF (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP2INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DOEP2INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP2INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DOEP2INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DOEP3INTF  ======================================================= */
#define USBFS_DEVICE_DOEP3INTF_BTBSTP_Pos (6UL)                     /*!< BTBSTP (Bit 6)                                        */
#define USBFS_DEVICE_DOEP3INTF_BTBSTP_Msk (0x40UL)                  /*!< BTBSTP (Bitfield-Mask: 0x01)                          */
#define USBFS_DEVICE_DOEP3INTF_EPRXFOVR_Pos (4UL)                   /*!< EPRXFOVR (Bit 4)                                      */
#define USBFS_DEVICE_DOEP3INTF_EPRXFOVR_Msk (0x10UL)                /*!< EPRXFOVR (Bitfield-Mask: 0x01)                        */
#define USBFS_DEVICE_DOEP3INTF_STPF_Pos   (3UL)                     /*!< STPF (Bit 3)                                          */
#define USBFS_DEVICE_DOEP3INTF_STPF_Msk   (0x8UL)                   /*!< STPF (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP3INTF_EPDIS_Pos  (1UL)                     /*!< EPDIS (Bit 1)                                         */
#define USBFS_DEVICE_DOEP3INTF_EPDIS_Msk  (0x2UL)                   /*!< EPDIS (Bitfield-Mask: 0x01)                           */
#define USBFS_DEVICE_DOEP3INTF_TF_Pos     (0UL)                     /*!< TF (Bit 0)                                            */
#define USBFS_DEVICE_DOEP3INTF_TF_Msk     (0x1UL)                   /*!< TF (Bitfield-Mask: 0x01)                              */
/* =======================================================  DIEP0LEN  ======================================================== */
#define USBFS_DEVICE_DIEP0LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DIEP0LEN_PCNT_Msk    (0x180000UL)              /*!< PCNT (Bitfield-Mask: 0x03)                            */
#define USBFS_DEVICE_DIEP0LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DIEP0LEN_TLEN_Msk    (0x7fUL)                  /*!< TLEN (Bitfield-Mask: 0x7f)                            */
/* =======================================================  DOEP0LEN  ======================================================== */
#define USBFS_DEVICE_DOEP0LEN_STPCNT_Pos  (29UL)                    /*!< STPCNT (Bit 29)                                       */
#define USBFS_DEVICE_DOEP0LEN_STPCNT_Msk  (0x60000000UL)            /*!< STPCNT (Bitfield-Mask: 0x03)                          */
#define USBFS_DEVICE_DOEP0LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DOEP0LEN_PCNT_Msk    (0x80000UL)               /*!< PCNT (Bitfield-Mask: 0x01)                            */
#define USBFS_DEVICE_DOEP0LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DOEP0LEN_TLEN_Msk    (0x7fUL)                  /*!< TLEN (Bitfield-Mask: 0x7f)                            */
/* =======================================================  DIEP1LEN  ======================================================== */
#define USBFS_DEVICE_DIEP1LEN_MCPF_Pos    (29UL)                    /*!< MCPF (Bit 29)                                         */
#define USBFS_DEVICE_DIEP1LEN_MCPF_Msk    (0x60000000UL)            /*!< MCPF (Bitfield-Mask: 0x03)                            */
#define USBFS_DEVICE_DIEP1LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DIEP1LEN_PCNT_Msk    (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_DEVICE_DIEP1LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DIEP1LEN_TLEN_Msk    (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
/* =======================================================  DIEP2LEN  ======================================================== */
#define USBFS_DEVICE_DIEP2LEN_MCPF_Pos    (29UL)                    /*!< MCPF (Bit 29)                                         */
#define USBFS_DEVICE_DIEP2LEN_MCPF_Msk    (0x60000000UL)            /*!< MCPF (Bitfield-Mask: 0x03)                            */
#define USBFS_DEVICE_DIEP2LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DIEP2LEN_PCNT_Msk    (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_DEVICE_DIEP2LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DIEP2LEN_TLEN_Msk    (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
/* =======================================================  DIEP3LEN  ======================================================== */
#define USBFS_DEVICE_DIEP3LEN_MCPF_Pos    (29UL)                    /*!< MCPF (Bit 29)                                         */
#define USBFS_DEVICE_DIEP3LEN_MCPF_Msk    (0x60000000UL)            /*!< MCPF (Bitfield-Mask: 0x03)                            */
#define USBFS_DEVICE_DIEP3LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DIEP3LEN_PCNT_Msk    (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_DEVICE_DIEP3LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DIEP3LEN_TLEN_Msk    (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
/* =======================================================  DOEP1LEN  ======================================================== */
#define USBFS_DEVICE_DOEP1LEN_STPCNT_RXDPID_Pos (29UL)              /*!< STPCNT_RXDPID (Bit 29)                                */
#define USBFS_DEVICE_DOEP1LEN_STPCNT_RXDPID_Msk (0x60000000UL)      /*!< STPCNT_RXDPID (Bitfield-Mask: 0x03)                   */
#define USBFS_DEVICE_DOEP1LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DOEP1LEN_PCNT_Msk    (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_DEVICE_DOEP1LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DOEP1LEN_TLEN_Msk    (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
/* =======================================================  DOEP2LEN  ======================================================== */
#define USBFS_DEVICE_DOEP2LEN_STPCNT_RXDPID_Pos (29UL)              /*!< STPCNT_RXDPID (Bit 29)                                */
#define USBFS_DEVICE_DOEP2LEN_STPCNT_RXDPID_Msk (0x60000000UL)      /*!< STPCNT_RXDPID (Bitfield-Mask: 0x03)                   */
#define USBFS_DEVICE_DOEP2LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DOEP2LEN_PCNT_Msk    (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_DEVICE_DOEP2LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DOEP2LEN_TLEN_Msk    (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
/* =======================================================  DOEP3LEN  ======================================================== */
#define USBFS_DEVICE_DOEP3LEN_STPCNT_RXDPID_Pos (29UL)              /*!< STPCNT_RXDPID (Bit 29)                                */
#define USBFS_DEVICE_DOEP3LEN_STPCNT_RXDPID_Msk (0x60000000UL)      /*!< STPCNT_RXDPID (Bitfield-Mask: 0x03)                   */
#define USBFS_DEVICE_DOEP3LEN_PCNT_Pos    (19UL)                    /*!< PCNT (Bit 19)                                         */
#define USBFS_DEVICE_DOEP3LEN_PCNT_Msk    (0x1ff80000UL)            /*!< PCNT (Bitfield-Mask: 0x3ff)                           */
#define USBFS_DEVICE_DOEP3LEN_TLEN_Pos    (0UL)                     /*!< TLEN (Bit 0)                                          */
#define USBFS_DEVICE_DOEP3LEN_TLEN_Msk    (0x7ffffUL)               /*!< TLEN (Bitfield-Mask: 0x7ffff)                         */
/* ======================================================  DIEP0TFSTAT  ====================================================== */
#define USBFS_DEVICE_DIEP0TFSTAT_IEPTFS_Pos (0UL)                   /*!< IEPTFS (Bit 0)                                        */
#define USBFS_DEVICE_DIEP0TFSTAT_IEPTFS_Msk (0xffffUL)              /*!< IEPTFS (Bitfield-Mask: 0xffff)                        */
/* ======================================================  DIEP1TFSTAT  ====================================================== */
#define USBFS_DEVICE_DIEP1TFSTAT_IEPTFS_Pos (0UL)                   /*!< IEPTFS (Bit 0)                                        */
#define USBFS_DEVICE_DIEP1TFSTAT_IEPTFS_Msk (0xffffUL)              /*!< IEPTFS (Bitfield-Mask: 0xffff)                        */
/* ======================================================  DIEP2TFSTAT  ====================================================== */
#define USBFS_DEVICE_DIEP2TFSTAT_IEPTFS_Pos (0UL)                   /*!< IEPTFS (Bit 0)                                        */
#define USBFS_DEVICE_DIEP2TFSTAT_IEPTFS_Msk (0xffffUL)              /*!< IEPTFS (Bitfield-Mask: 0xffff)                        */
/* ======================================================  DIEP3TFSTAT  ====================================================== */
#define USBFS_DEVICE_DIEP3TFSTAT_IEPTFS_Pos (0UL)                   /*!< IEPTFS (Bit 0)                                        */
#define USBFS_DEVICE_DIEP3TFSTAT_IEPTFS_Msk (0xffffUL)              /*!< IEPTFS (Bitfield-Mask: 0xffff)                        */


/* =========================================================================================================================== */
/* ================                                       USBFS_PWRCLK                                        ================ */
/* =========================================================================================================================== */

/* =======================================================  PWRCLKCTL  ======================================================= */
#define USBFS_PWRCLK_PWRCLKCTL_SUCLK_Pos  (0UL)                     /*!< SUCLK (Bit 0)                                         */
#define USBFS_PWRCLK_PWRCLKCTL_SUCLK_Msk  (0x1UL)                   /*!< SUCLK (Bitfield-Mask: 0x01)                           */
#define USBFS_PWRCLK_PWRCLKCTL_SHCLK_Pos  (1UL)                     /*!< SHCLK (Bit 1)                                         */
#define USBFS_PWRCLK_PWRCLKCTL_SHCLK_Msk  (0x2UL)                   /*!< SHCLK (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                           WWDGT                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CTL  ========================================================== */
#define WWDGT_CTL_WDGTEN_Pos              (7UL)                     /*!< WDGTEN (Bit 7)                                        */
#define WWDGT_CTL_WDGTEN_Msk              (0x80UL)                  /*!< WDGTEN (Bitfield-Mask: 0x01)                          */
#define WWDGT_CTL_CNT_Pos                 (0UL)                     /*!< CNT (Bit 0)                                           */
#define WWDGT_CTL_CNT_Msk                 (0x7fUL)                  /*!< CNT (Bitfield-Mask: 0x7f)                             */
/* ==========================================================  CFG  ========================================================== */
#define WWDGT_CFG_EWIE_Pos                (9UL)                     /*!< EWIE (Bit 9)                                          */
#define WWDGT_CFG_EWIE_Msk                (0x200UL)                 /*!< EWIE (Bitfield-Mask: 0x01)                            */
#define WWDGT_CFG_PSC_Pos                 (7UL)                     /*!< PSC (Bit 7)                                           */
#define WWDGT_CFG_PSC_Msk                 (0x180UL)                 /*!< PSC (Bitfield-Mask: 0x03)                             */
#define WWDGT_CFG_WIN_Pos                 (0UL)                     /*!< WIN (Bit 0)                                           */
#define WWDGT_CFG_WIN_Msk                 (0x7fUL)                  /*!< WIN (Bitfield-Mask: 0x7f)                             */
/* =========================================================  STAT  ========================================================== */
#define WWDGT_STAT_EWIF_Pos               (0UL)                     /*!< EWIF (Bit 0)                                          */
#define WWDGT_STAT_EWIF_Msk               (0x1UL)                   /*!< EWIF (Bitfield-Mask: 0x01)                            */


#ifdef __cplusplus
}
#endif

#endif /* GD32VF103_H */
