boards: Introduce atxmega-a1-xplained board
Add initial version. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke
Gerson Fernando Budke
parent
2de7dab0f4
commit
0232e9d89c
20
boards/atxmega-a1-xplained/Kconfig
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20
boards/atxmega-a1-xplained/Kconfig
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# Copyright (c) 2020 HAW Hamburg
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# Copyright (c) 2021 Gerson Fernando Budle
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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config BOARD
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default "atxmega-a1-xplained" if BOARD_ATXMEGA_A1_XPLAINED
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config BOARD_ATXMEGA_A1_XPLAINED
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bool
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default y
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select CPU_MODEL_XMEGA128A1
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select HAS_PERIPH_I2C
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select HAS_PERIPH_SPI
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select HAS_PERIPH_UART
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select HAVE_SAUL_GPIO
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5
boards/atxmega-a1-xplained/Makefile
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5
boards/atxmega-a1-xplained/Makefile
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MODULE = board
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DIRS = $(RIOTBOARD)/common/atxmega
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include $(RIOTBASE)/Makefile.base
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5
boards/atxmega-a1-xplained/Makefile.dep
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5
boards/atxmega-a1-xplained/Makefile.dep
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USEMODULE += boards_common_atxmega
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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7
boards/atxmega-a1-xplained/Makefile.features
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7
boards/atxmega-a1-xplained/Makefile.features
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@ -0,0 +1,7 @@
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CPU_MODEL = atxmega128a1
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_uart
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include $(RIOTBOARD)/common/atxmega/Makefile.features
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4
boards/atxmega-a1-xplained/Makefile.include
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4
boards/atxmega-a1-xplained/Makefile.include
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override RAM_LEN = 65536
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override EXP_RAM = 1
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include $(RIOTBOARD)/common/atxmega/Makefile.include
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52
boards/atxmega-a1-xplained/doc.txt
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52
boards/atxmega-a1-xplained/doc.txt
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/**
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@defgroup boards_atxmega-a1-xplained ATxmega-A1 Xplained board
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@ingroup boards
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@brief Support for the ATxmega-A1 Xplained board
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## Overview
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The ATxmega-A1 Xplained is an old reference to develop with XMEGA's.
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### MCU
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| MCU | ATxmega128A1 |
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|:------------- |:--------------------------------------------- |
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| Family | AVR/ATxmega |
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| Vendor | Microchip (previously Atmel) |
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| Flash | 128KiB |
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| RAM | 8KiB |
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| EBI | 16MiB SRAM, 128MiB SDRAM |
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| EEPROM | 2KiB |
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| Frequency | up to 32MHz |
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| Timers | 8 16bit (32 bit combining 2 x 16 bit) |
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| ACs | 4 Analog Comparators |
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| ADCs | 2 - 16 channels - 12 bit - 2msps |
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| ADCs | 2 - 2 channels - 12 bit - 1msps |
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| UARTs | 8 (can be used in SPI mode) with 1 IrDA |
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| SPIs | 4 |
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| I2Cs | 4 (called TWI) |
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| DMA | 4 Channels |
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| Event System | 8 Channels |
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| Ext. INT | All GPIOs |
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| Crypto | AES/DES, CRC-16, CRC-32 |
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| Vcc | 2.7V - 5.5V (when clocked at 8MHz) |
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| Datasheet | [Datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/ATxmega128A1U-64A1U-Data-Sheet-DS40002058A.pdf) |
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| Xmega Manual | [Manual](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual.pdf) |
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| Guide | [AVR1924 PDF](http://ww1.microchip.com/downloads/en/AppNotes/doc8370.pdf) |
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| Schematic | [AVR1924 ZIP](https://ww1.microchip.com/downloads/en/AppNotes/AVR1924.zip) |
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## Flashing the Device
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The ATxmega-A1 Xplained needs an external programmer like atmelice.
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In order to flash the ATxmega128A1, simple run:
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make BOARD=atxmega-a1-xplained flash
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## Serial Terminal
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The CDC-ACM will enumerate a /dev/ttyACM device. The STDIO at CDC-ACM shares
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with J4 pins 2/3.
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make BOARD=atxmega-a1-xplained term
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*/
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186
boards/atxmega-a1-xplained/include/board.h
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186
boards/atxmega-a1-xplained/include/board.h
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/*
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* Copyright (C) 2021 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_atxmega-a1-xplained
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* @{
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*
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* @file
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* @brief Board specific definitions for the ATxmegaA1 Xplained board.
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "cpu.h"
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#include "macros/units.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clock configuration
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*/
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#define CLOCK_CORECLOCK MHZ(32)
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/**
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* @brief Use the UART-2 for STDIO on this board
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*/
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#define STDIO_UART_DEV UART_DEV(2)
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/**
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* @name Baudrate for STDIO terminal
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*
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* The standard configuration for STDIO in cpu/atxmega/periph/uart.c
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* is to use double speed.
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*
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* For 32MHz F_CPU following Baudrate have good error rates
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* 115200
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*
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* Matches this with BAUD in Board/Makefile.include
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*
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* @{
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*/
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#ifndef STDIO_UART_BAUDRATE
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#define STDIO_UART_BAUDRATE (115200U)
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#endif
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/** @} */
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/**
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* @name LED pin definitions and handlers
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* @{
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*/
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#define LED_PORT PORTE
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#define LED0_PIN GPIO_PIN(PORT_E, 0)
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#define LED0_MODE GPIO_OUT
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#define LED0_MASK (PIN0_bm)
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#define LED0_ON (LED_PORT.OUTCLR = LED0_MASK)
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#define LED0_OFF (LED_PORT.OUTSET = LED0_MASK)
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#define LED0_TOGGLE (LED_PORT.OUTTGL = LED0_MASK)
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#define LED1_PIN GPIO_PIN(PORT_E, 1)
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#define LED1_MODE GPIO_OUT
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#define LED1_MASK (PIN1_bm)
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#define LED1_ON (LED_PORT.OUTCLR = LED1_MASK)
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#define LED1_OFF (LED_PORT.OUTSET = LED1_MASK)
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#define LED1_TOGGLE (LED_PORT.OUTTGL = LED1_MASK)
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#define LED2_PIN GPIO_PIN(PORT_E, 2)
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#define LED2_MODE GPIO_OUT
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#define LED2_MASK (PIN2_bm)
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#define LED2_ON (LED_PORT.OUTCLR = LED2_MASK)
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#define LED2_OFF (LED_PORT.OUTSET = LED2_MASK)
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#define LED2_TOGGLE (LED_PORT.OUTTGL = LED2_MASK)
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#define LED3_PIN GPIO_PIN(PORT_E, 3)
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#define LED3_MODE GPIO_OUT
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#define LED3_MASK (PIN3_bm)
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#define LED3_ON (LED_PORT.OUTCLR = LED3_MASK)
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#define LED3_OFF (LED_PORT.OUTSET = LED3_MASK)
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#define LED3_TOGGLE (LED_PORT.OUTTGL = LED3_MASK)
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#define LED4_PIN GPIO_PIN(PORT_E, 4)
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#define LED4_MODE GPIO_OUT
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#define LED4_MASK (PIN4_bm)
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#define LED4_ON (LED_PORT.OUTCLR = LED4_MASK)
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#define LED4_OFF (LED_PORT.OUTSET = LED4_MASK)
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#define LED4_TOGGLE (LED_PORT.OUTTGL = LED4_MASK)
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#define LED5_PIN GPIO_PIN(PORT_E, 5)
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#define LED5_MODE GPIO_OUT
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#define LED5_MASK (PIN5_bm)
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#define LED5_ON (LED_PORT.OUTCLR = LED5_MASK)
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#define LED5_OFF (LED_PORT.OUTSET = LED5_MASK)
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#define LED5_TOGGLE (LED_PORT.OUTTGL = LED5_MASK)
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#define LED6_PIN GPIO_PIN(PORT_E, 6)
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#define LED6_MODE GPIO_OUT
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#define LED6_MASK (PIN6_bm)
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#define LED6_ON (LED_PORT.OUTCLR = LED6_MASK)
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#define LED6_OFF (LED_PORT.OUTSET = LED6_MASK)
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#define LED6_TOGGLE (LED_PORT.OUTTGL = LED6_MASK)
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#define LED7_PIN GPIO_PIN(PORT_E, 7)
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#define LED7_MODE GPIO_OUT
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#define LED7_MASK (PIN7_bm)
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#define LED7_ON (LED_PORT.OUTCLR = LED7_MASK)
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#define LED7_OFF (LED_PORT.OUTSET = LED7_MASK)
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#define LED7_TOGGLE (LED_PORT.OUTTGL = LED7_MASK)
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#define LED_PORT_MASK (LED0_MASK | LED1_MASK | LED2_MASK | LED3_MASK | \
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LED4_MASK | LED5_MASK | LED6_MASK | LED7_MASK)
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/** @} */
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/**
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* @name Button pin configuration
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* @{
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*/
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#define BTN0_PIN GPIO_PIN(PORT_D, 0)
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#define BTN0_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN0_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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#define BTN1_PIN GPIO_PIN(PORT_D, 1)
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#define BTN1_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN1_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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#define BTN2_PIN GPIO_PIN(PORT_D, 2)
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#define BTN2_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN2_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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#define BTN3_PIN GPIO_PIN(PORT_D, 3)
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#define BTN3_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN3_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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#define BTN4_PIN GPIO_PIN(PORT_D, 4)
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#define BTN4_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN4_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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#define BTN5_PIN GPIO_PIN(PORT_D, 5)
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#define BTN5_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN5_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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#define BTN6_PIN GPIO_PIN(PORT_R, 0)
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#define BTN6_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN6_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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#define BTN7_PIN GPIO_PIN(PORT_R, 1)
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#define BTN7_MODE (GPIO_IN | GPIO_OPC_PU | GPIO_SLEW_RATE)
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#define BTN7_INT_FLANK (GPIO_ISC_FALLING | GPIO_LVL_LOW)
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/** @} */
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/**
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* @name xtimer configuration values
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* if XTIMER_HZ > 1MHz then (XTIMER_HZ != (1000000ul << XTIMER_SHIFT))
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* if XTIMER_HZ < 1MHz then ((XTIMER_HZ << XTIMER_SHIFT) != 1000000ul)
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*
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* 32MHz Core Clock
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* XTIMER_HZ 4000000 (clkdiv 8 ) XTIMER_SHIFT 2
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* XTIMER_HZ 1000000 () XTIMER_SHIFT 0
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* XTIMER_HZ 500000 (clkdiv 64) XTIMER_SHIFT 1
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* XTIMER_HZ 250000 (clkdiv 128) XTIMER_SHIFT 2
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* XTIMER_HZ 31250 (clkdiv 1024) XTIMER_SHIFT 5
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*
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* @{
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*/
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#define XTIMER_DEV TIMER_DEV(0)
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#define XTIMER_CHAN (0)
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#define XTIMER_WIDTH (16)
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#define XTIMER_HZ KHZ(500)
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#define XTIMER_BACKOFF (150)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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137
boards/atxmega-a1-xplained/include/gpio_params.h
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137
boards/atxmega-a1-xplained/include/gpio_params.h
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@ -0,0 +1,137 @@
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/*
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* Copyright (C) 2021 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_atxmega-a1-xplained
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* @{
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*
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* @file
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* @brief Configuration of SAUL mapped GPIO pins
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "SW0",
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.pin = BTN0_PIN,
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.mode = BTN0_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "SW1",
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.pin = BTN1_PIN,
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.mode = BTN1_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "SW2",
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.pin = BTN2_PIN,
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.mode = BTN2_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "SW3",
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.pin = BTN3_PIN,
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.mode = BTN3_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "SW4",
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.pin = BTN4_PIN,
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.mode = BTN4_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "SW5",
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.pin = BTN5_PIN,
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.mode = BTN5_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "SW6",
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.pin = BTN6_PIN,
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.mode = BTN6_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "SW7",
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.pin = BTN7_PIN,
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.mode = BTN7_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED0",
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.pin = LED0_PIN,
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.mode = LED0_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED1",
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.pin = LED1_PIN,
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.mode = LED1_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED2",
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.pin = LED2_PIN,
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.mode = LED2_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED3",
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.pin = LED3_PIN,
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.mode = LED3_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED4",
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.pin = LED4_PIN,
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.mode = LED4_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED5",
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.pin = LED5_PIN,
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.mode = LED5_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED6",
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.pin = LED6_PIN,
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.mode = LED6_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED7",
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.pin = LED7_PIN,
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.mode = LED7_MODE,
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.flags = SAUL_GPIO_INVERTED,
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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242
boards/atxmega-a1-xplained/include/periph_conf.h
Normal file
242
boards/atxmega-a1-xplained/include/periph_conf.h
Normal file
@ -0,0 +1,242 @@
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/*
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* Copyright (C) 2021 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_atxmega-a1-xplained
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Peripheral MCU configuration for the ATxmegaA1 Xplained board.
|
||||
*
|
||||
* @author Gerson Fernando Budke <nandojve@gmail.com>
|
||||
*/
|
||||
#include "mutex.h"
|
||||
|
||||
#ifndef PERIPH_CONF_H
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <avr/io.h>
|
||||
|
||||
#include "periph_cpu.h"
|
||||
|
||||
/**
|
||||
* @name Timer peripheral configuration
|
||||
* @{
|
||||
*/
|
||||
static const timer_conf_t timer_config[] = {
|
||||
{
|
||||
.dev = (void *)&TCC1,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_C, PR_TC1_bm),
|
||||
.type = TC_TYPE_1,
|
||||
.int_lvl = { CPU_INT_LVL_LOW,
|
||||
CPU_INT_LVL_OFF,
|
||||
CPU_INT_LVL_OFF,
|
||||
CPU_INT_LVL_OFF },
|
||||
},
|
||||
{
|
||||
.dev = (void *)&TCC0,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_C, PR_TC0_bm),
|
||||
.type = TC_TYPE_0,
|
||||
.int_lvl = { CPU_INT_LVL_LOW,
|
||||
CPU_INT_LVL_LOW,
|
||||
CPU_INT_LVL_LOW,
|
||||
CPU_INT_LVL_LOW },
|
||||
}
|
||||
};
|
||||
|
||||
#define TIMER_0_ISRA TCC1_CCA_vect
|
||||
|
||||
#define TIMER_1_ISRA TCC0_CCA_vect
|
||||
#define TIMER_1_ISRB TCC0_CCB_vect
|
||||
#define TIMER_1_ISRC TCC0_CCC_vect
|
||||
#define TIMER_1_ISRD TCC0_CCD_vect
|
||||
|
||||
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name UART configuration
|
||||
* @{
|
||||
*/
|
||||
static const uart_conf_t uart_config[] = {
|
||||
{ /* J1 */
|
||||
.dev = &USARTF0,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_F, PR_USART0_bm),
|
||||
.rx_pin = GPIO_PIN(PORT_F, 2),
|
||||
.tx_pin = GPIO_PIN(PORT_F, 3),
|
||||
#ifdef MODULE_PERIPH_UART_HW_FC
|
||||
.rts_pin = GPIO_UNDEF,
|
||||
.cts_pin = GPIO_UNDEF,
|
||||
#endif
|
||||
.rx_int_lvl = CPU_INT_LVL_LOW,
|
||||
.tx_int_lvl = CPU_INT_LVL_LOW,
|
||||
.dre_int_lvl = CPU_INT_LVL_OFF,
|
||||
},
|
||||
{ /* J3 - Shared with SAUL */
|
||||
.dev = &USARTD0,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_D, PR_USART0_bm),
|
||||
.rx_pin = GPIO_PIN(PORT_D, 2),
|
||||
.tx_pin = GPIO_PIN(PORT_D, 3),
|
||||
#ifdef MODULE_PERIPH_UART_HW_FC
|
||||
.rts_pin = GPIO_UNDEF,
|
||||
.cts_pin = GPIO_UNDEF,
|
||||
#endif
|
||||
.rx_int_lvl = CPU_INT_LVL_LOW,
|
||||
.tx_int_lvl = CPU_INT_LVL_LOW,
|
||||
.dre_int_lvl = CPU_INT_LVL_OFF,
|
||||
},
|
||||
{ /* J4 */
|
||||
.dev = &USARTC0,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_C, PR_USART0_bm),
|
||||
.rx_pin = GPIO_PIN(PORT_C, 2),
|
||||
.tx_pin = GPIO_PIN(PORT_C, 3),
|
||||
#ifdef MODULE_PERIPH_UART_HW_FC
|
||||
.rts_pin = GPIO_UNDEF,
|
||||
.cts_pin = GPIO_UNDEF,
|
||||
#endif
|
||||
.rx_int_lvl = CPU_INT_LVL_LOW,
|
||||
.tx_int_lvl = CPU_INT_LVL_LOW,
|
||||
.dre_int_lvl = CPU_INT_LVL_OFF,
|
||||
},
|
||||
};
|
||||
|
||||
/* interrupt function name mapping */
|
||||
#define UART_0_RXC_ISR USARTF0_RXC_vect /* Reception Complete Interrupt */
|
||||
#define UART_0_DRE_ISR USARTF0_DRE_vect /* Data Register Empty Interrupt */
|
||||
#define UART_0_TXC_ISR USARTF0_TXC_vect /* Transmission Complete Interrupt */
|
||||
|
||||
#define UART_1_RXC_ISR USARTD0_RXC_vect
|
||||
#define UART_1_DRE_ISR USARTD0_DRE_vect
|
||||
#define UART_1_TXC_ISR USARTD0_TXC_vect
|
||||
|
||||
#define UART_2_RXC_ISR USARTC0_RXC_vect
|
||||
#define UART_2_DRE_ISR USARTC0_DRE_vect
|
||||
#define UART_2_TXC_ISR USARTC0_TXC_vect
|
||||
|
||||
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = &TWIF,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_F, PR_TWI_bm),
|
||||
.sda_pin = GPIO_PIN(PORT_F, 0),
|
||||
.scl_pin = GPIO_PIN(PORT_F, 1),
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.int_lvl = CPU_INT_LVL_LOW,
|
||||
},
|
||||
{
|
||||
.dev = &TWIC,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_C, PR_TWI_bm),
|
||||
.sda_pin = GPIO_PIN(PORT_C, 0),
|
||||
.scl_pin = GPIO_PIN(PORT_C, 1),
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.int_lvl = CPU_INT_LVL_LOW,
|
||||
},
|
||||
};
|
||||
|
||||
#define I2C_0_ISR TWIF_TWIM_vect
|
||||
#define I2C_1_ISR TWIC_TWIM_vect
|
||||
|
||||
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
* @{
|
||||
*/
|
||||
static const spi_conf_t spi_config[] = {
|
||||
{
|
||||
.dev = &SPIF,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_F, PR_SPI_bm),
|
||||
.sck_pin = GPIO_PIN(PORT_F, 7),
|
||||
.miso_pin = GPIO_PIN(PORT_F, 6),
|
||||
.mosi_pin = GPIO_PIN(PORT_F, 5),
|
||||
.ss_pin = GPIO_PIN(PORT_F, 4),
|
||||
},
|
||||
{
|
||||
.dev = &SPIC,
|
||||
.pwr = PWR_RED_REG(PWR_PORT_C, PR_SPI_bm),
|
||||
.sck_pin = GPIO_PIN(PORT_C, 7),
|
||||
.miso_pin = GPIO_PIN(PORT_C, 6),
|
||||
.mosi_pin = GPIO_PIN(PORT_C, 5),
|
||||
.ss_pin = GPIO_PIN(PORT_C, 4),
|
||||
},
|
||||
};
|
||||
|
||||
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name EBI configuration
|
||||
*
|
||||
* For more information, see ebi_conf_t structure.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
static const ebi_conf_t ebi_config = {
|
||||
.addr_bits = 12,
|
||||
.flags = (EBI_PORT_SDRAM | EBI_PORT_3PORT),
|
||||
.sram_ale = 0,
|
||||
.lpc_ale = 0,
|
||||
.sdram = {
|
||||
0,
|
||||
1024,
|
||||
6400,
|
||||
EBI_CS_SDMODE_NORMAL_gc,
|
||||
EBI_SDRAM_CAS_LAT_3CLK,
|
||||
EBI_SDRAM_ROW_BITS_12,
|
||||
EBI_SDCOL_10BIT_gc,
|
||||
EBI_MRDLY_2CLK_gc,
|
||||
EBI_ROWCYCDLY_7CLK_gc,
|
||||
EBI_RPDLY_7CLK_gc,
|
||||
EBI_WRDLY_1CLK_gc,
|
||||
EBI_ESRDLY_7CLK_gc,
|
||||
EBI_ROWCOLDLY_7CLK_gc,
|
||||
},
|
||||
.cs = { { EBI_CS_MODE_DISABLED_gc,
|
||||
0,
|
||||
EBI_CS_SRWS_0CLK_gc,
|
||||
0x0UL,
|
||||
},
|
||||
{ EBI_CS_MODE_DISABLED_gc,
|
||||
0,
|
||||
EBI_CS_SRWS_0CLK_gc,
|
||||
0x0UL,
|
||||
},
|
||||
{ EBI_CS_MODE_DISABLED_gc,
|
||||
0,
|
||||
EBI_CS_SRWS_0CLK_gc,
|
||||
0x0UL,
|
||||
},
|
||||
{ EBI_CS_MODE_SDRAM_gc,
|
||||
EBI_CS_ASIZE_8MB_gc,
|
||||
EBI_CS_SRWS_0CLK_gc,
|
||||
0x0UL,
|
||||
},
|
||||
},
|
||||
};
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#include "periph_conf_common.h"
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
@ -4,6 +4,7 @@ include ../Makefile.tests_common
|
||||
|
||||
# list of ATxmega boards
|
||||
BOARD_WHITELIST = \
|
||||
atxmega-a1-xplained \
|
||||
atxmega-a1u-xpro \
|
||||
atxmega-a3bu-xplained \
|
||||
#
|
||||
|
||||
@ -36,6 +36,16 @@
|
||||
*/
|
||||
#define BOARD_EBI_RAM_BASE (0x10000)
|
||||
#define BOARD_EBI_RAM_SIZE (0x30000)
|
||||
#elif defined(BOARD_ATXMEGA_A1_XPLAINED)
|
||||
/**
|
||||
* 8MB bytes installed
|
||||
* 64k bytes reserved for RIOT-OS
|
||||
*
|
||||
* The remaining memory can be addressable by hugemem methods.
|
||||
* It is free for user and it is tested here
|
||||
*/
|
||||
#define BOARD_EBI_RAM_BASE (0x10000)
|
||||
#define BOARD_EBI_RAM_SIZE (0x7F0000)
|
||||
#else
|
||||
/**
|
||||
* 128k bytes installed
|
||||
|
||||
@ -3,6 +3,7 @@ include ../Makefile.tests_common
|
||||
FEATURES_REQUIRED = periph_timer
|
||||
|
||||
BOARDS_TIMER_500kHz := \
|
||||
atxmega-a1-xplained \
|
||||
atxmega-a1u-xpro \
|
||||
atxmega-a3bu-xplained \
|
||||
#
|
||||
|
||||
@ -8,6 +8,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
||||
atmega256rfr2-xpro \
|
||||
atmega328p \
|
||||
atmega328p-xplained-mini \
|
||||
atxmega-a1-xplained \
|
||||
atxmega-a1u-xpro \
|
||||
atxmega-a3bu-xplained \
|
||||
avr-rss2 \
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user