diff --git a/boards/common/stm32/include/cfg_i2c1_pb8_pb9.h b/boards/common/stm32/include/cfg_i2c1_pb8_pb9.h new file mode 100644 index 0000000000..cc199e0e21 --- /dev/null +++ b/boards/common/stm32/include/cfg_i2c1_pb8_pb9.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Common configuration for STM32 I2C + * + * @author Alexandre Abadie + */ + +#ifndef CFG_I2C1_PB8_PB9_H +#define CFG_I2C1_PB8_PB9_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name I2C configuration + * @{ + */ +static const i2c_conf_t i2c_config[] = { + { + .dev = I2C1, + .speed = I2C_SPEED_NORMAL, + .scl_pin = GPIO_PIN(PORT_B, 8), + .sda_pin = GPIO_PIN(PORT_B, 9), + .scl_af = GPIO_AF4, + .sda_af = GPIO_AF4, + .bus = APB1, +#if CPU_FAM_STM32F4 + .rcc_mask = RCC_APB1ENR_I2C1EN, + .clk = CLOCK_APB1, + .irqn = I2C1_EV_IRQn, +#elif CPU_FAM_STM32L4 + .rcc_mask = RCC_APB1ENR1_I2C1EN, + .irqn = I2C1_ER_IRQn, +#elif CPU_FAM_STM32F7 + .rcc_mask = RCC_APB1ENR_I2C1EN, + .irqn = I2C1_ER_IRQn, +#endif + } +}; + +#if CPU_FAM_STM32F4 +#define I2C_0_ISR isr_i2c1_ev +#elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7 +#define I2C_0_ISR isr_i2c1_er +#endif + +#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CFG_I2C1_PB8_PB9_H */ +/** @} */ diff --git a/boards/common/stm32/include/f4/cfg_clock_100_8_1.h b/boards/common/stm32/include/f4/cfg_clock_100_8_1.h new file mode 100644 index 0000000000..cf4007dff4 --- /dev/null +++ b/boards/common/stm32/include/f4/cfg_clock_100_8_1.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2018 Freie Universität Berlin + * 2017 OTA keys S.A. + * 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Configure STM32F4 clock to 100MHz using PLL + * + * @author Hauke Petersen + * @author Vincent Dupont + * @author Alexandre Abadie + */ + +#ifndef F4_CFG_CLOCK_100_8_1_H +#define F4_CFG_CLOCK_100_8_1_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock settings + * + * @note This is auto-generated from + * `cpu/stm32_common/dist/clk_conf/clk_conf.c` + * @{ + */ +/* give the target core clock (HCLK) frequency [in Hz], + * maximum: 100MHz */ +#define CLOCK_CORECLOCK (100000000U) +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (8000000U) +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) + +/* Main PLL factors */ +#define CLOCK_PLL_M (4) +#define CLOCK_PLL_N (200) +#define CLOCK_PLL_P (4) +#define CLOCK_PLL_Q (0) + +/* PLL I2S configuration */ +#define CLOCK_ENABLE_PLL_I2S (1) +#define CLOCK_PLL_I2S_SRC (0) +#define CLOCK_PLL_I2S_M (4) +#define CLOCK_PLL_I2S_N (216) +#define CLOCK_PLL_I2S_P (0) +#define CLOCK_PLL_I2S_Q (9) + +/* Use alternative source for 48MHz clock */ +#define CLOCK_USE_ALT_48MHZ (1) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* F4_CFG_CLOCK_100_8_1_H */ +/** @} */ diff --git a/boards/common/stm32/include/f4/cfg_clock_84_8_1.h b/boards/common/stm32/include/f4/cfg_clock_84_8_1.h new file mode 100644 index 0000000000..8424046f1f --- /dev/null +++ b/boards/common/stm32/include/f4/cfg_clock_84_8_1.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2018 Freie Universität Berlin + * 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Configure STM32F4 clock to 84MHz using PLL + * + * @author Hauke Petersen + * @author Alexandre Abadie + */ + +#ifndef F4_CFG_CLOCK_84_8_1_H +#define F4_CFG_CLOCK_84_8_1_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock settings + * + * @note This is auto-generated from + * `cpu/stm32_common/dist/clk_conf/clk_conf.c` + * @{ + */ +/* give the target core clock (HCLK) frequency [in Hz], + * maximum: 84MHz */ +#define CLOCK_CORECLOCK (84000000U) +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (8000000U) +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */ +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) + +/* Main PLL factors */ +#define CLOCK_PLL_M (4) +#define CLOCK_PLL_N (168) +#define CLOCK_PLL_P (4) +#define CLOCK_PLL_Q (7) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* F4_CFG_CLOCK_84_8_1_H */ +/** @} */ diff --git a/boards/common/stm32/include/f4/cfg_clock_96_8_1.h b/boards/common/stm32/include/f4/cfg_clock_96_8_1.h new file mode 100644 index 0000000000..abcf2377e1 --- /dev/null +++ b/boards/common/stm32/include/f4/cfg_clock_96_8_1.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2018 Freie Universität Berlin + * 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Configure STM32F4 clock to 96MHz using PLL + * + * @author Hauke Petersen + * @author Alexandre Abadie + */ + +#ifndef F4_CFG_CLOCK_96_8_1_H +#define F4_CFG_CLOCK_96_8_1_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock settings + * + * @note This is auto-generated from + * `cpu/stm32_common/dist/clk_conf/clk_conf.c` + * @{ + */ +/* give the target core clock (HCLK) frequency [in Hz], + * maximum: 100MHz */ +#define CLOCK_CORECLOCK (96000000U) +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (8000000U) +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) + +/* Main PLL factors */ +#define CLOCK_PLL_M (4) +#define CLOCK_PLL_N (192) +#define CLOCK_PLL_P (4) +#define CLOCK_PLL_Q (8) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* F4_CFG_CLOCK_96_8_1_H */ +/** @} */ diff --git a/boards/nucleo-f401re/include/periph_conf.h b/boards/nucleo-f401re/include/periph_conf.h index d697b2ecee..37bb66b36c 100644 --- a/boards/nucleo-f401re/include/periph_conf.h +++ b/boards/nucleo-f401re/include/periph_conf.h @@ -22,42 +22,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f4/cfg_clock_84_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 84MHz */ -#define CLOCK_CORECLOCK (84000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (168) -#define CLOCK_PLL_P (4) -#define CLOCK_PLL_Q (7) -/** @} */ - /** * @name Timer configuration * @{ @@ -249,31 +220,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ - -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-f410rb/include/periph_conf.h b/boards/nucleo-f410rb/include/periph_conf.h index 0f61d4393f..17e4524369 100644 --- a/boards/nucleo-f410rb/include/periph_conf.h +++ b/boards/nucleo-f410rb/include/periph_conf.h @@ -22,42 +22,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f4/cfg_clock_96_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 100MHz */ -#define CLOCK_CORECLOCK (96000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (192) -#define CLOCK_PLL_P (4) -#define CLOCK_PLL_Q (8) -/** @} */ - /** * @name Timer configuration * @{ @@ -178,30 +149,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-f411re/include/periph_conf.h b/boards/nucleo-f411re/include/periph_conf.h index 49c0283071..558ecd2fb6 100644 --- a/boards/nucleo-f411re/include/periph_conf.h +++ b/boards/nucleo-f411re/include/periph_conf.h @@ -22,42 +22,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f4/cfg_clock_96_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 100MHz */ -#define CLOCK_CORECLOCK (96000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (192) -#define CLOCK_PLL_P (4) -#define CLOCK_PLL_Q (8) -/** @} */ - /** * @name Timer configuration * @{ @@ -208,30 +179,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-f412zg/include/periph_conf.h b/boards/nucleo-f412zg/include/periph_conf.h index 968d472b5d..5536df2a25 100644 --- a/boards/nucleo-f412zg/include/periph_conf.h +++ b/boards/nucleo-f412zg/include/periph_conf.h @@ -24,53 +24,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f4/cfg_clock_100_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 100MHz */ -#define CLOCK_CORECLOCK (100000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (200) -#define CLOCK_PLL_P (4) -#define CLOCK_PLL_Q (0) - -/* PLL I2S configuration */ -#define CLOCK_ENABLE_PLL_I2S (1) -#define CLOCK_PLL_I2S_SRC (0) -#define CLOCK_PLL_I2S_M (4) -#define CLOCK_PLL_I2S_N (216) -#define CLOCK_PLL_I2S_P (0) -#define CLOCK_PLL_I2S_Q (9) - -/* Use alternative source for 48MHz clock */ -#define CLOCK_USE_ALT_48MHZ (1) -/** @} */ - /** * @name Timer configuration * @{ @@ -219,30 +179,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-f413zh/include/periph_conf.h b/boards/nucleo-f413zh/include/periph_conf.h index 5a88440574..4b3fd2adf3 100644 --- a/boards/nucleo-f413zh/include/periph_conf.h +++ b/boards/nucleo-f413zh/include/periph_conf.h @@ -24,53 +24,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f4/cfg_clock_100_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 100MHz */ -#define CLOCK_CORECLOCK (100000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* Main PLL factors */ -#define CLOCK_PLL_M (4) -#define CLOCK_PLL_N (200) -#define CLOCK_PLL_P (4) -#define CLOCK_PLL_Q (0) - -/* PLL I2S configuration */ -#define CLOCK_ENABLE_PLL_I2S (1) -#define CLOCK_PLL_I2S_SRC (0) -#define CLOCK_PLL_I2S_M (4) -#define CLOCK_PLL_I2S_N (216) -#define CLOCK_PLL_I2S_P (0) -#define CLOCK_PLL_I2S_Q (9) - -/* Use alternative source for 48MHz clock */ -#define CLOCK_USE_ALT_48MHZ (1) -/** @} */ - /** * @name DMA streams configuration * @{ @@ -248,30 +208,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-f429zi/include/periph_conf.h b/boards/nucleo-f429zi/include/periph_conf.h index 9c5387b515..acccd0d258 100644 --- a/boards/nucleo-f429zi/include/periph_conf.h +++ b/boards/nucleo-f429zi/include/periph_conf.h @@ -23,6 +23,7 @@ #include "periph_cpu.h" #include "f4/cfg_clock_168_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #include "cfg_spi_divtable.h" #ifdef __cplusplus @@ -157,30 +158,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-f446re/include/periph_conf.h b/boards/nucleo-f446re/include/periph_conf.h index cc69f628e5..25ca136d84 100644 --- a/boards/nucleo-f446re/include/periph_conf.h +++ b/boards/nucleo-f446re/include/periph_conf.h @@ -23,6 +23,7 @@ #include "periph_cpu.h" #include "f4/cfg_clock_180_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #include "cfg_spi_divtable.h" #ifdef __cplusplus @@ -213,31 +214,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ - -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-f446ze/include/periph_conf.h b/boards/nucleo-f446ze/include/periph_conf.h index ff88e4573d..fccd35c128 100644 --- a/boards/nucleo-f446ze/include/periph_conf.h +++ b/boards/nucleo-f446ze/include/periph_conf.h @@ -23,6 +23,7 @@ #include "periph_cpu.h" #include "f4/cfg_clock_180_8_1.h" +#include "cfg_i2c1_pb8_pb9.h" #include "cfg_spi_divtable.h" #ifdef __cplusplus @@ -157,30 +158,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .clk = CLOCK_APB1, - .irqn = I2C1_EV_IRQn - } -}; - -#define I2C_0_ISR isr_i2c1_ev - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * @{ diff --git a/boards/nucleo-f722ze/include/periph_conf.h b/boards/nucleo-f722ze/include/periph_conf.h index d932e50e96..0535821b6f 100644 --- a/boards/nucleo-f722ze/include/periph_conf.h +++ b/boards/nucleo-f722ze/include/periph_conf.h @@ -22,6 +22,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { @@ -136,29 +137,6 @@ static const uart_conf_t uart_config[] = { #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR_I2C1EN, - .irqn = I2C1_ER_IRQn, - } -}; - -#define I2C_0_ISR isr_i2c1_er - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - #ifdef __cplusplus } #endif diff --git a/boards/nucleo-f746zg/Makefile.features b/boards/nucleo-f746zg/Makefile.features index f45a13c595..593b57950b 100644 --- a/boards/nucleo-f746zg/Makefile.features +++ b/boards/nucleo-f746zg/Makefile.features @@ -1,4 +1,5 @@ # Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_rtc FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_uart diff --git a/boards/nucleo-f746zg/include/periph_conf.h b/boards/nucleo-f746zg/include/periph_conf.h index ca6cb9962f..18169713ee 100644 --- a/boards/nucleo-f746zg/include/periph_conf.h +++ b/boards/nucleo-f746zg/include/periph_conf.h @@ -22,6 +22,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { diff --git a/boards/nucleo-l476rg/include/periph_conf.h b/boards/nucleo-l476rg/include/periph_conf.h index 6ad36e0adf..33130f0b91 100644 --- a/boards/nucleo-l476rg/include/periph_conf.h +++ b/boards/nucleo-l476rg/include/periph_conf.h @@ -26,6 +26,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { @@ -249,29 +250,6 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ -/** - * @name I2C configuration - * @{ - */ -static const i2c_conf_t i2c_config[] = { - { - .dev = I2C1, - .speed = I2C_SPEED_NORMAL, - .scl_pin = GPIO_PIN(PORT_B, 8), - .sda_pin = GPIO_PIN(PORT_B, 9), - .scl_af = GPIO_AF4, - .sda_af = GPIO_AF4, - .bus = APB1, - .rcc_mask = RCC_APB1ENR1_I2C1EN, - .irqn = I2C1_ER_IRQn, - } -}; - -#define I2C_0_ISR isr_i2c1_er - -#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) -/** @} */ - /** * @name ADC configuration * diff --git a/boards/nucleo-l496zg/Makefile.features b/boards/nucleo-l496zg/Makefile.features index 67dc676d95..ac8975dfb3 100644 --- a/boards/nucleo-l496zg/Makefile.features +++ b/boards/nucleo-l496zg/Makefile.features @@ -1,4 +1,5 @@ # Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc FEATURES_PROVIDED += periph_rtt diff --git a/boards/nucleo-l496zg/include/periph_conf.h b/boards/nucleo-l496zg/include/periph_conf.h index 0366faa80b..b16e308951 100644 --- a/boards/nucleo-l496zg/include/periph_conf.h +++ b/boards/nucleo-l496zg/include/periph_conf.h @@ -20,6 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" {