diff --git a/cpu/efm32/Makefile b/cpu/efm32/Makefile index 519aa8138e..11066d31e8 100644 --- a/cpu/efm32/Makefile +++ b/cpu/efm32/Makefile @@ -16,6 +16,9 @@ endif ifneq (,$(filter cpu_efm32pg12b,$(USEMODULE))) DIRS += families/efm32pg12b endif +ifneq (,$(filter cpu_efm32zg,$(USEMODULE))) + DIRS += families/efm32zg +endif ifneq (,$(filter cpu_efr32mg1p,$(USEMODULE))) DIRS += families/efr32mg1p endif diff --git a/cpu/efm32/doc.txt b/cpu/efm32/doc.txt index 4e037d791e..c18df88139 100644 --- a/cpu/efm32/doc.txt +++ b/cpu/efm32/doc.txt @@ -94,6 +94,12 @@ * @brief Silicon Labs's EFM32PG12B MCUs family implementation */ +/** + * @defgroup cpu_efm32zg Silicon Labs EFM32ZG family + * @ingroup cpu_efm32 + * @brief Silicon Labs's EFM32ZG MCUs family implementation + */ + /** * @defgroup cpu_efr32mg1p Silicon Labs EFR32MG1P family * @ingroup cpu_efm32 diff --git a/cpu/efm32/families/efm32zg/Kconfig b/cpu/efm32/families/efm32zg/Kconfig new file mode 100644 index 0000000000..63f65639b3 --- /dev/null +++ b/cpu/efm32/families/efm32zg/Kconfig @@ -0,0 +1,97 @@ +# Copyright (c) 2020 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. + +config CPU_FAM_EFM32ZG + bool + select CPU_CORE_CORTEX_M0PLUS + select CPU_COMMON_EFM32 + +## CPU Models +config CPU_MODEL_EFM32ZG222F16 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG108F8 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG110F16 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG108F32 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG210F4 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG210F32 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG222F8 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG110F4 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG210F16 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG108F4 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG210F8 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG222F32 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG222F4 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG110F32 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG110F8 + bool + select CPU_FAM_EFM32ZG + +config CPU_MODEL_EFM32ZG108F16 + bool + select CPU_FAM_EFM32ZG + +## Common CPU symbols +config CPU_FAM + default "efm32zg" if CPU_FAM_EFM32ZG + +config CPU_MODEL + default "efm32zg222f16" if CPU_MODEL_EFM32ZG222F16 + default "efm32zg108f8" if CPU_MODEL_EFM32ZG108F8 + default "efm32zg110f16" if CPU_MODEL_EFM32ZG110F16 + default "efm32zg108f32" if CPU_MODEL_EFM32ZG108F32 + default "efm32zg210f4" if CPU_MODEL_EFM32ZG210F4 + default "efm32zg210f32" if CPU_MODEL_EFM32ZG210F32 + default "efm32zg222f8" if CPU_MODEL_EFM32ZG222F8 + default "efm32zg110f4" if CPU_MODEL_EFM32ZG110F4 + default "efm32zg210f16" if CPU_MODEL_EFM32ZG210F16 + default "efm32zg108f4" if CPU_MODEL_EFM32ZG108F4 + default "efm32zg210f8" if CPU_MODEL_EFM32ZG210F8 + default "efm32zg222f32" if CPU_MODEL_EFM32ZG222F32 + default "efm32zg222f4" if CPU_MODEL_EFM32ZG222F4 + default "efm32zg110f32" if CPU_MODEL_EFM32ZG110F32 + default "efm32zg110f8" if CPU_MODEL_EFM32ZG110F8 + default "efm32zg108f16" if CPU_MODEL_EFM32ZG108F16 diff --git a/cpu/efm32/families/efm32zg/Makefile b/cpu/efm32/families/efm32zg/Makefile new file mode 100644 index 0000000000..d9c2a28094 --- /dev/null +++ b/cpu/efm32/families/efm32zg/Makefile @@ -0,0 +1,6 @@ +MODULE = cpu_efm32zg + +# (file triggers compiler bug. see #5775) +SRC_NOLTO += vectors.c + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/efm32/families/efm32zg/Makefile.include b/cpu/efm32/families/efm32zg/Makefile.include new file mode 100644 index 0000000000..5555a2b578 --- /dev/null +++ b/cpu/efm32/families/efm32zg/Makefile.include @@ -0,0 +1,7 @@ +# Find the header file that should exist if the CPU is supported. Only headers +# for supported boards are included, but to support another CPU, it should be +# as easy as adding the header file only. +EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efm32zg/include/vendor/$(CPU_MODEL).h) + +# include vendor device headers +INCLUDES += -I$(RIOTCPU)/efm32/families/efm32zg/include/vendor diff --git a/cpu/efm32/families/efm32zg/efm32-info.mk b/cpu/efm32/families/efm32zg/efm32-info.mk new file mode 100644 index 0000000000..df8893bee3 --- /dev/null +++ b/cpu/efm32/families/efm32zg/efm32-info.mk @@ -0,0 +1,24 @@ +# This file is automatically generated, and should not be changed. There is +# probably little reason to edit this file anyway, since it should already +# contain all information for the EFM32ZG family of CPUs. + +# The intended usage is to grep for the exact model name, and split by spaces +# to get the required information. + +# CPU - Family - Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio? +EFM32_INFO_efm32zg222f16 = 0 cortex-m0plus 0x00000000 0x00004000 0x20000000 0x00001000 0 0 0 +EFM32_INFO_efm32zg108f8 = 0 cortex-m0plus 0x00000000 0x00002000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg110f16 = 0 cortex-m0plus 0x00000000 0x00004000 0x20000000 0x00001000 0 0 0 +EFM32_INFO_efm32zg108f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0 +EFM32_INFO_efm32zg210f4 = 0 cortex-m0plus 0x00000000 0x00001000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg210f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0 +EFM32_INFO_efm32zg222f8 = 0 cortex-m0plus 0x00000000 0x00002000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg110f4 = 0 cortex-m0plus 0x00000000 0x00001000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg210f16 = 0 cortex-m0plus 0x00000000 0x00004000 0x20000000 0x00001000 0 0 0 +EFM32_INFO_efm32zg108f4 = 0 cortex-m0plus 0x00000000 0x00001000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg210f8 = 0 cortex-m0plus 0x00000000 0x00002000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg222f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0 +EFM32_INFO_efm32zg222f4 = 0 cortex-m0plus 0x00000000 0x00001000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg110f32 = 0 cortex-m0plus 0x00000000 0x00008000 0x20000000 0x00001000 0 0 0 +EFM32_INFO_efm32zg110f8 = 0 cortex-m0plus 0x00000000 0x00002000 0x20000000 0x00000800 0 0 0 +EFM32_INFO_efm32zg108f16 = 0 cortex-m0plus 0x00000000 0x00004000 0x20000000 0x00001000 0 0 0 diff --git a/cpu/efm32/families/efm32zg/system.c b/cpu/efm32/families/efm32zg/system.c new file mode 100644 index 0000000000..e7af3806c2 --- /dev/null +++ b/cpu/efm32/families/efm32zg/system.c @@ -0,0 +1,375 @@ +/***************************************************************************//** + * @file system_efm32zg.c + * @brief CMSIS Cortex-M0+ System Layer for EFM32ZG devices. + * @version 5.4.0 + ****************************************************************************** + * # License + * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** LFRCO frequency, tuned to below frequency during manufacturing. */ +#define EFM32_LFRCO_FREQ (32768UL) +/** ULFRCO frequency. */ +#define EFM32_ULFRCO_FREQ (1000UL) + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */ +/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#ifndef EFM32_HFXO_FREQ +/** HFXO frequency. */ +#define EFM32_HFXO_FREQ (24000000UL) +#endif + +/** Maximum HFRCO frequency. */ +#define EFM32_HFRCO_MAX_FREQ (21000000UL) + +/* Do not define variable if HF crystal oscillator not present */ +#if (EFM32_HFXO_FREQ > 0) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System HFXO clock. */ +static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +#ifndef EFM32_LFXO_FREQ +/** LFXO frequency. */ +#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) +#endif + +/* Do not define variable if LF crystal oscillator not present */ +#if (EFM32_LFXO_FREQ > 0) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System LFXO clock. */ +static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = 14000000UL; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current core clock frequency. + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemCoreClockGet(void) +{ + uint32_t ret; + + ret = SystemHFClockGet(); + ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT; + + /* Keep CMSIS variable up-to-date just in case */ + SystemCoreClock = ret; + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is an EFR32 proprietary function, not part of the CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ +#if (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ) + return EFM32_HFRCO_MAX_FREQ; +#else + return EFM32_HFXO_FREQ; +#endif +} + +/***************************************************************************//** + * @brief + * Get the current HFCLK frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current HFCLK frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFClockGet(void) +{ + uint32_t ret; + + switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL + | CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL)) { + case CMU_STATUS_LFXOSEL: +#if (EFM32_LFXO_FREQ > 0) + ret = SystemLFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + case CMU_STATUS_LFRCOSEL: + ret = EFM32_LFRCO_FREQ; + break; + + case CMU_STATUS_HFXOSEL: +#if (EFM32_HFXO_FREQ > 0) + ret = SystemHFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + default: /* CMU_STATUS_HFRCOSEL */ + switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) { + case CMU_HFRCOCTRL_BAND_21MHZ: + ret = 21000000U; + break; + + case CMU_HFRCOCTRL_BAND_14MHZ: + ret = 14000000U; + break; + + case CMU_HFRCOCTRL_BAND_11MHZ: + ret = 11000000U; + break; + + case CMU_HFRCOCTRL_BAND_7MHZ: + ret = 6600000U; + break; + + case CMU_HFRCOCTRL_BAND_1MHZ: + ret = 1200000U; + break; + + default: + ret = 0; + break; + } + break; + } + + return ret; +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * HFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + return SystemHFXOClock; +#else + return 0; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if ((CMU->STATUS & CMU_STATUS_HFXOSEL) != 0U) { + /* The function will update the global variable */ + (void)SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + /* Currently we assume that this frequency is properly tuned during */ + /* manufacturing and is not changed after reset. If future requirements */ + /* for re-tuning by user, we can add support for that. */ + return EFM32_LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return EFM32_ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + return SystemLFXOClock; +#else + return 0; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + SystemLFXOClock = freq; + + /* Update core clock frequency if LFXO is used to clock core */ + if ((CMU->STATUS & CMU_STATUS_LFXOSEL) != 0U) { + /* The function will update the global variable */ + (void)SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} diff --git a/cpu/efm32/families/efm32zg/vectors.c b/cpu/efm32/families/efm32zg/vectors.c new file mode 100644 index 0000000000..57f38e074b --- /dev/null +++ b/cpu/efm32/families/efm32zg/vectors.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2015-2018 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_efm32zg + * @{ + * + * @file + * @brief Startup code and interrupt vector definition + * + * @author Hauke Petersen + * @author Bas Stottelaar + * + * @} + */ + +#include "vectors_cortexm.h" + +/* define a local dummy handler as it needs to be in the same compilation unit + * as the alias definition */ +void dummy_handler(void) +{ + dummy_handler_default(); +} + +/* Silicon Labs specific interrupt vector */ +WEAK_DEFAULT void isr_dma(void); +WEAK_DEFAULT void isr_gpio_even(void); +WEAK_DEFAULT void isr_timer0(void); +WEAK_DEFAULT void isr_acmp0(void); +WEAK_DEFAULT void isr_adc0(void); +WEAK_DEFAULT void isr_i2c0(void); +WEAK_DEFAULT void isr_gpio_odd(void); +WEAK_DEFAULT void isr_timer1(void); +WEAK_DEFAULT void isr_usart1_rx(void); +WEAK_DEFAULT void isr_usart1_tx(void); +WEAK_DEFAULT void isr_leuart0(void); +WEAK_DEFAULT void isr_pcnt0(void); +WEAK_DEFAULT void isr_rtc(void); +WEAK_DEFAULT void isr_cmu(void); +WEAK_DEFAULT void isr_vcmp(void); +WEAK_DEFAULT void isr_msc(void); +WEAK_DEFAULT void isr_aes(void); + +/* interrupt vector table */ +ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { + [ 0] = isr_dma, /* DMA */ + [ 1] = isr_gpio_even, /* GPIO_EVEN */ + [ 2] = isr_timer0, /* TIMER0 */ + [ 3] = isr_acmp0, /* ACMP0 */ + [ 4] = isr_adc0, /* ADC0 */ + [ 5] = isr_i2c0, /* I2C0 */ + [ 6] = isr_gpio_odd, /* GPIO_ODD */ + [ 7] = isr_timer1, /* TIMER1 */ + [ 8] = isr_usart1_rx, /* USART1_RX */ + [ 9] = isr_usart1_tx, /* USART1_TX */ + [10] = isr_leuart0, /* LEUART0 */ + [11] = isr_pcnt0, /* PCNT0 */ + [12] = isr_rtc, /* RTC */ + [13] = isr_cmu, /* CMU */ + [14] = isr_vcmp, /* VCMP */ + [15] = isr_msc, /* MSC */ + [16] = isr_aes, /* AES */ +};