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cpu/stm32: adapt Kconfig clock configuration for f0

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This commit is contained in:
Alexandre Abadie 2020-08-30 16:54:57 +02:00
parent 948777936d
commit 03ee0c938f
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GPG Key ID: 1C919A403CAE1405
1 changed files with 16 additions and 2 deletions
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18
cpu/stm32/kconfigs/Kconfig.clk
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@ -6,7 +6,7 @@
# #
menu "STM32 clock configuration" menu "STM32 clock configuration"
depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_F0 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
choice choice
bool "Clock source selection" bool "Clock source selection"
@ -47,11 +47,11 @@ endchoice
endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
config CUSTOM_PLL_PARAMS config CUSTOM_PLL_PARAMS
bool "Configure PLL parameters" bool "Configure PLL parameters"
depends on USE_CLOCK_PLL depends on USE_CLOCK_PLL
if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
config CLOCK_PLL_M config CLOCK_PLL_M
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
default 1 if CPU_FAM_G0 default 1 if CPU_FAM_G0
@ -112,6 +112,20 @@ endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
if CPU_FAM_F0
config CLOCK_PLL_PREDIV
int "PLLIN division factor" if USE_CLOCK_PLL && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6
default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
default 1
range 1 16
config CLOCK_PLL_MUL
int "PLLIN multiply factor" if USE_CLOCK_PLL
default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
default 6
range 2 16
endif
if CPU_FAM_L0 || CPU_FAM_L1 if CPU_FAM_L0 || CPU_FAM_L1
config CLOCK_PLL_DIV config CLOCK_PLL_DIV
int "Main PLL division factor" if USE_CLOCK_PLL int "Main PLL division factor" if USE_CLOCK_PLL