From 04f49a1929bced803f0a38f9056da6ad3632015f Mon Sep 17 00:00:00 2001 From: DipSwitch Date: Mon, 24 Aug 2015 21:46:36 +0200 Subject: [PATCH] cpu: fix stm32l1 cpuid driver for cat 1/2 --- cpu/stm32l1/ldscripts/stm32l151rba.ld | 36 ++++++++++++++++++++++++++ cpu/stm32l1/ldscripts/stm32l151rc.ld | 9 +++++++ cpu/stm32l1/ldscripts/stm32l152ret6.ld | 9 +++++++ cpu/stm32l1/periph/cpuid.c | 4 +-- 4 files changed, 56 insertions(+), 2 deletions(-) create mode 100644 cpu/stm32l1/ldscripts/stm32l151rba.ld diff --git a/cpu/stm32l1/ldscripts/stm32l151rba.ld b/cpu/stm32l1/ldscripts/stm32l151rba.ld new file mode 100644 index 0000000000..17339c3fac --- /dev/null +++ b/cpu/stm32l1/ldscripts/stm32l151rba.ld @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2015 Engineering-Spirit + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @addtogroup cpu_stm32l1 + * @{ + * + * @file + * @brief Memory definitions for the STM32L151RB-A + * + * @author Nick van IJzendoorn + * + * @} + */ + +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rw) : ORIGIN = 0x20000000, LENGTH = 32K + + /* see STM32L1 Reference Manual (31.2 Unique device ID registers (96 bits)) + * Base address: + * - 0x1FF80050 for Cat.1 and Cat.2 devices + * - 0x1FF800D0 for Cat.3, Cat.4, Cat.5 and Cat.6 devices + */ + cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12 +} + +_cpuid_address = ORIGIN(cpuid); + +INCLUDE cortexm_base.ld diff --git a/cpu/stm32l1/ldscripts/stm32l151rc.ld b/cpu/stm32l1/ldscripts/stm32l151rc.ld index 6344f1fc98..38f061b5e3 100644 --- a/cpu/stm32l1/ldscripts/stm32l151rc.ld +++ b/cpu/stm32l1/ldscripts/stm32l151rc.ld @@ -22,6 +22,15 @@ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K ram (xrw) : ORIGIN = 0x20000000, LENGTH = 32K + + /* see STM32L1 Reference Manual (31.2 Unique device ID registers (96 bits)) + * Base address: + * - 0x1FF80050 for Cat.1 and Cat.2 devices + * - 0x1FF800D0 for Cat.3, Cat.4, Cat.5 and Cat.6 devices + */ + cpuid (r) : ORIGIN = 0x1ff800d0, LENGTH = 12 } +_cpuid_address = ORIGIN(cpuid); + INCLUDE cortexm_base.ld diff --git a/cpu/stm32l1/ldscripts/stm32l152ret6.ld b/cpu/stm32l1/ldscripts/stm32l152ret6.ld index 256baa223f..c98faaae2c 100644 --- a/cpu/stm32l1/ldscripts/stm32l152ret6.ld +++ b/cpu/stm32l1/ldscripts/stm32l152ret6.ld @@ -22,6 +22,15 @@ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K ram (xrw) : ORIGIN = 0x20000000, LENGTH = 80K + + /* see STM32L1 Reference Manual (31.2 Unique device ID registers (96 bits)) + * Base address: + * - 0x1FF80050 for Cat.1 and Cat.2 devices + * - 0x1FF800D0 for Cat.3, Cat.4, Cat.5 and Cat.6 devices + */ + cpuid (r) : ORIGIN = 0x1ff800d0, LENGTH = 12 } +_cpuid_address = ORIGIN(cpuid); + INCLUDE cortexm_base.ld diff --git a/cpu/stm32l1/periph/cpuid.c b/cpu/stm32l1/periph/cpuid.c index 5eeeec29c6..6d3b096ab1 100644 --- a/cpu/stm32l1/periph/cpuid.c +++ b/cpu/stm32l1/periph/cpuid.c @@ -20,11 +20,11 @@ #include "periph/cpuid.h" -#define STM32L1_CPUID_ADDR (0x1ff800d0) +extern volatile uint32_t _cpuid_address[3]; void cpuid_get(void *id) { - memcpy(id, (void *)(STM32L1_CPUID_ADDR), CPUID_ID_LEN); + memcpy(id, (void *)(&_cpuid_address), CPUID_ID_LEN); } /** @} */