cpu/stm32_common: adapt i2c driver to stm32f1
This commit is contained in:
Alexandre Abadie
dylad
parent
2aed31906e
commit
06e11c5586
@ -26,6 +26,7 @@
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Toon Stegen <toon.stegen@altran.com>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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@ -103,9 +104,14 @@ void i2c_init(i2c_t dev)
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/* configure pins */
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DEBUG("[i2c] init: configuring pins\n");
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gpio_init(i2c_config[dev].scl_pin, GPIO_OD_PU);
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gpio_init_af(i2c_config[dev].scl_pin, i2c_config[dev].scl_af);
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gpio_init(i2c_config[dev].sda_pin, GPIO_OD_PU);
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#ifdef CPU_FAM_STM32F1
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gpio_init_af(i2c_config[dev].scl_pin, GPIO_AF_OUT_OD);
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gpio_init_af(i2c_config[dev].sda_pin, GPIO_AF_OUT_OD);
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#else
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gpio_init_af(i2c_config[dev].scl_pin, i2c_config[dev].scl_af);
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gpio_init_af(i2c_config[dev].sda_pin, i2c_config[dev].sda_af);
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#endif
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/* configure device */
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DEBUG("[i2c] init: configuring device\n");
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@ -128,9 +134,14 @@ void i2c_init(i2c_t dev)
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gpio_set(i2c_config[dev].scl_pin);
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/* reset pins for alternate function */
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gpio_init(i2c_config[dev].scl_pin, GPIO_OD_PU);
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gpio_init_af(i2c_config[dev].scl_pin, i2c_config[dev].scl_af);
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gpio_init(i2c_config[dev].sda_pin, GPIO_OD_PU);
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#ifdef CPU_FAM_STM32F1
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gpio_init_af(i2c_config[dev].scl_pin, GPIO_AF_OUT_OD);
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gpio_init_af(i2c_config[dev].sda_pin, GPIO_AF_OUT_OD);
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#else
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gpio_init_af(i2c_config[dev].scl_pin, i2c_config[dev].scl_af);
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gpio_init_af(i2c_config[dev].sda_pin, i2c_config[dev].sda_af);
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#endif
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/* make peripheral soft reset */
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i2c->CR1 |= I2C_CR1_SWRST;
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i2c->CR1 &= ~I2C_CR1_SWRST;
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@ -1,547 +0,0 @@
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/*
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* Copyright (C) 2014 FU Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f1
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* @ingroup drivers_periph_i2c
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* @{
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*
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* @file
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* @brief Low-level I2C driver implementation
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*
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* @note This implementation only implements the 7-bit addressing mode.
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*
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* For implementation details please refer to STM application note AN2824.
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "irq.h"
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#include "mutex.h"
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#include "periph_conf.h"
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#include "periph/i2c.h"
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#include "periph/gpio.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/* static function definitions */
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static void _i2c_init(I2C_TypeDef *i2c, int ccr);
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static void _pin_config(gpio_t pin_scl, gpio_t pin_sda);
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static void _start(I2C_TypeDef *dev, uint8_t address, uint8_t rw_flag, uint8_t *err);
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static inline void _clear_addr(I2C_TypeDef *dev);
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static inline void _write(I2C_TypeDef *dev, const uint8_t *data, int length, uint8_t *err);
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static inline void _stop(I2C_TypeDef *dev, uint8_t *err);
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/**
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* @brief Array holding one pre-initialized mutex for each I2C device
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*/
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static mutex_t locks[] = {
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#if I2C_0_EN
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[I2C_0] = MUTEX_INIT,
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#endif
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#if I2C_1_EN
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[I2C_1] = MUTEX_INIT,
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#endif
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#if I2C_2_EN
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[I2C_2] = MUTEX_INIT
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#endif
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#if I2C_3_EN
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[I2C_3] = MUTEX_INIT
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#endif
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};
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static uint8_t err_flag[] = {
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#if I2C_0_EN
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[I2C_0] = 0x00,
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#endif
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#if I2C_1_EN
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[I2C_1] = 0x00,
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#endif
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#if I2C_2_EN
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[I2C_2] = 0x00
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#endif
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#if I2C_3_EN
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[I2C_3] = 0x00
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#endif
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};
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int i2c_init_master(i2c_t dev, i2c_speed_t speed)
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{
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I2C_TypeDef *i2c;
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gpio_t pin_scl, pin_sda;
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int ccr;
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/* read speed configuration */
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switch (speed) {
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case I2C_SPEED_NORMAL:
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ccr = I2C_APBCLK / 200000;
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break;
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case I2C_SPEED_FAST:
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ccr = I2C_APBCLK / 800000;
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break;
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default:
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return -2;
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}
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/* read static device configuration */
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switch (dev) {
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#if I2C_0_EN
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case I2C_0:
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i2c = I2C_0_DEV;
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pin_scl = I2C_0_SCL_PIN;
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pin_sda = I2C_0_SDA_PIN;
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I2C_0_CLKEN();
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NVIC_SetPriority(I2C_0_ERR_IRQ, I2C_IRQ_PRIO);
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NVIC_EnableIRQ(I2C_0_ERR_IRQ);
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break;
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#endif
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#if I2C_1_EN
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case I2C_1:
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i2c = I2C_1_DEV;
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pin_scl = I2C_1_SCL_PIN;
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pin_sda = I2C_1_SDA_PIN;
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I2C_1_CLKEN();
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NVIC_SetPriority(I2C_1_ERR_IRQ, I2C_IRQ_PRIO);
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NVIC_EnableIRQ(I2C_1_ERR_IRQ);
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break;
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#endif
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default:
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return -1;
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}
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/* disable peripheral */
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i2c->CR1 &= ~I2C_CR1_PE;
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/* configure pins */
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_pin_config(pin_scl, pin_sda);
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/* configure device */
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_i2c_init(i2c, ccr);
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/* make sure the analog filters don't hang -> see errata sheet 2.14.7 */
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if (i2c->SR2 & I2C_SR2_BUSY) {
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DEBUG("LINE BUSY AFTER RESET -> toggle pins now\n");
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/* disable peripheral */
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i2c->CR1 &= ~I2C_CR1_PE;
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/* re-run pin config to toggle and re-configure pins */
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_pin_config(pin_scl, pin_sda);
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/* make peripheral soft reset */
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i2c->CR1 |= I2C_CR1_SWRST;
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i2c->CR1 &= ~I2C_CR1_SWRST;
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/* enable device */
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_i2c_init(i2c, ccr);
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}
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return 0;
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}
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static void _i2c_init(I2C_TypeDef *i2c, int ccr)
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{
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/* disable device and set ACK bit */
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i2c->CR1 = I2C_CR1_ACK;
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/* configure I2C clock and enable error interrupts */
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i2c->CR2 = (I2C_APBCLK / 1000000) | I2C_CR2_ITERREN;
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i2c->CCR = ccr;
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i2c->TRISE = (I2C_APBCLK / 1000000) + 1;
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/* configure device */
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i2c->OAR1 = 0; /* makes sure we are in 7-bit address mode */
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/* enable device */
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i2c->CR1 |= I2C_CR1_PE;
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}
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static void _pin_config(gpio_t scl, gpio_t sda)
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{
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/* toggle pins to reset analog filter -> see datasheet */
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/* set as output */
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gpio_init(scl, GPIO_OUT);
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gpio_init(sda, GPIO_OUT);
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/* run through toggling sequence */
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gpio_set(scl);
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gpio_set(sda);
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gpio_clear(sda);
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gpio_clear(scl);
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gpio_set(scl);
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gpio_set(sda);
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/* configure the pins alternate function */
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gpio_init_af(scl, GPIO_AF_OUT_OD);
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gpio_init_af(sda, GPIO_AF_OUT_OD);
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}
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int i2c_acquire(i2c_t dev)
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{
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if (dev >= I2C_NUMOF) {
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return -1;
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}
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mutex_lock(&locks[dev]);
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return 0;
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}
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int i2c_release(i2c_t dev)
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{
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if (dev >= I2C_NUMOF) {
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return -1;
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}
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mutex_unlock(&locks[dev]);
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return 0;
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}
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int i2c_read_byte(i2c_t dev, uint8_t address, void *data)
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{
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return i2c_read_bytes(dev, address, data, 1);
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}
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int i2c_read_bytes(i2c_t dev, uint8_t address, void *data, int length)
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{
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int i = 0;
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I2C_TypeDef *i2c;
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uint8_t *my_data = data;
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switch (dev) {
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#if I2C_0_EN
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case I2C_0:
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i2c = I2C_0_DEV;
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break;
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#endif
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#if I2C_1_EN
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case I2C_1:
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i2c = I2C_1_DEV;
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break;
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#endif
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default:
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return -1;
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}
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DEBUG("Send Slave address and wait for ADDR == 1\n");
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_start(i2c, address, I2C_FLAG_READ, &err_flag[dev]);
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if (err_flag[dev]) {
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return -2;
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}
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DEBUG("Clear ADDR\n");
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_clear_addr(i2c);
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switch (length) {
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case 1:
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break;
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case 2:
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DEBUG("Set POS and ACK bit\n");
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i2c->CR1 |= (I2C_CR1_POS | I2C_CR1_ACK);
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DEBUG("Crit block: clear ACK flag\n");
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i2c->CR1 &= ~(I2C_CR1_ACK);
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DEBUG("Wait for transfer to be completed\n");
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while (!(i2c->SR1 & I2C_SR1_BTF)) {}
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break;
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default:
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i2c->CR1 |= (I2C_CR1_ACK);
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while (i < (length - 3)) {
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DEBUG("Wait until byte was received\n");
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while (!(i2c->SR1 & I2C_SR1_RXNE)) {}
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DEBUG("Copy byte from DR\n");
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my_data[i++] = i2c->DR;
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}
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DEBUG("Reading the last 3 bytes, waiting for BTF flag\n");
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while (!(i2c->SR1 & I2C_SR1_BTF)) {}
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DEBUG("Read N-3 byte\n");
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my_data[i++] = i2c->DR;
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}
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DEBUG("Clear ACK\n");
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i2c->CR1 &= ~(I2C_CR1_ACK);
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DEBUG("Setting STOP=1\n");
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i2c->CR1 |= (I2C_CR1_STOP);
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while (i < length) {
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DEBUG("Wait for RXNE == 1\n");
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while (!(i2c->SR1 & I2C_SR1_RXNE)) {}
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DEBUG("Read byte\n");
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my_data[i++] = i2c->DR;
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}
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DEBUG("wait for STOP bit to be cleared again\n");
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while (i2c->CR1 & I2C_CR1_STOP) {}
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DEBUG("reset POS = 0 and ACK = 1\n");
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i2c->CR1 &= ~(I2C_CR1_POS);
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i2c->CR1 |= (I2C_CR1_ACK);
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return length;
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}
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int i2c_read_reg(i2c_t dev, uint8_t address, uint8_t reg, void *data)
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{
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return i2c_read_regs(dev, address, reg, data, 1);
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}
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int i2c_read_regs(i2c_t dev, uint8_t address, uint8_t reg, void *data, int length)
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{
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I2C_TypeDef *i2c;
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switch (dev) {
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#if I2C_0_EN
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case I2C_0:
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i2c = I2C_0_DEV;
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break;
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#endif
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#if I2C_1_EN
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case I2C_1:
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i2c = I2C_1_DEV;
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break;
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#endif
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default:
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return -1;
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}
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/* send start condition and slave address */
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DEBUG("Send slave address and clear ADDR flag\n");
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_start(i2c, address, I2C_FLAG_WRITE, &err_flag[dev]);
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_clear_addr(i2c);
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DEBUG("Write reg into DR\n");
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i2c->DR = reg;
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_stop(i2c, &err_flag[dev]);
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if (err_flag[dev]) {
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return -2;
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}
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DEBUG("Now start a read transaction\n");
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return i2c_read_bytes(dev, address, data, length);
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}
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int i2c_write_byte(i2c_t dev, uint8_t address, uint8_t data)
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{
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return i2c_write_bytes(dev, address, &data, 1);
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}
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int i2c_write_bytes(i2c_t dev, uint8_t address, const void *data, int length)
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{
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I2C_TypeDef *i2c;
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switch (dev) {
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#if I2C_0_EN
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case I2C_0:
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i2c = I2C_0_DEV;
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break;
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#endif
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#if I2C_1_EN
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case I2C_1:
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i2c = I2C_1_DEV;
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break;
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#endif
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default:
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return -1;
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}
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/* start transmission and send slave address */
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DEBUG("sending start sequence\n");
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_start(i2c, address, I2C_FLAG_WRITE, &err_flag[dev]);
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_clear_addr(i2c);
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/* send out data bytes */
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_write(i2c, data, length, &err_flag[dev]);
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/* end transmission */
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DEBUG("Ending transmission\n");
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_stop(i2c, &err_flag[dev]);
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DEBUG("STOP condition was send out\n");
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if (err_flag[dev]) {
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return -2;
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}
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else {
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return length;
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}
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}
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int i2c_write_reg(i2c_t dev, uint8_t address, uint8_t reg, uint8_t data)
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{
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return i2c_write_regs(dev, address, reg, &data, 1);
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}
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int i2c_write_regs(i2c_t dev, uint8_t address, uint8_t reg, const void *data, int length)
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{
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I2C_TypeDef *i2c;
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switch (dev) {
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#if I2C_0_EN
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case I2C_0:
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i2c = I2C_0_DEV;
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break;
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#endif
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#if I2C_1_EN
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case I2C_1:
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i2c = I2C_1_DEV;
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break;
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#endif
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default:
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return -1;
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}
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/* start transmission and send slave address */
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_start(i2c, address, I2C_FLAG_WRITE, &err_flag[dev]);
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_clear_addr(i2c);
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/* send register address and wait for complete transfer to be finished*/
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_write(i2c, ®, 1, &err_flag[dev]);
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/* write data to register */
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_write(i2c, data, length, &err_flag[dev]);
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/* finish transfer */
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_stop(i2c, &err_flag[dev]);
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if (err_flag[dev]) {
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return -2;
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}
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else {
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/* return number of bytes send */
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return length;
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}
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}
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void i2c_poweron(i2c_t dev)
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{
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switch (dev) {
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#if I2C_0_EN
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case I2C_0:
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I2C_0_CLKEN();
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break;
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#endif
|
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#if I2C_1_EN
|
||||
case I2C_1:
|
||||
I2C_1_CLKEN();
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void i2c_poweroff(i2c_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if I2C_0_EN
|
||||
case I2C_0:
|
||||
while (I2C_0_DEV->SR2 & I2C_SR2_BUSY) {}
|
||||
I2C_0_CLKDIS();
|
||||
break;
|
||||
#endif
|
||||
#if I2C_1_EN
|
||||
case I2C_1:
|
||||
while (I2C_1_DEV->SR2 & I2C_SR2_BUSY) {}
|
||||
I2C_1_CLKDIS();
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static void _start(I2C_TypeDef *dev, uint8_t address, uint8_t rw_flag, uint8_t *err)
|
||||
{
|
||||
/* flag that there's no error (yet) */
|
||||
*err = 0x00;
|
||||
/* wait for device to be ready */
|
||||
DEBUG("Wait for device to be ready\n");
|
||||
while (dev->SR2 & I2C_SR2_BUSY) {}
|
||||
/* generate start condition */
|
||||
DEBUG("Generate start condition\n");
|
||||
dev->CR1 |= I2C_CR1_START;
|
||||
DEBUG("Wait for SB flag to be set\n");
|
||||
while (!(dev->SR1 & I2C_SR1_SB)) {}
|
||||
/* send address and read/write flag */
|
||||
DEBUG("Send address\n");
|
||||
dev->DR = (address << 1) | rw_flag;
|
||||
/* clear ADDR flag by reading first SR1 and then SR2 */
|
||||
DEBUG("Wait for ADDR flag to be set\n");
|
||||
while (!(dev->SR1 & I2C_SR1_ADDR) && !(*err)) {}
|
||||
}
|
||||
|
||||
static inline void _clear_addr(I2C_TypeDef *dev)
|
||||
{
|
||||
dev->SR1;
|
||||
dev->SR2;
|
||||
}
|
||||
|
||||
static inline void _write(I2C_TypeDef *dev, const uint8_t *data, int length, uint8_t *err)
|
||||
{
|
||||
DEBUG("Looping through bytes\n");
|
||||
for (int i = 0; i < length && !(*err); i++) {
|
||||
/* write data to data register */
|
||||
dev->DR = data[i];
|
||||
DEBUG("Written %i byte to data reg, now waiting for DR to be empty again\n", i);
|
||||
/* wait for transfer to finish */
|
||||
while (!(dev->SR1 & I2C_SR1_TXE) && !(*err)) {}
|
||||
DEBUG("DR is now empty again\n");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static inline void _stop(I2C_TypeDef *dev, uint8_t *err)
|
||||
{
|
||||
/* make sure last byte was send */
|
||||
while (!(dev->SR1 & I2C_SR1_BTF) && !(*err)) {}
|
||||
/* send STOP condition */
|
||||
dev->CR1 |= I2C_CR1_STOP;
|
||||
/* wait until transmission is complete */
|
||||
while (dev->SR2 & I2C_SR2_BUSY) {}
|
||||
}
|
||||
|
||||
static inline void i2c_irq_handler(i2c_t i2c_dev, I2C_TypeDef *dev)
|
||||
{
|
||||
unsigned volatile state = dev->SR1;
|
||||
|
||||
/* record and clear errors */
|
||||
err_flag[i2c_dev] = (state >> 8);
|
||||
dev->SR1 &= 0x00ff;
|
||||
|
||||
DEBUG("\n\n### I2C %d ERROR OCCURED ###\n", i2c_dev);
|
||||
DEBUG("status: %08x\n", state);
|
||||
if (state & I2C_SR1_OVR) {
|
||||
DEBUG("OVR\n");
|
||||
}
|
||||
if (state & I2C_SR1_AF) {
|
||||
DEBUG("AF\n");
|
||||
}
|
||||
if (state & I2C_SR1_ARLO) {
|
||||
DEBUG("ARLO\n");
|
||||
}
|
||||
if (state & I2C_SR1_BERR) {
|
||||
DEBUG("BERR\n");
|
||||
}
|
||||
if (state & I2C_SR1_PECERR) {
|
||||
DEBUG("PECERR\n");
|
||||
}
|
||||
if (state & I2C_SR1_TIMEOUT) {
|
||||
DEBUG("TIMEOUT\n");
|
||||
}
|
||||
if (state & I2C_SR1_SMBALERT) {
|
||||
DEBUG("SMBALERT\n");
|
||||
}
|
||||
}
|
||||
|
||||
#if I2C_0_EN
|
||||
void I2C_0_ERR_ISR(void)
|
||||
{
|
||||
i2c_irq_handler(I2C_0, I2C_0_DEV);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if I2C_1_EN
|
||||
void I2C_1_ERR_ISR(void)
|
||||
{
|
||||
i2c_irq_handler(I2C_1, I2C_1_DEV);
|
||||
}
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user