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Merge pull request #14946 from aabadie/pr/boards/stm32f2f4f7_clock_kconfig

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boards/stm32f2/f4/f7: rework clock initialization and configuration
This commit is contained in:
Alexandre Abadie 2020-10-06 16:57:19 +02:00 committed by GitHub
commit 072372a221
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43 changed files with 1466 additions and 935 deletions
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64
boards/common/stm32/include/f2/cfg_clock_120_8_1.h
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/*
* Copyright (C) 2016-2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F2 clock to 120MHz using PLL
*
* @author Vincent Dupont <vincent@otakeys.com>
* @author Aurelien Gonce <aurelien.gonce@altran.fr>
* @author Toon Stegen <toon.stegen@altran.com>
*/
#ifndef F2_CFG_CLOCK_120_8_1_H
#define F2_CFG_CLOCK_120_8_1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 120MHz */
#define CLOCK_CORECLOCK (120000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (120)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (5)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F2_CFG_CLOCK_120_8_1_H */
/** @} */

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boards/common/stm32/include/f2f4f7/cfg_clock_common.h Normal file
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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Base STM32F4 clock configuration
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_COMMON_H
#define F2F4F7_CFG_CLOCK_COMMON_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock common configuration
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(8)
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 0
#endif
#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define CLOCK_LSE (1)
#else
#define CLOCK_LSE (0)
#endif
#define CLOCK_HSI MHZ(16)
#ifdef __cplusplus
}
#endif
#endif /* F2F4F7_CFG_CLOCK_COMMON_H */
/** @} */

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boards/common/stm32/include/f2f4f7/cfg_clock_default_100.h Normal file
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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F4 clock configuration for 100MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_100_H
#define F2F4F7_CFG_CLOCK_DEFAULT_100_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (100MHz)
* @{
*/
/* The following parameters configure a 100MHz system clock with HSE (8MHz or
16MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (4)
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (100)
#else
#define CONFIG_CLOCK_PLL_N (50)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (4)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (4)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1) /* max 100MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(100)
#error "SYSCLK cannot exceed 100MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_100_H */
/** @} */

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boards/common/stm32/include/f2f4f7/cfg_clock_default_120.h Normal file
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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F2/4/7 clock configuration for 120MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_120_H
#define F2F4F7_CFG_CLOCK_DEFAULT_120_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (120MHz)
* @{
*/
/* The following parameters configure a 120MHz system clock with HSE (8MHz or
16MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (4)
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (120)
#else
#define CONFIG_CLOCK_PLL_N (60)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (5)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 30MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2) /* max 60MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(120)
#error "SYSCLK cannot exceed 120MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_120_H */
/** @} */

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boards/common/stm32/include/f2f4f7/cfg_clock_default_168.h Normal file
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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F4 clock configuration for 168MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_168_H
#define F2F4F7_CFG_CLOCK_DEFAULT_168_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (180MHz)
*
* The PLL settings provided here can be used for USB on CPU with a max
* frequency of 180MHz.
* @{
*/
/* The following parameters configure a 168MHz system clock with HSE
(8MHz, 12MHz or 16MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_M (12)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
#define CONFIG_CLOCK_PLL_N (336)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (168)
#else
#define CONFIG_CLOCK_PLL_N (84)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (7)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (0)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(180)
#error "SYSCLK cannot exceed 180MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_168_H */
/** @} */

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boards/common/stm32/include/f2f4f7/cfg_clock_default_180.h Normal file
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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F4 clock configuration for 180MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_180_H
#define F2F4F7_CFG_CLOCK_DEFAULT_180_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (180MHz)
* @{
*/
/* The following parameters configure a 180MHz system clock with HSE (8MHz or
16MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (4)
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (180)
#else
#define CONFIG_CLOCK_PLL_N (90)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (8)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (8)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(180)
#error "SYSCLK cannot exceed 180MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_180_H */
/** @} */

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boards/common/stm32/include/f2f4f7/cfg_clock_default_216.h Normal file
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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F7 clock configuration for 216MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_216_H
#define F2F4F7_CFG_CLOCK_DEFAULT_216_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (216MHz)
* @{
*/
/* The following parameters configure a 216MHz system clock with HSE (8MHz,
16MHz or 25MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_M (25)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (432)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (216)
#else
#define CONFIG_CLOCK_PLL_N (108)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (9)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (8)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(216)
#error "SYSCLK cannot exceed 216MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_216_H */
/** @} */

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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F4 clock configuration for 84MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_84_H
#define F2F4F7_CFG_CLOCK_DEFAULT_84_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (84MHz)
* @{
*/
/* The following parameters configure a 84MHz system clock with HSE (8MHz or
16MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (4)
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (168)
#else
#define CONFIG_CLOCK_PLL_N (84)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (4)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (7)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (0)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 42MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1) /* max 84MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(84)
#error "SYSCLK cannot exceed 84MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_84_H */
/** @} */

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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default STM32F4 clock configuration for 96MHz boards
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_DEFAULT_96_H
#define F2F4F7_CFG_CLOCK_DEFAULT_96_H
#include "f2f4f7/cfg_clock_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock PLL settings (100MHz)
*
* The PLL settings provided here can be used for USB on CPU with a max
* frequency of 100MHz.
* @{
*/
/* The following parameters configure a 96MHz system clock with HSE (8MHz, 16MHz or
25MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLL_M
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_M (25)
#else
#define CONFIG_CLOCK_PLL_M (4)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
#define CONFIG_CLOCK_PLL_N (192)
#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
#define CONFIG_CLOCK_PLL_N (96)
#else
#define CONFIG_CLOCK_PLL_N (48)
#endif
#endif
#ifndef CONFIG_CLOCK_PLL_P
#define CONFIG_CLOCK_PLL_P (2)
#endif
#ifndef CONFIG_CLOCK_PLL_Q
#define CONFIG_CLOCK_PLL_Q (4)
#endif
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (4)
#endif
/** @} */
/**
* @name Clock bus settings (APB1 and APB2)
*/
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */
#endif
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1) /* max 100MHz */
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#include "f2f4f7/cfg_clock_values.h"
#if CLOCK_CORECLOCK > MHZ(100)
#error "SYSCLK cannot exceed 100MHz"
#endif
#endif /* F2F4F7_CFG_CLOCK_DEFAULT_96_H */
/** @} */

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boards/common/stm32/include/f2f4f7/cfg_clock_values.h Normal file
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/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018-2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief STM32F4 clock values definitions
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F2F4F7_CFG_CLOCK_VALUES_H
#define F2F4F7_CFG_CLOCK_VALUES_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock values
* @{
*/
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P)
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q)
#define CLOCK_AHB CLOCK_CORECLOCK
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV)
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F2F4F7_CFG_CLOCK_VALUES_H */
/** @} */

77
boards/common/stm32/include/f4/cfg_clock_100_8_1.h
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@ -1,77 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 100MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F4_CFG_CLOCK_100_8_1_H
#define F4_CFG_CLOCK_100_8_1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (100000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (200)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (0)
/* PLL I2S configuration */
#define CLOCK_ENABLE_PLL_I2S (1)
#define CLOCK_PLL_I2S_SRC (0)
#define CLOCK_PLL_I2S_M (4)
#define CLOCK_PLL_I2S_N (216)
#define CLOCK_PLL_I2S_P (0)
#define CLOCK_PLL_I2S_Q (9)
/* Use alternative source for 48MHz clock */
#define CLOCK_USE_ALT_48MHZ (1)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_100_8_1_H */
/** @} */

62
boards/common/stm32/include/f4/cfg_clock_168_16_0.h
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@ -1,62 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 168MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef F4_CFG_CLOCK_168_16_0_H
#define F4_CFG_CLOCK_168_16_0_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (8)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_168_16_0_H */
/** @} */

41
boards/common/stm32/include/f4/cfg_clock_168_8_0.h
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@ -1,41 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 168MHz using PLL and without LSE
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef F4_CFG_CLOCK_168_8_0_H
#define F4_CFG_CLOCK_168_8_0_H
#include "f4/cfg_clock_168_8_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LSE clock settings
*
* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz)
*/
#define CLOCK_LSE (0)
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_168_8_0_H */
/** @} */

41
boards/common/stm32/include/f4/cfg_clock_168_8_1.h
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@ -1,41 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 168MHz using PLL with LSE
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef F4_CFG_CLOCK_168_8_1_H
#define F4_CFG_CLOCK_168_8_1_H
#include "f4/cfg_clock_168_8_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LSE clock settings
*
* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz)
*/
#define CLOCK_LSE (1)
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_168_8_1_H */
/** @} */

59
boards/common/stm32/include/f4/cfg_clock_168_8_common.h
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@ -1,59 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 168MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef F4_CFG_CLOCK_168_8_COMMON_H
#define F4_CFG_CLOCK_168_8_COMMON_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_168_8_COMMON_H */
/** @} */

72
boards/common/stm32/include/f4/cfg_clock_180_8_1.h
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@ -1,72 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 180MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef F4_CFG_CLOCK_180_8_1_H
#define F4_CFG_CLOCK_180_8_1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (180000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (180)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (0)
/* PLL SAI configuration */
#define CLOCK_ENABLE_PLL_SAI (1)
#define CLOCK_PLL_SAI_M (4)
#define CLOCK_PLL_SAI_N (192)
#define CLOCK_PLL_SAI_P (8)
#define CLOCK_PLL_SAI_Q (0)
/* Use alternative source for 48MHz clock */
#define CLOCK_USE_ALT_48MHZ (1)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_180_8_1_H */
/** @} */

64
boards/common/stm32/include/f4/cfg_clock_84_8_1.h
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@ -1,64 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2018 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 84MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F4_CFG_CLOCK_84_8_1_H
#define F4_CFG_CLOCK_84_8_1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 84MHz */
#define CLOCK_CORECLOCK (84000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (7)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_84_8_1_H */
/** @} */

66
boards/common/stm32/include/f4/cfg_clock_96_25_1.h
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@ -1,66 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2017 OTA keys S.A.
* 2018 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 96MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F4_CFG_CLOCK_96_25_1_H
#define F4_CFG_CLOCK_96_25_1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (25000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (25)
#define CLOCK_PLL_N (384)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (8)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_96_25_1_H */
/** @} */

64
boards/common/stm32/include/f4/cfg_clock_96_8_1.h
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@ -1,64 +0,0 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
* 2018 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 96MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F4_CFG_CLOCK_96_8_1_H
#define F4_CFG_CLOCK_96_8_1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 100MHz */
#define CLOCK_CORECLOCK (96000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (192)
#define CLOCK_PLL_P (4)
#define CLOCK_PLL_Q (8)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_96_8_1_H */
/** @} */

59
boards/common/stm32/include/f7/cfg_clock_216_8_1.h
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@ -1,59 +0,0 @@
/*
* Copyright (C) 2019 Otto-von-Guericke-Universität Magdeburg
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F7 clock to 216MHz and 8MHz HSE using PLL with
* LSE
*
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
#ifndef F7_CFG_CLOCK_216_8_1_H
#define F7_CFG_CLOCK_216_8_1_H
#ifdef __cplusplus
extern "C" {
#endif
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (216)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
#ifdef __cplusplus
}
#endif
#endif /* F7_CFG_CLOCK_216_8_1_H */
/** @} */

10
boards/f4vi1/include/periph_conf.h
View File

@ -21,8 +21,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 16MHz clock */
#define CLOCK_HSE MHZ(16)
#include "periph_cpu.h"
#include "f4/cfg_clock_168_16_0.h"
#include "f2f4f7/cfg_clock_default_168.h"
#ifdef __cplusplus
extern "C" {

10
boards/msbiot/include/periph_conf.h
View File

@ -19,8 +19,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 16MHz clock */
#define CLOCK_HSE MHZ(16)
#include "periph_cpu.h"
#include "f4/cfg_clock_168_16_0.h"
#include "f2f4f7/cfg_clock_default_168.h"
#ifdef __cplusplus
extern "C" {

12
boards/nucleo-f207zg/include/periph_conf.h
View File

@ -21,8 +21,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f2/cfg_clock_120_8_1.h"
#include "f2f4f7/cfg_clock_default_120.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_usb_otg_fs.h"

12
boards/nucleo-f401re/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_84_8_1.h"
#include "f2f4f7/cfg_clock_default_84.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f410rb/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_96_8_1.h"
#include "f2f4f7/cfg_clock_default_96.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f411re/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_96_8_1.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f412zg/include/periph_conf.h
View File

@ -21,8 +21,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_100_8_1.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

12
boards/nucleo-f413zh/include/periph_conf.h
View File

@ -21,8 +21,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_100_8_1.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f429zi/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

12
boards/nucleo-f446re/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f446ze/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

12
boards/nucleo-f722ze/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f7/cfg_clock_216_8_1.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

12
boards/nucleo-f746zg/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f7/cfg_clock_216_8_1.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

12
boards/nucleo-f767zi/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f7/cfg_clock_216_8_1.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

45
boards/pyboard/include/periph_conf.h
View File

@ -21,44 +21,27 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 12MHz clock */
#define CLOCK_HSE MHZ(12)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (12000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name DMA streams configuration
* @{

12
boards/stm32f429i-disc1/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_hs_fs.h"

7
boards/stm32f4discovery/include/periph_conf.h
View File

@ -20,8 +20,13 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_0.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus

45
boards/stm32f723e-disco/include/periph_conf.h
View File

@ -19,7 +19,21 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "cfg_rtt_default.h"
#include "cfg_usb_otg_fs.h"
@ -27,37 +41,6 @@
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (25000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (25)
#define CLOCK_PLL_N (432)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */
/**
* @name Timer configuration
* @{

45
boards/stm32f769i-disco/include/periph_conf.h
View File

@ -19,7 +19,21 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_216.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#include "cfg_usb_otg_fs.h"
@ -28,37 +42,6 @@
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (25000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (25)
#define CLOCK_PLL_N (432)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */
/**
* @name UART configuration
* @{

45
boards/ublox-c030-u201/include/periph_conf.h
View File

@ -19,44 +19,27 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 12MHz clock */
#define CLOCK_HSE MHZ(12)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (12000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name DMA streams configuration
* @{

15
boards/weact-f411ce/include/periph_conf.h
View File

@ -22,8 +22,21 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#include "periph_cpu.h"
#include "f4/cfg_clock_96_25_1.h"
#include "f2f4f7/cfg_clock_default_96.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

4
cpu/stm32/cpu_init.c
View File

@ -154,14 +154,14 @@ void cpu_init(void)
#ifndef CPU_FAM_STM32WB
periph_clk_en(APB1, BIT_APB_PWREN);
#endif
/* initialize the system clock as configured in the periph_conf.h */
stmclk_init_sysclk();
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32L1)
_gpio_init_ain();
#endif
/* initialize the system clock as configured in the periph_conf.h */
stmclk_init_sysclk();
#ifdef MODULE_PERIPH_DMA
/* initialize DMA streams */
dma_init();

606
cpu/stm32/stmclk/stmclk_f2f4f7.c
View File

@ -22,108 +22,444 @@
#include "cpu.h"
#include "stmclk.h"
#include "periph_conf.h"
#include "periph/gpio.h"
/* make sure we have all needed information about the clock configuration */
#ifndef CLOCK_HSE
#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
#endif
#ifndef CLOCK_LSE
#error "Please provide CLOCK_LSE in your board's periph_conf.h"
#endif
#ifndef CLOCK_CORECLOCK
#error "Please provide CLOCK_CORECLOCK in your board's periph_conf.h"
/* PLL configuration */
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
#else
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
#endif
/**
* @name PLL configuration
* @{
*/
/* figure out which input to use */
#if (CLOCK_HSE)
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
/* I2S clock source */
#ifndef CONFIG_PLLI2S_SRC
#define CONFIG_PLLI2S_SRC (0) /* PLLI2S used as I2S clock source */
#else
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
#define CONFIG_PLLI2S_SRC (1) /* Use external I2S source */
#endif
#if defined(CPU_FAM_STM32F2)
#define RCC_PLLCFGR_PLLP_Pos (16U)
#define RCC_PLLCFGR_PLLM_Pos (0U)
#define RCC_PLLCFGR_PLLN_Pos (6U)
#define RCC_PLLCFGR_PLLQ_Pos (24U)
#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
/* Compute the bitfields for the PLL configuration */
#define PLL_M (CONFIG_CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos)
#define PLL_N (CONFIG_CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
#define PLL_P (((CONFIG_CLOCK_PLL_P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
#define PLL_Q (CONFIG_CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
#if defined(RCC_PLLCFGR_PLLR_Pos)
#define PLL_R (CONFIG_CLOCK_PLL_R << RCC_PLLCFGR_PLLR_Pos)
#else
#define PLL_R (0)
#endif
#if (CLOCK_ENABLE_PLL_I2S)
#ifdef RCC_PLLI2SCFGR_PLLI2SM_Pos
#define PLLI2S_M (CLOCK_PLL_I2S_M << RCC_PLLI2SCFGR_PLLI2SM_Pos)
#else
#define PLLI2S_M (0)
#endif
#define PLLI2S_N (CLOCK_PLL_I2S_N << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#ifdef RCC_PLLI2SCFGR_PLLI2SP_Pos
#define PLLI2S_P (((CLOCK_PLL_I2S_P / 2) - 1) << RCC_PLLI2SCFGR_PLLI2SP_Pos)
#else
#define PLLI2S_P (0)
#endif
#ifdef RCC_PLLI2SCFGR_PLLI2SQ_Pos
#define PLLI2S_Q (CLOCK_PLL_I2S_Q << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
#else
#define PLLI2S_Q (0)
#endif
#if defined(RCC_PLLI2SCFGR_PLLI2SR_Pos) && defined(CLOCK_PLL_I2S_R)
#define PLLI2S_R (CLOCK_PLL_I2S_R << RCC_PLLI2SCFGR_PLLI2SR_Pos)
#else
#define PLLI2S_R (0)
#endif
#endif /* CLOCK_ENABLE_PLLI_2S */
/* Select 48MHz clock source between PLLQ, PLLI2SQ or PLLSAIQ. This depends on
the PLL parameters and if not possible on CPU lines which can provide 48MHz
from PLLI2S or PLLSAI */
#if (CLOCK_ENABLE_PLL_SAI)
#ifdef RCC_PLLSAICFGR_PLLSAIN_Pos
#define PLLSAI_M (CLOCK_PLL_SAI_M << RCC_PLLSAICFGR_PLLSAIM_Pos)
/* Determine if PLL is required, even if not used as SYSCLK
This is the case when USB is used in application and PLLQ is configured to
output 48MHz */
#if IS_USED(MODULE_PERIPH_USBDEV) && (CLOCK_PLLQ == MHZ(48))
#define CLOCK_REQUIRE_PLLQ 1
#else
#define PLLSAI_M (0)
#define CLOCK_REQUIRE_PLLQ 0
#endif
#define PLLSAI_N (CLOCK_PLL_SAI_N << RCC_PLLSAICFGR_PLLSAIN_Pos)
#ifdef RCC_PLLSAICFGR_PLLSAIP_Pos
#define PLLSAI_P (((CLOCK_PLL_SAI_P / 2) - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)
#else
#define PLLSAI_P (0)
#endif
#define PLLSAI_Q (CLOCK_PLL_SAI_Q << RCC_PLLSAICFGR_PLLSAIQ_Pos)
#if defined(RCC_PLLSAICFGR_PLLSAIR_Pos) && defined(CLOCK_PLL_SAI_R)
#define PLLSAI_R (CLOCK_PLL_SAI_R << RCC_PLLSAICFGR_PLLSAIR_Pos)
#else
#define PLLSAI_R (0)
#endif
#endif /* CLOCK_ENABLE_PLL_SAI */
/* now we get the actual bitfields */
#define PLL_P (((CLOCK_PLL_P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
#define PLL_M (CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos)
#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
#define PLL_Q (CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
#if defined(RCC_PLLCFGR_PLLR_Pos) && defined(CLOCK_PLL_R)
#define PLL_R (CLOCK_PLL_R << RCC_PLLCFGR_PLLR_Pos)
/* PLLI2S can only be used for USB with F412/F413/F423 lines
PLLI2S is only enabled if no suitable 48MHz clock source can be generated with PLLQ */
#if (defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)) && \
IS_USED(MODULE_PERIPH_USBDEV) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
#define CLOCK_REQUIRE_PLLI2SR 1
#else
#define PLL_R (0)
/* Disable PLLI2S if USB is not required or is required but PLLQ cannot generate 48MHz clock */
#define CLOCK_REQUIRE_PLLI2SR 0
#endif
/** @} */
/**
* @name Deduct the needed flash wait states from the core clock frequency
* @{
*/
#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
/* PLLSAI can only be used for USB with F446/469/479 lines and F7
PLLSAI is only enabled if no suitable 48MHz clock source can be generated with PLLQ */
#if (defined(CPU_LINE_STM32F446xx) || defined(CPU_LINE_STM32F469xx) || \
defined(CPU_LINE_STM32F479xx) || defined(CPU_FAM_STM32F7)) && \
IS_USED(MODULE_PERIPH_USBDEV) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
#define CLOCK_REQUIRE_PLLSAIP 1
#else
/* Disable PLLSAI if USB is not required or is required but PLLQ cannot generate 48MHz clock */
#define CLOCK_REQUIRE_PLLSAIP 0
#endif
#if IS_USED(MODULE_PERIPH_USBDEV) && \
!(IS_ACTIVE(CLOCK_REQUIRE_PLLQ) || \
IS_ACTIVE(CLOCK_REQUIRE_PLLI2SR) || \
IS_ACTIVE(CLOCK_REQUIRE_PLLSAIP))
#error No suitable 48MHz found, USB will not work
#endif
/* PLLI2S configuration: the following parameters configure a 48MHz I2S clock
with HSE (8MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLLI2S_M
/* PLLM factor is not shared with PLLI2S on F412/413/423/446 cpu lines */
#if defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx) || \
defined(CPU_LINE_STM32F446xx)
#define CONFIG_CLOCK_PLLI2S_M (4)
#else
#define CONFIG_CLOCK_PLLI2S_M CONFIG_CLOCK_PLL_M
#endif
#endif
#ifndef CONFIG_CLOCK_PLLI2S_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CONFIG_CLOCK_PLLI2S_N (192)
#else
#define CONFIG_CLOCK_PLLI2S_N (96)
#endif
#endif
#ifndef CONFIG_CLOCK_PLLI2S_P
#define CONFIG_CLOCK_PLLI2S_P (8) /* SPDIF-Rx clock, 48MHz by default */
#endif
#ifndef CONFIG_CLOCK_PLLI2S_Q
#define CONFIG_CLOCK_PLLI2S_Q (8) /* Alternative 48MHz clock (USB) and/or MCO2 PLLI2S */
#endif
#ifndef CONFIG_CLOCK_PLLI2S_R
#define CONFIG_CLOCK_PLLI2S_R (8) /* I2S clock, 48MHz by default */
#endif
#if defined(RCC_PLLI2SCFGR_PLLI2SM_Pos)
#define PLLI2S_M (CONFIG_CLOCK_PLLI2S_M << RCC_PLLI2SCFGR_PLLI2SM_Pos)
#else
#define PLLI2S_M (0)
#endif
#if defined(RCC_PLLI2SCFGR_PLLI2SN_Pos)
#define PLLI2S_N (CONFIG_CLOCK_PLLI2S_N << RCC_PLLI2SCFGR_PLLI2SN_Pos)
#else
#define PLLI2S_N (0)
#endif
#if defined(RCC_PLLI2SCFGR_PLLI2SP_Pos)
#define PLLI2S_P (((CONFIG_CLOCK_PLLI2S_P >> 1) - 1) << RCC_PLLI2SCFGR_PLLI2SP_Pos)
#else
#define PLLI2S_P (0)
#endif
#if defined(RCC_PLLI2SCFGR_PLLI2SQ_Pos)
#define PLLI2S_Q (CONFIG_CLOCK_PLLI2S_Q << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
#else
#define PLLI2S_Q (0)
#endif
#if defined(RCC_PLLI2SCFGR_PLLI2SR_Pos)
#define PLLI2S_R (CONFIG_CLOCK_PLLI2S_R << RCC_PLLI2SCFGR_PLLI2SR_Pos)
#else
#define PLLI2S_R (0)
#endif
/* PLLSAI configuration: the following parameters configure a 48MHz SAI clock
with HSE (8MHz) or HSI (16MHz) as PLL input clock */
#ifndef CONFIG_CLOCK_PLLSAI_M
/* PLLM factor is not shared with PLLSAI on F412/413/423/446 cpu lines */
#if defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx) || \
defined(CPU_LINE_STM32F446xx)
#define CONFIG_CLOCK_PLLSAI_M (4)
#else
#define CONFIG_CLOCK_PLLSAI_M CONFIG_CLOCK_PLL_M
#endif
#endif
#ifndef CONFIG_CLOCK_PLLSAI_N
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CONFIG_CLOCK_PLLSAI_N (192)
#else
#define CONFIG_CLOCK_PLLSAI_N (96)
#endif
#endif
#ifndef CONFIG_CLOCK_PLLSAI_P
#define CONFIG_CLOCK_PLLSAI_P (8) /* Alternative 48MHz clock (USB) */
#endif
#ifndef CONFIG_CLOCK_PLLSAI_Q
#define CONFIG_CLOCK_PLLSAI_Q (8) /* SAI clock, 48MHz by default */
#endif
#ifndef CONFIG_CLOCK_PLLSAI_R
#define CONFIG_CLOCK_PLLSAI_R (8) /* LCD clock, 48MHz by default */
#endif
#if defined(RCC_PLLSAICFGR_PLLSAIM_Pos)
#define PLLSAI_M (CONFIG_CLOCK_PLLSAI_M << RCC_PLLSAICFGR_PLLSAIM_Pos)
#else
#define PLLSAI_M (0)
#endif
#if defined(RCC_PLLSAICFGR_PLLSAIN_Pos)
#define PLLSAI_N (CONFIG_CLOCK_PLLSAI_N << RCC_PLLSAICFGR_PLLSAIN_Pos)
#else
#define PLLSAI_N (0)
#endif
#if defined(RCC_PLLSAICFGR_PLLSAIP_Pos)
#define PLLSAI_P (((CONFIG_CLOCK_PLLSAI_P >> 1) - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)
#else
#define PLLSAI_P (0)
#endif
#if defined(RCC_PLLSAICFGR_PLLSAIQ_Pos)
#define PLLSAI_Q (CONFIG_CLOCK_PLLSAI_Q << RCC_PLLSAICFGR_PLLSAIQ_Pos)
#else
#define PLLSAI_Q (0)
#endif
#if defined(RCC_PLLSAICFGR_PLLSAIR_Pos)
#define PLLSAI_R (CONFIG_CLOCK_PLLSAI_R << RCC_PLLSAICFGR_PLLSAIR_Pos)
#else
#define PLLSAI_R (0)
#endif
/* Configure HLCK and PCLK prescalers */
#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1)
#if CONFIG_CLOCK_APB1_DIV == 1
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
#elif CONFIG_CLOCK_APB1_DIV == 2
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2)
#elif CONFIG_CLOCK_APB1_DIV == 4
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4)
#elif CONFIG_CLOCK_APB1_DIV == 8
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8)
#elif CONFIG_CLOCK_APB1_DIV == 16
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16)
#else
#error "Invalid APB1 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
#endif
#if CONFIG_CLOCK_APB2_DIV == 1
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
#elif CONFIG_CLOCK_APB2_DIV == 2
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2)
#elif CONFIG_CLOCK_APB2_DIV == 4
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4)
#elif CONFIG_CLOCK_APB2_DIV == 8
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8)
#elif CONFIG_CLOCK_APB2_DIV == 16
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16)
#else
#error "Invalid APB2 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
#endif
/* Deduct the needed flash wait states from the core clock frequency */
#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
/* we enable I+D cashes, pre-fetch, and we set the actual number of
* needed flash wait states */
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
#define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
#define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
#elif defined(CPU_FAM_STM32F7)
#define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
#define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
#endif
/* Default is not configure MCO1 */
#ifndef CONFIG_CLOCK_ENABLE_MCO1
#define CONFIG_CLOCK_ENABLE_MCO1 0
#endif
#if !defined(RCC_CFGR_MCO1) && IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1)
#error "stmclk: no MCO1 on this device"
#endif
/* Configure the MCO1 clock source: options are PLL (default), HSE or HSI */
#ifndef CONFIG_CLOCK_MCO1_USE_PLL
#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI)
#define CONFIG_CLOCK_MCO1_USE_PLL 0
#else
#define CONFIG_CLOCK_MCO1_USE_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_CLOCK_MCO1_USE_PLL */
#ifndef CONFIG_CLOCK_MCO1_USE_HSE
#define CONFIG_CLOCK_MCO1_USE_HSE 0
#endif /* CONFIG_CLOCK_MCO1_USE_HSE */
#ifndef CONFIG_CLOCK_MCO1_USE_HSI
#define CONFIG_CLOCK_MCO1_USE_HSI 0
#endif /* CONFIG_CLOCK_MCO1_USE_HSI */
#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL) && \
(IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI))
#error "Cannot use PLL as MCO1 clock source with other clock"
#endif
#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) && \
(IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI))
#error "Cannot use HSE as MCO1 clock source with other clock"
#endif
#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI) && \
(IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL))
#error "Cannot use HSI as MCO1 clock source with other clock"
#endif
#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL)
#define CLOCK_MCO1_SRC (RCC_CFGR_MCO1_1 | RCC_CFGR_MCO1_0)
#elif IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE)
#define CLOCK_MCO1_SRC (RCC_CFGR_MCO1_1)
#elif IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI)
#define CLOCK_MCO1_SRC (0)
#else
#error "Invalid MCO1 clock source selection"
#endif
/* Configure the MCO1 prescaler: options are 1 to 5 */
#ifndef CONFIG_CLOCK_MCO1_PRE
#define CONFIG_CLOCK_MCO1_PRE (1)
#endif
#if CONFIG_CLOCK_MCO1_PRE == 1
#define CLOCK_MCO1_PRE (0)
#elif CONFIG_CLOCK_MCO1_PRE == 2
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2)
#elif CONFIG_CLOCK_MCO1_PRE == 3
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_0)
#elif CONFIG_CLOCK_MCO1_PRE == 4
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1)
#elif CONFIG_CLOCK_MCO1_PRE == 5
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0)
#else
#error "Invalid MCO1 prescaler"
#endif
/* Default is not configure MCO2 */
#ifndef CONFIG_CLOCK_ENABLE_MCO2
#define CONFIG_CLOCK_ENABLE_MCO2 0
#endif
#if !defined(RCC_CFGR_MCO2) && IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2)
#error "stmclk: no MCO2 on this device"
#endif
/* Configure the MCO2 clock source: options are PLL (default), HSE, HSI or LSE */
#ifndef CONFIG_CLOCK_MCO2_USE_PLL
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK)
#define CONFIG_CLOCK_MCO2_USE_PLL 0
#else
#define CONFIG_CLOCK_MCO2_USE_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_CLOCK_MCO2_USE_PLL */
#ifndef CONFIG_CLOCK_MCO2_USE_HSE
#define CONFIG_CLOCK_MCO2_USE_HSE 0
#endif /* CONFIG_CLOCK_MCO2_USE_HSE */
#ifndef CONFIG_CLOCK_MCO2_USE_PLLI2S
#define CONFIG_CLOCK_MCO2_USE_PLLI2S 0
#endif /* CONFIG_CLOCK_MCO2_USE_PLLI2S */
#ifndef CONFIG_CLOCK_MCO2_USE_SYSCLK
#define CONFIG_CLOCK_MCO2_USE_SYSCLK 0
#endif /* CONFIG_CLOCK_MCO2_USE_SYSCLK */
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL) && \
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK))
#error "Cannot use PLL as MCO2 clock source with other clock"
#endif
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) && \
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK))
#error "Cannot use HSE as MCO2 clock source with other clock"
#endif
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) && \
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL) || \
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK))
#error "Cannot use PLLI2S as MCO2 clock source with other clock"
#endif
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK) && \
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL))
#error "Cannot use SYSCLK as MCO2 clock source with other clock"
#endif
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL)
#define CLOCK_MCO2_SRC (RCC_CFGR_MCO2_1 | RCC_CFGR_MCO2_0)
#elif IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE)
#define CLOCK_MCO2_SRC (RCC_CFGR_MCO2_1)
#elif IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S)
#define CLOCK_MCO2_SRC (RCC_CFGR_MCO2_0)
#elif IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK)
#define CLOCK_MCO2_SRC (0)
#else
#error "Invalid MCO2 clock source selection"
#endif
/* Configure the MCO2 prescaler: options are 1 to 5 */
#ifndef CONFIG_CLOCK_MCO2_PRE
#define CONFIG_CLOCK_MCO2_PRE (1)
#endif
#if CONFIG_CLOCK_MCO2_PRE == 1
#define CLOCK_MCO2_PRE (0)
#elif CONFIG_CLOCK_MCO2_PRE == 2
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2)
#elif CONFIG_CLOCK_MCO2_PRE == 3
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)
#elif CONFIG_CLOCK_MCO2_PRE == 4
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)
#elif CONFIG_CLOCK_MCO2_PRE == 5
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
#else
#error "Invalid MCO1 prescaler"
#endif
/* Check whether PLL must be enabled:
- When PLL is used as SYSCLK
- When PLLQ is required
- When PLL is used as input source for MCO1 or MCO2
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_CLOCK_ENABLE_PLLQ) || \
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1) && IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL)) || \
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2) && IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL))
#define CLOCK_ENABLE_PLL 1
#else
#define CLOCK_ENABLE_PLL 0
#endif
/* Check whether HSE must be enabled:
- When HSE is used as SYSCLK
- When PLL is used as SYSCLK and the board provides HSE (since HSE will be
used as PLL input clock)
- When HSE is used input source for MCO1 or MCO2
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
(IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CLOCK_ENABLE_PLL)) || \
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1) && IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE)) || \
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2) && IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE))
#define CLOCK_ENABLE_HSE 1
#else
#define CLOCK_ENABLE_HSE 0
#endif
/* Check whether HSI must be enabled:
- When HSI is used as SYSCLK
- When PLL is used as SYSCLK and the board doesn't provide HSE (since HSI will be
used as PLL input clock)
- When HSI is used input source for MCO1
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
(!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CLOCK_ENABLE_PLL)) || \
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1) && IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE))
#define CLOCK_ENABLE_HSI 1
#else
#define CLOCK_ENABLE_HSI 0
#endif
/* Check whether PLLI2S must be enabled:
- When PLLI2SR is required
- When PLLI2S is used as input clock for MCO2
*/
#if IS_ACTIVE(CLOCK_REQUIRE_PLLI2SR) || \
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2) && IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S))
#define CLOCK_ENABLE_PLLI2S 1
#else
#define CLOCK_ENABLE_PLLI2S 0
#endif
/* Check whether PLLSAI must be enabled */
#if IS_ACTIVE(CLOCK_REQUIRE_PLLSAIP)
#define CLOCK_ENABLE_PLLSAI 1
#else
#define CLOCK_ENABLE_PLLSAI 0
#endif
/** @} */
void stmclk_init_sysclk(void)
{
@ -137,8 +473,7 @@ void stmclk_init_sysclk(void)
/* use HSI as system clock while we do any further configuration and
* configure the AHB and APB clock dividers as configure by the board */
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
CLOCK_APB1_DIV | CLOCK_APB2_DIV);
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
/* Flash config */
@ -147,49 +482,74 @@ void stmclk_init_sysclk(void)
/* disable all active clocks except HSI -> resets the clk configuration */
RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
#if (CLOCK_MCO1_SRC)
#ifndef RCC_CFGR_MCO1
#error "stmclk: no MCO1 on this device"
#endif
RCC->CFGR |= CLOCK_MCO1_SRC | CLOCK_MCO1_PRE;
#endif
#if (CLOCK_MCO2_SRC)
#ifndef RCC_CFGR_MCO2
#error "stmclk: no MCO2 on this device"
#endif
RCC->CFGR |= CLOCK_MCO2_SRC | CLOCK_MCO2_PRE;
if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1)) {
RCC->CFGR |= CLOCK_MCO1_SRC | CLOCK_MCO1_PRE;
/* Configure GPIO pin (PA8/AF0) */
gpio_init(GPIO_PIN(PORT_A, 8), GPIO_OUT);
gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
}
if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2)) {
RCC->CFGR |= CLOCK_MCO2_SRC | CLOCK_MCO2_PRE;
/* Configure GPIO pin (PC9/AF0) */
gpio_init(GPIO_PIN(PORT_C, 9), GPIO_OUT);
gpio_init_af(GPIO_PIN(PORT_C, 9), GPIO_AF0);
}
/* Enable HSE if required */
if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {}
}
/* Enable PLL if required */
if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
/* now we can safely configure and start the PLL */
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q | PLL_R);
RCC->CR |= (RCC_CR_PLLON);
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
}
/* Configure SYSCLK */
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
/* Enable HSE as system clock */
RCC->CFGR |= (RCC_CFGR_SW_HSE);
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
}
else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
/* Enable PLLP as system clock */
RCC->CFGR |= (RCC_CFGR_SW_PLL);
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
}
if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
/* Disable HSI only if not used */
stmclk_disable_hsi();
}
#if defined(RCC_CR_PLLI2SON)
if (IS_ACTIVE(CLOCK_ENABLE_PLLI2S)) {
RCC->PLLI2SCFGR = (CONFIG_PLLI2S_SRC | PLLI2S_M | PLLI2S_N | PLLI2S_P | PLLI2S_Q | PLLI2S_R);
RCC->CR |= (RCC_CR_PLLI2SON);
while (!(RCC->CR & RCC_CR_PLLI2SRDY)) {}
}
#endif
/* if configured, we need to enable the HSE clock now */
#if (CLOCK_HSE)
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {}
#if defined(RCC_CR_PLLSAION)
if (IS_ACTIVE(CLOCK_ENABLE_PLLSAI)) {
RCC->PLLSAICFGR = (PLLSAI_M | PLLSAI_N | PLLSAI_P | PLLSAI_Q | PLLSAI_R);
RCC->CR |= (RCC_CR_PLLSAION);
while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {}
}
#endif
#if CLOCK_USE_ALT_48MHZ
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
#endif
/* now we can safely configure and start the PLL */
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q | PLL_R);
RCC->CR |= (RCC_CR_PLLON);
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
/* now that the PLL is running, we use it as system clock */
RCC->CFGR |= (RCC_CFGR_SW_PLL);
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
stmclk_disable_hsi();
#if (CLOCK_ENABLE_PLL_I2S)
RCC->PLLI2SCFGR = (CLOCK_PLL_I2S_SRC | PLLI2S_M | PLLI2S_N | PLLI2S_P | PLLI2S_Q | PLLI2S_R);
RCC->CR |= (RCC_CR_PLLI2SON);
while (!(RCC->CR & RCC_CR_PLLI2SRDY)) {}
#endif /* CLOCK_ENABLE_PLLI2S */
#if (CLOCK_ENABLE_PLL_SAI)
RCC->PLLSAICFGR = (PLLSAI_M | PLLSAI_N | PLLSAI_P | PLLSAI_Q | PLLSAI_R);
RCC->CR |= (RCC_CR_PLLSAION);
while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {}
#if defined(RCC_DCKCFGR2_CK48MSEL)
if (IS_ACTIVE(CLOCK_ENABLE_PLLI2S) || IS_ACTIVE(CLOCK_ENABLE_PLLSAI)) {
/* Use PLLSAI_P or PLLI2S_Q clock source */
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
}
#endif
irq_restore(is);