cpu: boards: smt32l4: rework clock configuration
This commit is contained in:
Alexandre Abadie
parent
95057a8aef
commit
0745cc4a99
@ -12,14 +12,14 @@
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* @{
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* @{
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*
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*
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* @file
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* @file
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* @brief Configure STM32L4 clock using 80MHz core clock and LSE (32.768kHz)
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* @brief Default STM32L4 clock configuration
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*
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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*/
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#ifndef L4_CFG_CLOCK_80_1_H
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#ifndef L4_CFG_CLOCK_DEFAULT_H
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#define L4_CFG_CLOCK_80_1_H
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#define L4_CFG_CLOCK_DEFAULT_H
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#include "periph_cpu.h"
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#include "periph_cpu.h"
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@ -31,55 +31,153 @@ extern "C" {
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* @name Clock system configuration
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* @name Clock system configuration
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* @{
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* @{
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*/
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*/
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/* 0: no external high speed crystal available
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#ifndef CONFIG_USE_CLOCK_PLL
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* else: actual crystal frequency [in Hz] */
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
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#define CLOCK_HSE (0)
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IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
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#define CONFIG_USE_CLOCK_PLL (0)
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#else
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#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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/* 0: no external low speed crystal available,
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#ifndef CONFIG_USE_CLOCK_MSI
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* 1: external crystal available (always 32.768kHz)
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#define CONFIG_USE_CLOCK_MSI (0)
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*/
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#endif /* CONFIG_USE_CLOCK_MSI */
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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#ifndef CONFIG_USE_CLOCK_HSE
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CONFIG_USE_CLOCK_HSE (0)
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#define CLOCK_MSI_ENABLE (1)
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#endif /* CONFIG_USE_CLOCK_HSE */
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/* 0: disable Hardware auto calibration with LSE
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#ifndef CONFIG_USE_CLOCK_HSI
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
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#define CONFIG_USE_CLOCK_HSI (0)
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* LSE is mandatory for MSI/LSE-trimming to work */
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#endif /* CONFIG_USE_CLOCK_HSI */
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#if CONFIG_USE_CLOCK_PLL && \
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#define CLOCK_CORECLOCK (80000000U)
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(CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
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/* PLL configuration: make sure your values are legit!
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#error "Cannot use PLL as clock source with other clock configurations"
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*
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#endif
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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#if CONFIG_USE_CLOCK_MSI && \
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI || CONFIG_USE_CLOCK_HSE)
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* M: pre-divider, allowed range: [1:8]
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#error "Cannot use MSI as clock source with other clock configurations"
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* N: multiplier, allowed range: [8:86]
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#endif
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* R: post-divider, allowed range: [2,4,6,8]
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*
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#if CONFIG_USE_CLOCK_HSE && \
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* Also the following constraints need to be met:
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI)
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* (PLL_IN / M) -> [4MHz:16MHz]
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#error "Cannot use HSE as clock source with other clock configurations"
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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#endif
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* CORECLOCK -> 80MHz MAX!
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*/
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#if CONFIG_USE_CLOCK_HSI && \
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#define CLOCK_PLL_M (6)
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(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE)
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#define CLOCK_PLL_N (20)
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#error "Cannot use HSI as clock source with other clock configurations"
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#define CLOCK_PLL_R (2)
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#endif
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CONFIG_BOARD_HAS_HSE (0)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#ifndef CLOCK_HSE
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_HSE MHZ(8)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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#endif
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/** @} */
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#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
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#error "HSE clock frequency must be between 4MHz and 48MHz"
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#endif
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE (0)
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#endif
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#if CONFIG_BOARD_HAS_LSE
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#define CLOCK_LSE (1)
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#else
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#define CLOCK_LSE (0)
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#endif
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#define CLOCK_HSI MHZ(16)
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#ifndef CONFIG_CLOCK_MSI
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#define CONFIG_CLOCK_MSI MHZ(48)
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#endif
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/* The following parameters configure a 80MHz system clock with PLL as input clock */
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#ifndef CONFIG_CLOCK_PLL_SRC_MSI
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
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CONFIG_BOARD_HAS_HSE
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#define CONFIG_CLOCK_PLL_SRC_MSI (0)
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#else
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#define CONFIG_CLOCK_PLL_SRC_MSI (1) /* Use MSI an input clock by default */
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#endif
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#endif /* CONFIG_CLOCK_PLL_SRC_MSI */
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#ifndef CONFIG_CLOCK_PLL_SRC_HSE
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#if CONFIG_BOARD_HAS_HSE
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#define CONFIG_CLOCK_PLL_SRC_HSE (1)
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#else
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#define CONFIG_CLOCK_PLL_SRC_HSE (0)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_SRC_HSI
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#define CONFIG_CLOCK_PLL_SRC_HSI (0)
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#endif
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#ifndef CONFIG_CLOCK_PLL_M
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#define CONFIG_CLOCK_PLL_M (6)
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (20)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (2)
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#endif
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#if CONFIG_USE_CLOCK_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#elif CONFIG_USE_CLOCK_HSE
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#if CONFIG_BOARD_HAS_HSE == 0
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif CONFIG_USE_CLOCK_MSI
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
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#elif CONFIG_USE_CLOCK_PLL
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#if CONFIG_CLOCK_PLL_SRC_MSI
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
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#elif CONFIG_CLOCK_PLL_SRC_HSE
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CONFIG_CLOCK_PLL_SRC_ */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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#define CLOCK_CORECLOCK \
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((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
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#ifndef CLOCK_CORECLOCK_MAX
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#define CLOCK_CORECLOCK_MAX MHZ(80)
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#endif
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#if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
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#if CLOCK_CORECLOCK_MAX == MHZ(64)
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#error "SYSCLK cannot exceed 64MHz"
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#elif CLOCK_CORECLOCK_MAX == MHZ(80)
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#error "SYSCLK cannot exceed 80MHz"
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#elif CLOCK_CORECLOCK_MAX == MHZ(120)
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#error "SYSCLK cannot exceed 120MHz"
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#else
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#error "invalid SYSCLK"
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#endif
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#endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* max: 80MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (4)
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 80MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2)
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#endif
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#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 80MHz */
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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#endif /* L4_CFG_CLOCK_80_1_H */
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#endif /* L4_CFG_CLOCK_DEFAULT_H */
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/** @} */
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/** @} */
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@ -27,17 +27,6 @@
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#include "stmclk.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#include "periph_conf.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#if !defined(CLOCK_PLL_M) || !defined(CLOCK_PLL_N) || !defined(CLOCK_PLL_R)
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#error "Please provide the PLL configuration in your board's periph_conf.h"
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#endif
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/* map CMSIS defines not present in stm32wb55xx.h */
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/* map CMSIS defines not present in stm32wb55xx.h */
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#if defined(CPU_FAM_STM32WB)
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#if defined(CPU_FAM_STM32WB)
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#define RCC_PLLCFGR_PLLSRC_HSE (RCC_PLLCFGR_PLLSRC_0 | RCC_PLLCFGR_PLLSRC_1)
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#define RCC_PLLCFGR_PLLSRC_HSE (RCC_PLLCFGR_PLLSRC_0 | RCC_PLLCFGR_PLLSRC_1)
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@ -57,39 +46,39 @@
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* @{
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* @{
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*/
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*/
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/* figure out which input to use */
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#if CONFIG_CLOCK_PLL_SRC_MSI
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
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#elif CONFIG_CLOCK_PLL_SRC_HSE && CONFIG_BOARD_HAS_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#else
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#define PLL_IN (48000000) /* MSI @ 48MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
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#endif
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#endif
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/**check configuration and get the corresponding bitfields */
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/**check configuration and get the corresponding bitfields */
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#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 8)
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#if (CONFIG_CLOCK_PLL_M < 1 || CONFIG_CLOCK_PLL_M > 8)
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#error "PLL configuration: PLL M value is out of range"
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#endif
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_M ((CONFIG_CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 86)
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#if (CONFIG_CLOCK_PLL_N < 8 || CONFIG_CLOCK_PLL_N > 86)
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#error "PLL configuration: PLL N value is out of range"
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#endif
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_N (CONFIG_CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if defined(CPU_FAM_STM32WB)
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#if defined(CPU_FAM_STM32WB)
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#if (CLOCK_PLL_R < 1 || CLOCK_PLL_R > 8)
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#if (CONFIG_CLOCK_PLL_R < 1 || CONFIG_CLOCK_PLL_R > 8)
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#error "PLL configuration: PLL R value is invalid"
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#error "PLL configuration: PLL R value is invalid"
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#else
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#else
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#define PLL_R ((CLOCK_PLL_R - 1)<< RCC_PLLCFGR_PLLR_Pos)
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#define PLL_R ((CONFIG_CLOCK_PLL_R - 1)<< RCC_PLLCFGR_PLLR_Pos)
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#endif
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#endif
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#else
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#else
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#if (CLOCK_PLL_R == 2)
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#if (CONFIG_CLOCK_PLL_R == 2)
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#define PLL_R (0)
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#define PLL_R (0)
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#elif (CLOCK_PLL_R == 4)
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#elif (CONFIG_CLOCK_PLL_R == 4)
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#define PLL_R (RCC_PLLCFGR_PLLR_0)
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#define PLL_R (RCC_PLLCFGR_PLLR_0)
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#elif (CLOCK_PLL_R == 6)
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#elif (CONFIG_CLOCK_PLL_R == 6)
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#define PLL_R (RCC_PLLCFGR_PLLR_1)
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#define PLL_R (RCC_PLLCFGR_PLLR_1)
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#elif (CLOCK_PLL_R == 8)
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#elif (CONFIG_CLOCK_PLL_R == 8)
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#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1)
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#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1)
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#else
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#else
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#error "PLL configuration: PLL R value is invalid"
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#error "PLL configuration: PLL R value is invalid"
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#endif
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#endif
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/** @} */
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/** @} */
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#if CONFIG_CLOCK_MSI == KHZ(100)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_0)
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#elif CONFIG_CLOCK_MSI == KHZ(200)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_1)
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#elif CONFIG_CLOCK_MSI == KHZ(400)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_2)
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#elif CONFIG_CLOCK_MSI == KHZ(800)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_3)
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#elif CONFIG_CLOCK_MSI == MHZ(1)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_4)
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#elif CONFIG_CLOCK_MSI == MHZ(2)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_5)
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#elif CONFIG_CLOCK_MSI == MHZ(4)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_6)
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#elif CONFIG_CLOCK_MSI == MHZ(8)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_7)
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#elif CONFIG_CLOCK_MSI == MHZ(16)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_8)
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#elif CONFIG_CLOCK_MSI == MHZ(24)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_9)
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#elif CONFIG_CLOCK_MSI == MHZ(32)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_10)
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#elif CONFIG_CLOCK_MSI == MHZ(48)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_11)
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#else
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#error "Invalid MSI clock"
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#endif
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#if defined(CPU_FAM_STM32WB)
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#define CLOCK_AHB_DIV (0)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (0)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0)
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (0)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0)
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#elif CONFIG_CLOCK_APB2_DIV == 8
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1)
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#elif CONFIG_CLOCK_APB2_DIV == 16
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||||||
|
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0)
|
||||||
|
#endif
|
||||||
|
#else /* CPU_FAM_STM32L4 */
|
||||||
|
#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1)
|
||||||
|
|
||||||
|
#if CONFIG_CLOCK_APB1_DIV == 1
|
||||||
|
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 2
|
||||||
|
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 4
|
||||||
|
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 8
|
||||||
|
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8)
|
||||||
|
#elif CONFIG_CLOCK_APB1_DIV == 16
|
||||||
|
#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_CLOCK_APB2_DIV == 1
|
||||||
|
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 2
|
||||||
|
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 4
|
||||||
|
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 8
|
||||||
|
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8)
|
||||||
|
#elif CONFIG_CLOCK_APB2_DIV == 16
|
||||||
|
#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16)
|
||||||
|
#endif
|
||||||
|
#endif /* CPU_FAM_STM32WB */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name Deduct the needed flash wait states from the core clock frequency
|
* @name Deduct the needed flash wait states from the core clock frequency
|
||||||
* @{
|
* @{
|
||||||
@ -124,9 +195,9 @@ void stmclk_init_sysclk(void)
|
|||||||
stmclk_enable_hsi();
|
stmclk_enable_hsi();
|
||||||
|
|
||||||
/* use HSI as system clock while we do any further configuration and
|
/* use HSI as system clock while we do any further configuration and
|
||||||
* configure the AHB and APB clock dividers as configure by the board */
|
* configure the AHB and APB clock dividers as configured by the board */
|
||||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
|
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||||
CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
|
||||||
#if defined(CPU_FAM_STM32WB)
|
#if defined(CPU_FAM_STM32WB)
|
||||||
/* Use HSE/2 for radios systems */
|
/* Use HSE/2 for radios systems */
|
||||||
RCC->EXTCFGR = (RCC_EXTCFGR_RFCSS | CLOCK_EXTAHB_DIV);
|
RCC->EXTCFGR = (RCC_EXTCFGR_RFCSS | CLOCK_EXTAHB_DIV);
|
||||||
@ -151,50 +222,80 @@ void stmclk_init_sysclk(void)
|
|||||||
(instead of MSIRANGE in the RCC_CR) */
|
(instead of MSIRANGE in the RCC_CR) */
|
||||||
RCC->CR = (RCC_CR_HSION);
|
RCC->CR = (RCC_CR_HSION);
|
||||||
|
|
||||||
#if (CLOCK_HSE)
|
if (CONFIG_USE_CLOCK_HSE) {
|
||||||
/* if configured, we need to enable the HSE clock now */
|
RCC->CR |= (RCC_CR_HSEON);
|
||||||
RCC->CR |= (RCC_CR_HSEON);
|
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if ((CLOCK_HSE == 0) || CLOCK_MSI_ENABLE)
|
/* Select HSE as system clock and configure the different prescalers */
|
||||||
/* reset clock to MSI with 48MHz, disables all other clocks */
|
RCC->CFGR &= ~RCC_CFGR_SW;
|
||||||
|
RCC->CFGR |= RCC_CFGR_SW_HSE;
|
||||||
|
}
|
||||||
|
else if (CONFIG_USE_CLOCK_MSI) {
|
||||||
#if defined(CPU_FAM_STM32WB)
|
#if defined(CPU_FAM_STM32WB)
|
||||||
RCC->CR |= (RCC_CR_MSIRANGE_11 | RCC_CR_MSION);
|
RCC->CR |= (CLOCK_MSIRANGE | RCC_CR_MSION);
|
||||||
#else
|
#else
|
||||||
RCC->CR |= (RCC_CR_MSIRANGE_11 | RCC_CR_MSION | RCC_CR_MSIRGSEL);
|
RCC->CR |= (CLOCK_MSIRANGE | RCC_CR_MSION | RCC_CR_MSIRGSEL);
|
||||||
#endif
|
#endif
|
||||||
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
||||||
/* select the MSI clock for the 48MHz clock tree (USB, RNG) */
|
|
||||||
RCC->CCIPR = (RCC_CCIPR_CLK48SEL_0 | RCC_CCIPR_CLK48SEL_1);
|
|
||||||
#if (CLOCK_MSI_LSE_PLL && CLOCK_LSE)
|
|
||||||
/* configure the low speed clock domain */
|
|
||||||
stmclk_enable_lfclk();
|
|
||||||
/* now we can enable the MSI PLL mode to enhance accuracy of the MSI*/
|
|
||||||
RCC->CR |= RCC_CR_MSIPLLEN;
|
|
||||||
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
|
||||||
#endif /* (CLOCK_MSI_LSE_PLL && CLOCK_LSE) */
|
|
||||||
#endif /* ((CLOCK_HSE == 0) || CLOCK_MSI_ENABLE) */
|
|
||||||
|
|
||||||
/* now we can safely configure and start the PLL */
|
if (CONFIG_CLOCK_MSI == MHZ(48)) {
|
||||||
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
|
/* select the MSI clock for the 48MHz clock tree (USB, RNG) */
|
||||||
RCC->CR |= (RCC_CR_PLLON);
|
RCC->CCIPR = (RCC_CCIPR_CLK48SEL_0 | RCC_CCIPR_CLK48SEL_1);
|
||||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
}
|
||||||
|
/* Select MSI as system clock and configure the different prescalers */
|
||||||
|
RCC->CFGR = (RCC_CFGR_SW_MSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||||
|
}
|
||||||
|
else if (CONFIG_USE_CLOCK_PLL) {
|
||||||
|
if (CONFIG_BOARD_HAS_HSE && CONFIG_CLOCK_PLL_SRC_HSE) {
|
||||||
|
/* if configured, we need to enable the HSE clock now */
|
||||||
|
RCC->CR |= (RCC_CR_HSEON);
|
||||||
|
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||||
|
}
|
||||||
|
|
||||||
/* now that the PLL is running, we use it as system clock */
|
if (CONFIG_CLOCK_PLL_SRC_MSI) {
|
||||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
/* reset clock to MSI with 48MHz, disables all other clocks */
|
||||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
|
#if defined(CPU_FAM_STM32WB)
|
||||||
|
RCC->CR |= (CLOCK_MSIRANGE | RCC_CR_MSION);
|
||||||
|
#else
|
||||||
|
RCC->CR |= (CLOCK_MSIRANGE | RCC_CR_MSION | RCC_CR_MSIRGSEL);
|
||||||
|
#endif
|
||||||
|
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
||||||
|
|
||||||
|
if (CONFIG_BOARD_HAS_LSE) {
|
||||||
|
/* configure the low speed clock domain */
|
||||||
|
stmclk_enable_lfclk();
|
||||||
|
/* now we can enable the MSI PLL mode to enhance accuracy of the MSI */
|
||||||
|
RCC->CR |= RCC_CR_MSIPLLEN;
|
||||||
|
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (CONFIG_CLOCK_MSI == MHZ(48)) {
|
||||||
|
/* select the MSI clock for the 48MHz clock tree (USB, RNG) */
|
||||||
|
RCC->CCIPR = (RCC_CCIPR_CLK48SEL_0 | RCC_CCIPR_CLK48SEL_1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* now we can safely configure and start the PLL */
|
||||||
|
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
|
||||||
|
RCC->CR |= (RCC_CR_PLLON);
|
||||||
|
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||||
|
|
||||||
|
/* now that the PLL is running, we use it as system clock */
|
||||||
|
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||||
|
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
|
||||||
|
}
|
||||||
|
|
||||||
stmclk_disable_hsi();
|
stmclk_disable_hsi();
|
||||||
irq_restore(is);
|
irq_restore(is);
|
||||||
|
|
||||||
#ifdef MODULE_PERIPH_RTT
|
if (IS_USED(MODULE_PERIPH_RTT)) {
|
||||||
/* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing
|
/* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing
|
||||||
the clock, this is particularly useful after waking up from deep sleep */
|
the clock, this is particularly useful after waking up from deep sleep */
|
||||||
#if CLOCK_LSE
|
if (CONFIG_BOARD_HAS_LSE) {
|
||||||
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1;
|
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1;
|
||||||
#else
|
}
|
||||||
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0;
|
else {
|
||||||
#endif /* CLOCK_LSE */
|
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0;
|
||||||
#endif /* MODULE_PERIPH_RTT */
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user