sam0_common: make RTT implementation common across all sam0 MCUs
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the same RTC peripheral, yet each of them carries it's own copy of the RTT driver. Unify the drivers and move them to sam0_common.
This commit is contained in:
Benjamin Valentin
parent
6afb0603aa
commit
077056b949
224
cpu/sam0_common/periph/rtt.c
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224
cpu/sam0_common/periph/rtt.c
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@ -0,0 +1,224 @@
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/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
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* 2015 FreshTemp, LLC.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @ingroup drivers_periph_rtt
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* @{
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*
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* @file rtt.c
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* @brief Low-level RTT driver implementation
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include "periph/rtt.h"
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#include "board.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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static rtt_cb_t _overflow_cb;
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static void* _overflow_arg;
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static rtt_cb_t _cmp0_cb;
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static void* _cmp0_arg;
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static void _wait_syncbusy(void)
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{
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#ifdef REG_RTC_MODE0_SYNCBUSY
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while (RTC->MODE0.SYNCBUSY.reg) {}
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#else
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while(RTC->MODE0.STATUS.bit.SYNCBUSY) {}
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#endif
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}
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static inline void _rtt_reset(void)
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{
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#ifdef RTC_MODE0_CTRL_SWRST
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RTC->MODE0.CTRL.bit.SWRST = 1;
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while (RTC->MODE0.CTRL.bit.SWRST) {}
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#else
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RTC->MODE0.CTRLA.bit.SWRST = 1;
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while (RTC->MODE0.CTRLA.bit.SWRST) {}
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#endif
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}
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#ifdef CPU_SAMD21
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static void _rtt_clock_setup(void)
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{
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/* RTC uses External 32,768KHz Oscillator because OSC32K isn't accurate
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* enough (p1075/1138). Also keep running in standby. */
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
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SYSCTRL_XOSC32K_EN32K |
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SYSCTRL_XOSC32K_XTALEN |
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SYSCTRL_XOSC32K_STARTUP(6) |
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#if RTT_RUNSTDBY
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SYSCTRL_XOSC32K_RUNSTDBY |
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#endif
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SYSCTRL_XOSC32K_ENABLE;
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/* Setup clock GCLK2 with divider 1 */
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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/* Enable GCLK2 with XOSC32K as source. Use divider without modification
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* and keep running in standby. */
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) |
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GCLK_GENCTRL_GENEN |
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#if RTT_RUNSTDBY
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GCLK_GENCTRL_RUNSTDBY |
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#endif
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GCLK_GENCTRL_SRC_XOSC32K;
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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/* Connect GCLK2 to RTC */
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK2 |
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GCLK_CLKCTRL_CLKEN |
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GCLK_CLKCTRL_ID(RTC_GCLK_ID);
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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}
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/* !CPU_SAMD21 */
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#else
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static void _rtt_clock_setup(void)
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{
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/* Turn on power manager for RTC */
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
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/* set clock source */
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K;
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}
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#endif
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void rtt_init(void)
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{
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_rtt_clock_setup();
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rtt_poweron();
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_rtt_reset();
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/* set 32bit counting mode & enable the RTC */
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#ifdef REG_RTC_MODE0_CTRLA
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RTC->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | RTC_MODE0_CTRLA_ENABLE;
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#else
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RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | RTC_MODE0_CTRL_ENABLE;
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#endif
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_wait_syncbusy();
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/* initially clear flag */
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RTC->MODE0.INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0
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| RTC_MODE0_INTFLAG_OVF;
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NVIC_EnableIRQ(RTC_IRQn);
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DEBUG("%s:%d %u\n", __func__, __LINE__, (unsigned)rtt_get_counter());
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}
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void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
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{
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/* clear overflow cb to avoid race while assigning */
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rtt_clear_overflow_cb();
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/* set callback variables */
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_overflow_cb = cb;
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_overflow_arg = arg;
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/* enable overflow interrupt */
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RTC->MODE0.INTENSET.bit.OVF = 1;
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}
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void rtt_clear_overflow_cb(void)
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{
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/* disable overflow interrupt */
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RTC->MODE0.INTENCLR.bit.OVF = 1;
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}
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uint32_t rtt_get_counter(void)
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{
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_wait_syncbusy();
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return RTC->MODE0.COUNT.reg;
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}
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void rtt_set_counter(uint32_t count)
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{
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RTC->MODE0.COUNT.reg = count;
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_wait_syncbusy();
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}
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uint32_t rtt_get_alarm(void)
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{
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_wait_syncbusy();
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return RTC->MODE0.COMP[0].reg;
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}
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void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
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{
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DEBUG("%s:%d alarm=%u\n", __func__, __LINE__, (unsigned)alarm);
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/* disable interrupt to avoid race */
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rtt_clear_alarm();
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/* setup callback */
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_cmp0_cb = cb;
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_cmp0_arg = arg;
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/* set COM register */
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RTC->MODE0.COMP[0].reg = alarm;
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_wait_syncbusy();
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/* enable compare interrupt and clear flag */
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RTC->MODE0.INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0;
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RTC->MODE0.INTENSET.reg |= RTC_MODE0_INTENSET_CMP0;
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}
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void rtt_clear_alarm(void)
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{
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/* clear compare interrupt */
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RTC->MODE0.INTENCLR.bit.CMP0 = 1;
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}
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void rtt_poweron(void)
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{
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#ifdef MCLK
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC;
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#else
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PM->APBAMASK.reg |= PM_APBAMASK_RTC;
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#endif
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}
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void rtt_poweroff(void)
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{
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#ifdef MCLK
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MCLK->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
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#else
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PM->APBAMASK.reg &= ~PM_APBAMASK_RTC;
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#endif
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}
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void isr_rtc(void)
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{
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if (RTC->MODE0.INTFLAG.bit.OVF) {
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RTC->MODE0.INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
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if (_overflow_cb) {
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_overflow_cb(_overflow_arg);
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}
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}
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if (RTC->MODE0.INTFLAG.bit.CMP0) {
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/* clear flag */
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RTC->MODE0.INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0;
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/* disable interrupt */
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RTC->MODE0.INTENCLR.bit.CMP0 = 1;
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if (_cmp0_cb) {
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_cmp0_cb(_cmp0_arg);
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}
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}
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cortexm_isr_end();
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}
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@ -1,210 +0,0 @@
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/*
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* Copyright (C) 2015 Daniel Krebs
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_samd21
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* @ingroup drivers_periph_rtt
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* @{
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*
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* @file
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* @brief Low-level RTT driver implementation
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*
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* @author Daniel Krebs <github@daniel-krebs.net>
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*
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* @}
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*/
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#include <time.h>
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#include "cpu.h"
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#include "periph/rtt.h"
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#include "periph_conf.h"
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/* if RTT_PRESCALER is not set, then set it to DIV1 */
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#ifndef RTT_PRESCALER
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#define RTT_PRESCALER RTC_MODE0_CTRL_PRESCALER_DIV1
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#endif
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typedef struct {
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rtt_cb_t overflow_cb; /**< called from RTT interrupt on overflow */
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void* overflow_arg; /**< argument passed to overflow callback */
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rtt_cb_t alarm_cb; /**< called from RTT interrupt on alarm */
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void* alarm_arg; /**< argument passen to alarm callback */
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} rtt_state_t;
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static rtt_state_t rtt_callback;
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/**
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* @brief Initialize RTT module
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*
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* The RTT is running at 32768 Hz by default, i.e. @ XOSC32K frequency without
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* divider. There are 2 cascaded dividers in the clock path:
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*
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* - GCLK_GENDIV_DIV(n): between 1 and 31
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* - RTC_MODE0_CTRL_PRESCALER_DIVn: between 1 and 1024, see defines in `component_rtc.h`
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*
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* However the division scheme of GCLK_GENDIV_DIV can be changed by setting
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* GCLK_GENCTRL_DIVSEL:
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*
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* - GCLK_GENCTRL_DIVSEL = 0: Clock divided by GENDIV.DIV (default)
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* - GCLK_GENCTRL_DIVSEL = 1: Clock divided by 2^( GENDIV.DIV + 1 )
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*/
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void rtt_init(void)
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{
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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/* Turn on power manager for RTC */
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PM->APBAMASK.reg |= PM_APBAMASK_RTC;
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/* RTC uses External 32,768KHz Oscillator because OSC32K isn't accurate
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* enough (p1075/1138). Also keep running in standby. */
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
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SYSCTRL_XOSC32K_EN32K |
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SYSCTRL_XOSC32K_XTALEN |
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SYSCTRL_XOSC32K_STARTUP(6) |
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#if RTT_RUNSTDBY
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SYSCTRL_XOSC32K_RUNSTDBY |
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#endif
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SYSCTRL_XOSC32K_ENABLE;
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/* Setup clock GCLK2 with divider 1 */
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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/* Enable GCLK2 with XOSC32K as source. Use divider without modification
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* and keep running in standby. */
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) |
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GCLK_GENCTRL_GENEN |
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#if RTT_RUNSTDBY
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GCLK_GENCTRL_RUNSTDBY |
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#endif
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GCLK_GENCTRL_SRC_XOSC32K;
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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/* Connect GCLK2 to RTC */
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK2 |
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GCLK_CLKCTRL_CLKEN |
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GCLK_CLKCTRL_ID(RTC_GCLK_ID);
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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/* Disable RTC */
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rtt_poweroff();
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/* Reset RTC */
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rtcMode0->CTRL.bit.SWRST = 1;
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while (rtcMode0->STATUS.bit.SYNCBUSY || rtcMode0->CTRL.bit.SWRST) {}
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/* Configure as 32bit counter with no prescaler and no clear on match compare */
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rtcMode0->CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32 |
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RTT_PRESCALER;
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while (rtcMode0->STATUS.bit.SYNCBUSY) {}
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/* Setup interrupt */
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NVIC_EnableIRQ(RTT_IRQ);
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/* Enable RTC */
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rtt_poweron();
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}
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void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
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{
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rtt_callback.overflow_cb = cb;
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rtt_callback.overflow_arg = arg;
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/* Enable Overflow Interrupt and clear flag */
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
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rtcMode0->INTENSET.bit.OVF = 1;
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}
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void rtt_clear_overflow_cb(void)
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{
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/* Disable Overflow Interrupt */
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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rtcMode0->INTENCLR.bit.OVF = 1;
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rtt_callback.overflow_cb = NULL;
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rtt_callback.overflow_arg = NULL;
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}
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uint32_t rtt_get_counter(void)
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{
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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while (rtcMode0->STATUS.bit.SYNCBUSY) {}
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return rtcMode0->COUNT.reg;
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}
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void rtt_set_counter(uint32_t counter)
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{
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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rtcMode0->COUNT.reg = counter;
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while (rtcMode0->STATUS.bit.SYNCBUSY) {}
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}
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void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
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{
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rtt_callback.alarm_cb = cb;
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rtt_callback.alarm_arg = arg;
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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rtcMode0->COMP[0].reg = alarm;
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while (rtcMode0->STATUS.bit.SYNCBUSY) {}
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/* Enable Compare Interrupt and clear flag */
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rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0;
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rtcMode0->INTENSET.bit.CMP0 = 1;
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}
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void rtt_clear_alarm(void)
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{
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/* Disable Compare Interrupt */
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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rtcMode0->INTENCLR.bit.CMP0 = 1;
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rtt_callback.alarm_cb = NULL;
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rtt_callback.alarm_arg = NULL;
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}
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uint32_t rtt_get_alarm(void)
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{
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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return rtcMode0->COMP[0].reg;
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}
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void rtt_poweron(void)
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{
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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rtcMode0->CTRL.bit.ENABLE = 1;
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while (rtcMode0->STATUS.bit.SYNCBUSY) {}
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}
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void rtt_poweroff(void)
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{
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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rtcMode0->CTRL.bit.ENABLE = 0;
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while (rtcMode0->STATUS.bit.SYNCBUSY) {}
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}
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void RTT_ISR(void)
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{
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RtcMode0 *rtcMode0 = &(RTT_DEV);
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uint8_t status = rtcMode0->INTFLAG.reg;
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if ( (status & RTC_MODE0_INTFLAG_CMP0) && (rtt_callback.alarm_cb != NULL) ) {
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rtt_callback.alarm_cb(rtt_callback.alarm_arg);
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rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0;
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}
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if ( (status & RTC_MODE0_INTFLAG_OVF) && (rtt_callback.overflow_cb != NULL) ) {
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rtt_callback.overflow_cb(rtt_callback.overflow_arg);
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rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
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}
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cortexm_isr_end();
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}
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@ -1,149 +0,0 @@
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/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
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* 2015 FreshTemp, LLC.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_saml21
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* @ingroup drivers_periph_rtt
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* @{
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*
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* @file rtt.c
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* @brief Low-level RTT driver implementation
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include "periph/rtt.h"
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#include "board.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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static rtt_cb_t _overflow_cb;
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static void* _overflow_arg;
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static rtt_cb_t _cmp0_cb;
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static void* _cmp0_arg;
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void rtt_init(void)
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{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
/* Turn on power manager for RTC */
|
||||
MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC | MCLK_APBAMASK_OSC32KCTRL;
|
||||
rtt_poweron();
|
||||
|
||||
/* reset */
|
||||
RTC->MODE0.CTRLA.bit.SWRST = 1;
|
||||
while(RTC->MODE0.CTRLA.bit.SWRST) {}
|
||||
|
||||
/* set 32bit counting mode */
|
||||
RTC->MODE0.CTRLA.bit.MODE = 0;
|
||||
|
||||
/* set clock source */
|
||||
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K;
|
||||
|
||||
/* enable */
|
||||
RTC->MODE0.CTRLA.bit.ENABLE = 1;
|
||||
while(RTC->MODE0.SYNCBUSY.bit.ENABLE) {}
|
||||
|
||||
/* initially clear flag */
|
||||
RTC->MODE0.INTFLAG.reg |= RTC_MODE1_INTFLAG_CMP(1 << 0);
|
||||
|
||||
/* enable RTT IRQ */
|
||||
NVIC_EnableIRQ(RTC_IRQn);
|
||||
|
||||
DEBUG("%s:%d %u\n", __func__, __LINE__, (unsigned)rtt_get_counter());
|
||||
}
|
||||
|
||||
void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
/* clear overflow cb to avoid race while assigning */
|
||||
rtt_clear_overflow_cb();
|
||||
|
||||
/* set callback variables */
|
||||
_overflow_cb = cb;
|
||||
_overflow_arg = arg;
|
||||
|
||||
/* enable overflow interrupt */
|
||||
RTC->MODE0.INTENSET.bit.OVF = 1;
|
||||
}
|
||||
void rtt_clear_overflow_cb(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
/* disable overflow interrupt */
|
||||
RTC->MODE0.INTENCLR.bit.OVF = 1;
|
||||
}
|
||||
|
||||
uint32_t rtt_get_counter(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
while (RTC->MODE0.SYNCBUSY.bit.COUNT) {}
|
||||
return RTC->MODE0.COUNT.reg;
|
||||
}
|
||||
|
||||
void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
|
||||
{
|
||||
DEBUG("%s:%d alarm=%u\n", __func__, __LINE__, (unsigned)alarm);
|
||||
|
||||
/* disable interrupt to avoid race */
|
||||
rtt_clear_alarm();
|
||||
|
||||
/* set COM register */
|
||||
while (RTC->MODE0.SYNCBUSY.bit.COMP0) {}
|
||||
RTC->MODE0.COMP[0].reg = alarm;
|
||||
|
||||
/* setup callback */
|
||||
_cmp0_cb = cb;
|
||||
_cmp0_arg = arg;
|
||||
|
||||
/* enable compare interrupt */
|
||||
RTC->MODE0.INTENSET.bit.CMP0 = 1;
|
||||
}
|
||||
|
||||
void rtt_clear_alarm(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
/* clear compare interrupt */
|
||||
RTC->MODE0.INTENCLR.bit.CMP0 = 1;
|
||||
}
|
||||
|
||||
void rtt_poweron(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC;
|
||||
}
|
||||
|
||||
void rtt_poweroff(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
MCLK->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
|
||||
}
|
||||
|
||||
void isr_rtc(void)
|
||||
{
|
||||
if (RTC->MODE0.INTFLAG.bit.OVF) {
|
||||
RTC->MODE0.INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
|
||||
if (_overflow_cb) {
|
||||
_overflow_cb(_overflow_arg);
|
||||
}
|
||||
}
|
||||
if (RTC->MODE0.INTFLAG.bit.CMP0) {
|
||||
/* clear flag */
|
||||
RTC->MODE0.INTFLAG.reg |= RTC_MODE1_INTFLAG_CMP(1 << 0);
|
||||
/* disable interrupt */
|
||||
RTC->MODE0.INTENCLR.bit.CMP0 = 1;
|
||||
if (_cmp0_cb) {
|
||||
_cmp0_cb(_cmp0_arg);
|
||||
}
|
||||
}
|
||||
cortexm_isr_end();
|
||||
}
|
||||
@ -1,147 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
|
||||
* 2015 FreshTemp, LLC.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_saml21
|
||||
* @ingroup drivers_periph_rtt
|
||||
* @{
|
||||
*
|
||||
* @file rtt.c
|
||||
* @brief Low-level RTT driver implementation
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "periph/rtt.h"
|
||||
#include "board.h"
|
||||
|
||||
#define ENABLE_DEBUG 0
|
||||
#include "debug.h"
|
||||
|
||||
static rtt_cb_t _overflow_cb;
|
||||
static void* _overflow_arg;
|
||||
|
||||
static rtt_cb_t _cmp0_cb;
|
||||
static void* _cmp0_arg;
|
||||
|
||||
void rtt_init(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
rtt_poweron();
|
||||
|
||||
/* reset */
|
||||
RTC->MODE0.CTRLA.bit.SWRST = 1;
|
||||
while(RTC->MODE0.CTRLA.bit.SWRST) {}
|
||||
|
||||
/* set 32bit counting mode */
|
||||
RTC->MODE0.CTRLA.bit.MODE = 0;
|
||||
|
||||
/* set clock source */
|
||||
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K;
|
||||
|
||||
/* enable */
|
||||
RTC->MODE0.CTRLA.bit.ENABLE = 1;
|
||||
while(RTC->MODE0.SYNCBUSY.bit.ENABLE) {}
|
||||
|
||||
/* initially clear flag */
|
||||
RTC->MODE0.INTFLAG.reg |= RTC_MODE1_INTFLAG_CMP(1 << 0);
|
||||
|
||||
/* enable RTT IRQ */
|
||||
NVIC_EnableIRQ(RTC_IRQn);
|
||||
|
||||
DEBUG("%s:%d %u\n", __func__, __LINE__, (unsigned)rtt_get_counter());
|
||||
}
|
||||
|
||||
void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
/* clear overflow cb to avoid race while assigning */
|
||||
rtt_clear_overflow_cb();
|
||||
|
||||
/* set callback variables */
|
||||
_overflow_cb = cb;
|
||||
_overflow_arg = arg;
|
||||
|
||||
/* enable overflow interrupt */
|
||||
RTC->MODE0.INTENSET.bit.OVF = 1;
|
||||
}
|
||||
void rtt_clear_overflow_cb(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
/* disable overflow interrupt */
|
||||
RTC->MODE0.INTENCLR.bit.OVF = 1;
|
||||
}
|
||||
|
||||
uint32_t rtt_get_counter(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
while (RTC->MODE0.SYNCBUSY.bit.COUNT) {}
|
||||
return RTC->MODE0.COUNT.reg;
|
||||
}
|
||||
|
||||
void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
|
||||
{
|
||||
DEBUG("%s:%d alarm=%u\n", __func__, __LINE__, (unsigned)alarm);
|
||||
|
||||
/* disable interrupt to avoid race */
|
||||
rtt_clear_alarm();
|
||||
|
||||
/* set COM register */
|
||||
while (RTC->MODE0.SYNCBUSY.bit.COMP0) {}
|
||||
RTC->MODE0.COMP[0].reg = alarm;
|
||||
|
||||
/* setup callback */
|
||||
_cmp0_cb = cb;
|
||||
_cmp0_arg = arg;
|
||||
|
||||
/* enable compare interrupt */
|
||||
RTC->MODE0.INTENSET.bit.CMP0 = 1;
|
||||
}
|
||||
|
||||
void rtt_clear_alarm(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
/* clear compare interrupt */
|
||||
RTC->MODE0.INTENCLR.bit.CMP0 = 1;
|
||||
}
|
||||
|
||||
void rtt_poweron(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC;
|
||||
}
|
||||
|
||||
void rtt_poweroff(void)
|
||||
{
|
||||
DEBUG("%s:%d\n", __func__, __LINE__);
|
||||
MCLK->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
|
||||
}
|
||||
|
||||
void isr_rtc(void)
|
||||
{
|
||||
if (RTC->MODE0.INTFLAG.bit.OVF) {
|
||||
RTC->MODE0.INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
|
||||
if (_overflow_cb) {
|
||||
_overflow_cb(_overflow_arg);
|
||||
}
|
||||
}
|
||||
if (RTC->MODE0.INTFLAG.bit.CMP0) {
|
||||
/* clear flag */
|
||||
RTC->MODE0.INTFLAG.reg |= RTC_MODE1_INTFLAG_CMP(1 << 0);
|
||||
/* disable interrupt */
|
||||
RTC->MODE0.INTENCLR.bit.CMP0 = 1;
|
||||
if (_cmp0_cb) {
|
||||
_cmp0_cb(_cmp0_arg);
|
||||
}
|
||||
}
|
||||
cortexm_isr_end();
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user