diff --git a/boards/ek-lm4f120xl/Makefile b/boards/ek-lm4f120xl/Makefile new file mode 100644 index 0000000000..37891de8e6 --- /dev/null +++ b/boards/ek-lm4f120xl/Makefile @@ -0,0 +1,4 @@ +# tell the Makefile.base which module to build +MODULE = $(BOARD)_base + +include $(RIOTBASE)/Makefile.base diff --git a/boards/ek-lm4f120xl/Makefile.features b/boards/ek-lm4f120xl/Makefile.features new file mode 100644 index 0000000000..af09dfc9af --- /dev/null +++ b/boards/ek-lm4f120xl/Makefile.features @@ -0,0 +1,5 @@ +FEATURES_PROVIDED += cpp +#FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_uart +FEATURES_PROVIDED += periph_cpuid +FEATURES_MCU_GROUP = cortex_m4 diff --git a/boards/ek-lm4f120xl/Makefile.include b/boards/ek-lm4f120xl/Makefile.include new file mode 100644 index 0000000000..ac2f1ceeff --- /dev/null +++ b/boards/ek-lm4f120xl/Makefile.include @@ -0,0 +1,23 @@ +# define the cpu used by the ek-lm4f120xl board +export CPU = lm4f120 +export CPU_MODEL = lm4f120 + +#define the default port depending on the host OS +PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1) + +# setup serial terminal +include $(RIOTBOARD)/Makefile.include.serial + +# this board uses openocd +include $(RIOTBOARD)/Makefile.include.openocd + +# include cortex defaults +include $(RIOTBOARD)/Makefile.include.cortexm_common + +# define stellaris specific flags and includes +export STELLARISWARE = $(RIOTCPU)/stellaris_common/include + +# define build specific options +PART = LM4F120H5QR +export CFLAGS += -I$(STELLARISWARE) -DPART_$(PART) -c -DTARGET_IS_BLIZZARD_RA1 diff --git a/boards/ek-lm4f120xl/board.c b/boards/ek-lm4f120xl/board.c new file mode 100644 index 0000000000..c0f8e1e646 --- /dev/null +++ b/boards/ek-lm4f120xl/board.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * + * @} + */ + +#include "board.h" +static void leds_init(void); + +void board_init(void) +{ + /* initialize the boards LEDs, this is done for debugging purpose */ + leds_init(); + + /* initialize the CPU */ + cpu_init(); +} + +/** + * @brief initialize the boards on-boards LEDS. + */ +static void leds_init(void) +{ + // enable clock for PORTF + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + + //configure the pins as general output + ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3); + // Turn Red led on + ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 2); +} diff --git a/boards/ek-lm4f120xl/cscope.out b/boards/ek-lm4f120xl/cscope.out new file mode 100644 index 0000000000..d0de4ae2bf --- /dev/null +++ b/boards/ek-lm4f120xl/cscope.out @@ -0,0 +1,2457 @@ +cscope 15 $HOME/Documents/LM4F120-XL/Examples/RIOT/boards/ek-lm4f120xl 0000013090 + @board.c + +21  + ~"brd.h +" + +23  + $brd_ +() + +25 + `SupFPU +(); + +26 + `SupClock +( +CLK40 +); + +27 + `ROM_SysCPhEb +( +SYSCTL_PERIPH_GPIOF +); + +29 + `ROM_GPIOPTyGPIOOuut +( +GPIO_PORTF_BASE +, +GPIO_PIN_1 + | +GPIO_PIN_2 + | +GPIO_PIN_3 +); + +30 + `ROM_GPIOPWre +( +GPIO_PORTF_BASE +, +GPIO_PIN_1 + | +GPIO_PIN_2 + | +GPIO_PIN_3 +, 2); + +33 + `u_ +(); + +34 + } +} + +36  + $SupFPU +() + +38 + `ROM_FPUEb +(); + +39 + `ROM_FPULazySckgEb +(); + +40 + } +} + +42  + $SupClock +( +k +) + +44  +k +){ + +45  +CLK80 +: + +46 + `ROM_SysCClockS +( +SYSCTL_SYSDIV_2_5 + | +SYSCTL_USE_PLL + | +SYSCTL_XTAL_16MHZ + | +SYSCTL_OSC_MAIN +); + +48  +CLK50 +: + +49 + `ROM_SysCClockS +( +SYSCTL_SYSDIV_4 + | +SYSCTL_USE_PLL + | +SYSCTL_XTAL_16MHZ + | +SYSCTL_OSC_MAIN +); + +51  +CLK40 +: + +52 + `ROM_SysCClockS +( +SYSCTL_SYSDIV_5 + | +SYSCTL_USE_PLL + | +SYSCTL_XTAL_16MHZ + | +SYSCTL_OSC_MAIN +); + +54  +CLK16 +: + +55 + `ROM_SysCClockS +( +SYSCTL_SYSDIV_1 + | +SYSCTL_USE_PLL + | +SYSCTL_XTAL_16MHZ + | +SYSCTL_OSC_MAIN +); + +58 + `ROM_SysCClockS +( +SYSCTL_SYSDIV_1 + | +SYSCTL_USE_PLL + | +SYSCTL_XTAL_16MHZ + | +SYSCTL_OSC_MAIN +); + +61 + } +} + + @include/board.h + +21 #ide +__BOARD_H + + +22  + #__BOARD_H + + + ) + +24  + ~"u.h +" + +25  + ~"rh/ut.h +" + +26  + ~"rh/tim.h +" + +28 #ifde +__lulus + + +35  + #F_CPU + (40000000UL) + + ) + +36  + #CLK80 + 1 + + ) + +37  + #CLK50 + 2 + + ) + +38  + #CLK40 + 3 + + ) + +39  + #CLK16 + 4 + + ) + +45  + #STDIO + +UART_0 + + + ) + +46  + #STDIO_BAUDRATE + 115200 + + ) + +47  + #STDIO_RX_BUFSIZE + +UART0_BUFSIZE + + + ) + +53  + #HW_TIMER + +TIMER_0 + + + ) + +59  + #LED_GREEN_PIN + 0x08 + + ) + +60  + #LED_BLUE_PIN + 0x04 + + ) + +61  + #LED_RED_PIN + 0x02 + + ) + +63  + #LED_GREEN_ON + +GPIO_PORTF_DATA_R + | +LED_GREEN_PIN + + + ) + +64  + #LED_GREEN_OFF + +GPIO_PORTF_DATA_R + &~( +LED_GREEN_PIN +) + + ) + +65  + #LED_GREEN_TOGGLE + + + ) + +67  + #LED_BLUE_ON + +GPIO_PORTF_DATA_R + | +LED_BLUE_PIN + + + ) + +68  + #LED_BLUE_OFF + +GPIO_PORTF_DATA_R + &~( +LED_BLUE_PIN +) + + ) + +69  + #LED_BLUE_TOGGLE + + + ) + +71  + #LED_RED_ON + +GPIO_PORTF_DATA_R + | +LED_RED_PIN + + + ) + +72  + #LED_RED_OFF + +GPIO_PORTF_DATA_R + &~( +LED_RED_PIN +) + + ) + +73  + #LED_RED_TOGGLE + + + ) + +75  + #TRACE + + `tf +("TRACE %s:%d: %s\n", +__FILE__ +, +__LINE__ +, +__FUNCTION__ +) + + ) + +76  + #VAL_I +( +x + + `tf +(#x ": %d\n",x); + + ) + +77  + #VAL_X +( +x + + `tf +(#x ":0x%X\n", ()x); + + ) + +78  + #VAL_S +( +x + + `tf +(#x ":%s\n", x); + + ) + +83  +brd_ +(); + +84  +SupFPU +(); + +85  +SupClock +( +k +); + +86  +SupStdio +(); + +87  +SupSysTick +(); + +89 #ifde +__lulus + + + @include/periph_conf.h + +19 #ide +__PERIPH_CONF_H + + +20  + #__PERIPH_CONF_H + + + ) + +22 #ifde +__lulus + + +36  + #TIMER_NUMOF + (2U) + + ) + +37  + #TIMER_0_EN + 1 + + ) + +38  + #TIMER_1_EN + 1 + + ) + +39  + #TIMER_IRQ_PRIO + 2 + + ) + +42  + #TIMER_0_DEV + +TIM2 + + + ) + +43  + #TIMER_0_CHANNELS + 2 + + ) + +44  + #TIMER_0_PRESCALER + (39U) + + ) + +45  + #TIMER_0_MAX_VALUE + (0xffffffff) + + ) + +46  + #TIMER_0_CLKEN +(( +RCC +-> +APB1ENR + | +RCC_APB1ENR_TIM2EN +) + + ) + +47  + #TIMER_0_ISR + +TIMER0IHdr + + + ) + +48  + #TIMER_0_IRQ_CHAN + +TIM2_IRQn + + + ) + +51  + #TIMER_1_DEV + +TIM5 + + + ) + +52  + #TIMER_1_CHANNELS + 2 + + ) + +53  + #TIMER_1_PRESCALER + (39U) + + ) + +54  + #TIMER_1_MAX_VALUE + (0xffffffff) + + ) + +55  + #TIMER_1_CLKEN +(( +RCC +-> +APB1ENR + | +RCC_APB1ENR_TIM5EN +) + + ) + +56  + #TIMER_1_ISR + +TIMER1IHdr + + + ) + +57  + #TIMER_1_IRQ_CHAN + +TIM5_IRQn + + + ) + +66  + #UART_NUMOF + (1U) + + ) + +67  + #UART_0_EN + 1 + + ) + +68  + #UART_1_EN + 0 + + ) + +69  + #UART_IRQ_PRIO + 1 + + ) + +70  + #UART_CLK + + `ROM_SysCClockG +( + + ) + +72  + #UART_0_DEV + +UART0_BASE + + + ) + +73  + #UART_0_CLKEN +(( +RCC +-> +APB1ENR + | +RCC_APB1ENR_USART2EN +) + + ) + +74  + #UART_0_CLKDIS +(( +RCC +-> +APB1ENR + &~( +RCC_APB1ENR_USART2EN +)) + + ) + +75  + #UART_0_CLK + (40000000 + + ) + +76  + #UART_0_IRQ_CHAN + +USART2_IRQn + + + ) + +77  + #UART_0_ISR + +UARTIHdr + + + ) + +79  + #UART_0_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOAEN +) + + ) + +80  + #UART_0_PORT + +GPIOA + + + ) + +81  + #UART_0_TX_PIN + +UART_PA1_U0TX + + + ) + +82  + #UART_0_RX_PIN + +UART_PA0_U0RX + + + ) + +83  + #UART_0_AF + 7 + + ) + +88  + #UART_1_DEV + +UART1_BASE + + + ) + +89  + #UART_1_CLKEN +(( +RCC +-> +APB1ENR + | +RCC_APB1ENR_USART3EN +) + + ) + +90  + #UART_1_CLKDIS +(( +RCC +-> +APB1ENR + &~( +RCC_APB1ENR_USART3EN +)) + + ) + +91  + #UART_1_CLK + (40000000 + + ) + +92  + #UART_1_IRQ_CHAN + +USART3_IRQn + + + ) + +93  + #UART_1_ISR + +UART1IHdr + + + ) + +95  + #UART_1_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIODEN +) + + ) + +96  + #UART_1_PORT + +GPIOD + + + ) + +97  + #UART_1_TX_PIN + 8 + + ) + +98  + #UART_1_RX_PIN + 9 + + ) + +99  + #UART_1_AF + 7 + + ) + +106  + #ADC_NUMOF + (2U) + + ) + +107  + #ADC_0_EN + 1 + + ) + +108  + #ADC_1_EN + 1 + + ) + +109  + #ADC_MAX_CHANNELS + 2 + + ) + +112  + #ADC_0_DEV + +ADC0_BASE + + + ) + +113  + #ADC_0_CHANNELS + 2 + + ) + +114  + #ADC_0_CLKEN +(( +RCC +-> +APB2ENR + | +RCC_APB2ENR_ADC1EN +) + + ) + +115  + #ADC_0_CLKDIS +(( +RCC +-> +APB2ENR + &~( +RCC_APB2ENR_ADC1EN +)) + + ) + +116  + #ADC_0_PORT + +GPIO_PORTE_BASE + + + ) + +117  + #ADC_0_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOAEN +) + + ) + +119  + #ADC_0_CH0 + 1 + + ) + +120  + #ADC_0_CH0_PIN + +GPIO_PIN_3 + + + ) + +122  + #ADC_0_CH1 + 4 + + ) + +123  + #ADC_0_CH1_PIN + 4 + + ) + +126  + #ADC_1_DEV + +ADC1_BASE + + + ) + +127  + #ADC_1_CHANNELS + 2 + + ) + +128  + #ADC_1_CLKEN +(( +RCC +-> +APB2ENR + | +RCC_APB2ENR_ADC2EN +) + + ) + +129  + #ADC_1_CLKDIS +(( +RCC +-> +APB2ENR + &~( +RCC_APB2ENR_ADC2EN +)) + + ) + +131  + #ADC_1_PORT + +GPIO_PORTE_BASE + + + ) + +132  + #ADC_1_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOCEN +) + + ) + +134  + #ADC_1_CH0 + 11 + + ) + +135  + #ADC_1_CH0_PIN + +GPIO_PIN_2 + + + ) + +137  + #ADC_1_CH1 + 12 + + ) + +138  + #ADC_1_CH1_PIN + 2 + + ) + +147  + #DAC_NUMOF + (1U) + + ) + +148  + #DAC_0_EN + 1 + + ) + +149  + #DAC_MAX_CHANNELS + 2 + + ) + +152  + #DAC_0_DEV + +DAC + + + ) + +153  + #DAC_0_CHANNELS + 2 + + ) + +154  + #DAC_0_CLKEN +(( +RCC +-> +APB1ENR + |( +RCC_APB1ENR_DACEN +)) + + ) + +155  + #DAC_0_CLKDIS +(( +RCC +-> +APB1ENR + &~( +RCC_APB1ENR_DACEN +)) + + ) + +156  + #DAC_0_PORT + +GPIOA + + + ) + +157  + #DAC_0_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOAEN +) + + ) + +159  + #DAC_0_CH0_PIN + 4 + + ) + +160  + #DAC_0_CH1_PIN + 5 + + ) + +166  + #PWM_NUMOF + (2U) + + ) + +167  + #PWM_0_EN + 1 + + ) + +168  + #PWM_1_EN + 1 + + ) + +169  + #PWM_MAX_CHANNELS + 4 + + ) + +172  + #PWM_0_DEV + +TIM1 + + + ) + +173  + #PWM_0_CHANNELS + 4 + + ) + +174  + #PWM_0_CLK + (168000000U) + + ) + +175  + #PWM_0_CLKEN +(( +RCC +-> +APB2ENR + | +RCC_APB2ENR_TIM1EN +) + + ) + +176  + #PWM_0_CLKDIS +(( +RCC +-> +APB2ENR + &~ +RCC_APB2ENR_TIM1EN +) + + ) + +178  + #PWM_0_PORT + +GPIOE + + + ) + +179  + #PWM_0_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOEEN +) + + ) + +180  + #PWM_0_PIN_CH0 + 9 + + ) + +181  + #PWM_0_PIN_CH1 + 11 + + ) + +182  + #PWM_0_PIN_CH2 + 13 + + ) + +183  + #PWM_0_PIN_CH3 + 14 + + ) + +184  + #PWM_0_PIN_AF + 1 + + ) + +187  + #PWM_1_DEV + +TIM3 + + + ) + +188  + #PWM_1_CHANNELS + 3 + + ) + +189  + #PWM_1_CLK + (84000000U) + + ) + +190  + #PWM_1_CLKEN +(( +RCC +-> +APB1ENR + | +RCC_APB1ENR_TIM3EN +) + + ) + +191  + #PWM_1_CLKDIS +(( +RCC +-> +APB1ENR + &~ +RCC_APB1ENR_TIM3EN +) + + ) + +193  + #PWM_1_PORT + +GPIOB + + + ) + +194  + #PWM_1_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOBEN +) + + ) + +195  + #PWM_1_PIN_CH0 + 4 + + ) + +196  + #PWM_1_PIN_CH1 + 5 + + ) + +197  + #PWM_1_PIN_CH2 + 0 + + ) + +198  + #PWM_1_PIN_CH3 + 1 + + ) + +199  + #PWM_1_PIN_AF + 2 + + ) + +206  + #RANDOM_NUMOF + (1U) + + ) + +213  + #SPI_NUMOF + (2U) + + ) + +214  + #SPI_0_EN + 1 + + ) + +215  + #SPI_1_EN + 1 + + ) + +216  + #SPI_IRQ_PRIO + 1 + + ) + +219  + #SPI_0_DEV + +SPI1 + + + ) + +220  + #SPI_0_CLKEN +(( +RCC +-> +APB2ENR + | +RCC_APB2ENR_SPI1EN +) + + ) + +221  + #SPI_0_CLKDIS +(( +RCC +-> +APB2ENR + &~ +RCC_APB2ENR_SPI1EN +) + + ) + +222  + #SPI_0_BUS_DIV + 1 + + ) + +223  + #SPI_0_IRQ + +SPI1_IRQn + + + ) + +224  + #SPI_0_IRQ_HANDLER + +i_i1 + + + ) + +226  + #SPI_0_SCK_PORT + +GPIOA + + + ) + +227  + #SPI_0_SCK_PIN + 5 + + ) + +228  + #SPI_0_SCK_AF + 5 + + ) + +229  + #SPI_0_SCK_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOAEN +) + + ) + +230  + #SPI_0_MISO_PORT + +GPIOA + + + ) + +231  + #SPI_0_MISO_PIN + 6 + + ) + +232  + #SPI_0_MISO_AF + 5 + + ) + +233  + #SPI_0_MISO_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOAEN +) + + ) + +234  + #SPI_0_MOSI_PORT + +GPIOA + + + ) + +235  + #SPI_0_MOSI_PIN + 7 + + ) + +236  + #SPI_0_MOSI_AF + 5 + + ) + +237  + #SPI_0_MOSI_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOAEN +) + + ) + +240  + #SPI_1_DEV + +SPI2 + + + ) + +241  + #SPI_1_CLKEN +(( +RCC +-> +APB1ENR + | +RCC_APB1ENR_SPI2EN +) + + ) + +242  + #SPI_1_CLKDIS +(( +RCC +-> +APB1ENR + &~ +RCC_APB1ENR_SPI2EN +) + + ) + +243  + #SPI_1_BUS_DIV + 0 + + ) + +244  + #SPI_1_IRQ + +SPI2_IRQn + + + ) + +245  + #SPI_1_IRQ_HANDLER + +i_i2 + + + ) + +247  + #SPI_1_SCK_PORT + +GPIOB + + + ) + +248  + #SPI_1_SCK_PIN + 13 + + ) + +249  + #SPI_1_SCK_AF + 5 + + ) + +250  + #SPI_1_SCK_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOBEN +) + + ) + +251  + #SPI_1_MISO_PORT + +GPIOB + + + ) + +252  + #SPI_1_MISO_PIN + 14 + + ) + +253  + #SPI_1_MISO_AF + 5 + + ) + +254  + #SPI_1_MISO_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOBEN +) + + ) + +255  + #SPI_1_MOSI_PORT + +GPIOB + + + ) + +256  + #SPI_1_MOSI_PIN + 15 + + ) + +257  + #SPI_1_MOSI_AF + 5 + + ) + +258  + #SPI_1_MOSI_PORT_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOBEN +) + + ) + +265  + #I2C_NUMOF + (1U) + + ) + +266  + #I2C_0_EN + 1 + + ) + +267  + #I2C_IRQ_PRIO + 1 + + ) + +268  + #I2C_APBCLK + (42000000U) + + ) + +271  + #I2C_0_DEV + +I2C1 + + + ) + +272  + #I2C_0_CLKEN +(( +RCC +-> +APB1ENR + | +RCC_APB1ENR_I2C1EN +) + + ) + +273  + #I2C_0_CLKDIS +(( +RCC +-> +APB1ENR + &~( +RCC_APB1ENR_I2C1EN +)) + + ) + +274  + #I2C_0_EVT_IRQ + +I2C1_EV_IRQn + + + ) + +275  + #I2C_0_EVT_ISR + +i_i2c1_ev + + + ) + +276  + #I2C_0_ERR_IRQ + +I2C1_ER_IRQn + + + ) + +277  + #I2C_0_ERR_ISR + +i_i2c1_ + + + ) + +279  + #I2C_0_SCL_PORT + +GPIOB + + + ) + +280  + #I2C_0_SCL_PIN + 6 + + ) + +281  + #I2C_0_SCL_AF + 4 + + ) + +282  + #I2C_0_SCL_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOBEN +) + + ) + +283  + #I2C_0_SDA_PORT + +GPIOB + + + ) + +284  + #I2C_0_SDA_PIN + 7 + + ) + +285  + #I2C_0_SDA_AF + 4 + + ) + +286  + #I2C_0_SDA_CLKEN +(( +RCC +-> +AHB1ENR + | +RCC_AHB1ENR_GPIOBEN +) + + ) + +293  + #GPIO_NUMOF + 12 + + ) + +294  + #GPIO_0_EN + 1 + + ) + +295  + #GPIO_1_EN + 1 + + ) + +296  + #GPIO_2_EN + 1 + + ) + +297  + #GPIO_3_EN + 1 + + ) + +298  + #GPIO_4_EN + 1 + + ) + +299  + #GPIO_5_EN + 1 + + ) + +300  + #GPIO_6_EN + 1 + + ) + +301  + #GPIO_7_EN + 1 + + ) + +302  + #GPIO_8_EN + 1 + + ) + +303  + #GPIO_9_EN + 1 + + ) + +304  + #GPIO_10_EN + 1 + + ) + +305  + #GPIO_11_EN + 1 + + ) + +306  + #GPIO_IRQ_PRIO + 1 + + ) + +309  + #GPIO_IRQ_0 + +GPIO_0 + + + ) + +310  + #GPIO_IRQ_1 + +GPIO_2 + + + ) + +311  + #GPIO_IRQ_2 + +GPIO_3 + + + ) + +312  + #GPIO_IRQ_3 + +GPIO_4 + + + ) + +313  + #GPIO_IRQ_4 + +GPIO_5 + + + ) + +314  + #GPIO_IRQ_5 + +GPIO_6 + + + ) + +315  + #GPIO_IRQ_6 + +GPIO_7 + + + ) + +316  + #GPIO_IRQ_7 + +GPIO_8 + + + ) + +317  + #GPIO_IRQ_8 + +GPIO_9 + + + ) + +318  + #GPIO_IRQ_9 + +GPIO_10 + + + ) + +319  + #GPIO_IRQ_10 + +GPIO_11 + + + ) + +320  + #GPIO_IRQ_11 + -1 + + ) + +321  + #GPIO_IRQ_12 + -1 + + ) + +322  + #GPIO_IRQ_13 + -1 + + ) + +323  + #GPIO_IRQ_14 + -1 + + ) + +324  + #GPIO_IRQ_15 + -1 + + ) + +327  + #GPIO_0_PORT + +GPIOA + + + ) + +328  + #GPIO_0_PIN + 0 + + ) + +329  + #GPIO_0_CLK + 0 + + ) + +330  + #GPIO_0_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[0] | +SYSCFG_EXTICR1_EXTI0_PA +) + + ) + +331  + #GPIO_0_IRQ + +EXTI0_IRQn + + + ) + +333  + #GPIO_1_PORT + +GPIOE + + + ) + +334  + #GPIO_1_PIN + 0 + + ) + +335  + #GPIO_1_CLK + 4 + + ) + +336  + #GPIO_1_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[0] | +SYSCFG_EXTICR1_EXTI0_PE +) + + ) + +337  + #GPIO_1_IRQ + +EXTI0_IRQn + + + ) + +339  + #GPIO_2_PORT + +GPIOE + + + ) + +340  + #GPIO_2_PIN + 1 + + ) + +341  + #GPIO_2_CLK + 4 + + ) + +342  + #GPIO_2_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[0] | +SYSCFG_EXTICR1_EXTI1_PE +) + + ) + +343  + #GPIO_2_IRQ + +EXTI1_IRQn + + + ) + +345  + #GPIO_3_PORT + +GPIOE + + + ) + +346  + #GPIO_3_PIN + 2 + + ) + +347  + #GPIO_3_CLK + 4 + + ) + +348  + #GPIO_3_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[0] | +SYSCFG_EXTICR1_EXTI2_PE +) + + ) + +349  + #GPIO_3_IRQ + +EXTI2_IRQn + + + ) + +351  + #GPIO_4_PORT + +GPIOE + + + ) + +352  + #GPIO_4_PIN + 3 + + ) + +353  + #GPIO_4_CLK + 4 + + ) + +354  + #GPIO_4_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[0] | +SYSCFG_EXTICR1_EXTI3_PE +) + + ) + +355  + #GPIO_4_IRQ + +EXTI3_IRQn + + + ) + +357  + #GPIO_5_PORT + +GPIOD + + + ) + +358  + #GPIO_5_PIN + 4 + + ) + +359  + #GPIO_5_CLK + 3 + + ) + +360  + #GPIO_5_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[1] | +SYSCFG_EXTICR2_EXTI4_PD +) + + ) + +361  + #GPIO_5_IRQ + +EXTI4_IRQn + + + ) + +363  + #GPIO_6_PORT + +GPIOD + + + ) + +364  + #GPIO_6_PIN + 5 + + ) + +365  + #GPIO_6_CLK + 3 + + ) + +366  + #GPIO_6_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[1] | +SYSCFG_EXTICR2_EXTI5_PD +) + + ) + +367  + #GPIO_6_IRQ + +EXTI9_5_IRQn + + + ) + +369  + #GPIO_7_PORT + +GPIOD + + + ) + +370  + #GPIO_7_PIN + 6 + + ) + +371  + #GPIO_7_CLK + 3 + + ) + +372  + #GPIO_7_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[1] | +SYSCFG_EXTICR2_EXTI6_PD +) + + ) + +373  + #GPIO_7_IRQ + +EXTI9_5_IRQn + + + ) + +375  + #GPIO_8_PORT + +GPIOD + + + ) + +376  + #GPIO_8_PIN + 7 + + ) + +377  + #GPIO_8_CLK + 3 + + ) + +378  + #GPIO_8_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[1] | +SYSCFG_EXTICR2_EXTI7_PD +) + + ) + +379  + #GPIO_8_IRQ + +EXTI9_5_IRQn + + + ) + +381  + #GPIO_9_PORT + +GPIOA + + + ) + +382  + #GPIO_9_PIN + 8 + + ) + +383  + #GPIO_9_CLK + 0 + + ) + +384  + #GPIO_9_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[2] | +SYSCFG_EXTICR3_EXTI8_PA +) + + ) + +385  + #GPIO_9_IRQ + +EXTI9_5_IRQn + + + ) + +387  + #GPIO_10_PORT + +GPIOA + + + ) + +388  + #GPIO_10_PIN + 9 + + ) + +389  + #GPIO_10_CLK + 0 + + ) + +390  + #GPIO_10_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[2] | +SYSCFG_EXTICR3_EXTI9_PA +) + + ) + +391  + #GPIO_10_IRQ + +EXTI9_5_IRQn + + + ) + +393  + #GPIO_11_PORT + +GPIOD + + + ) + +394  + #GPIO_11_PIN + 10 + + ) + +395  + #GPIO_11_CLK + 3 + + ) + +396  + #GPIO_11_EXTI_CFG +(( +SYSCFG +-> +EXTICR +[2] | +SYSCFG_EXTICR3_EXTI10_PD +) + + ) + +397  + #GPIO_11_IRQ + +EXTI15_10_IRQn + + + ) + +400 #ifde +__lulus + + + @ +1 +. +1 +/usr/include +3 +46 +board.c +include/board.h +include/periph_conf.h diff --git a/boards/ek-lm4f120xl/dist/openocd.cfg b/boards/ek-lm4f120xl/dist/openocd.cfg new file mode 100644 index 0000000000..2378772a1e --- /dev/null +++ b/boards/ek-lm4f120xl/dist/openocd.cfg @@ -0,0 +1 @@ +source [find board/ek-lm4f120xl.cfg] diff --git a/boards/ek-lm4f120xl/include/board.h b/boards/ek-lm4f120xl/include/board.h new file mode 100644 index 0000000000..b584363103 --- /dev/null +++ b/boards/ek-lm4f120xl/include/board.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + */ + +#ifndef __BOARD_H +#define __BOARD_H + +#include "cpu.h" +#include "periph/uart.h" +#include "periph/timer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Define the boards stdio + * @{ + */ +#define STDIO UART_0 +#define STDIO_BAUDRATE 115200 +#define STDIO_RX_BUFSIZE UART0_BUFSIZE +/** @} */ + +/** + * @name Assign the hardware timer + */ +#define HW_TIMER TIMER_0 + +/** + * @name Macros for controlling the on-board LEDs. + * @{ + */ +#define LED_GREEN_PIN 0x08 +#define LED_BLUE_PIN 0x04 +#define LED_RED_PIN 0x02 + +#define LED_GREEN_ON GPIO_PORTF_DATA_R |= LED_GREEN_PIN +#define LED_GREEN_OFF GPIO_PORTF_DATA_R &= ~(LED_GREEN_PIN) +#define LED_GREEN_TOGGLE /* not available */ + +#define LED_BLUE_ON GPIO_PORTF_DATA_R |= LED_BLUE_PIN +#define LED_BLUE_OFF GPIO_PORTF_DATA_R &= ~(LED_BLUE_PIN) +#define LED_BLUE_TOGGLE /* not available */ + +#define LED_RED_ON GPIO_PORTF_DATA_R |= LED_RED_PIN +#define LED_RED_OFF GPIO_PORTF_DATA_R &= ~(LED_RED_PIN) +#define LED_RED_TOGGLE /* not available */ +/* @} */ +#define TRACE printf("TRACE %s:%d: %s\n", __FILE__, __LINE__, __FUNCTION__) +#define VAL_I(x) printf(#x ": %d\n",x); +#define VAL_X(x) printf(#x ":0x%X\n", (unsigned int)x); +#define VAL_S(x) printf(#x ":%s\n", x); + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +extern void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /** __BOARD_H */ +/** @} */ diff --git a/boards/ek-lm4f120xl/include/periph_conf.h b/boards/ek-lm4f120xl/include/periph_conf.h new file mode 100644 index 0000000000..b98972af13 --- /dev/null +++ b/boards/ek-lm4f120xl/include/periph_conf.h @@ -0,0 +1,385 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_ek-lm4f120xl + * @{ + * + * @file + * @name Peripheral MCU configuration for the ek-lm4f120xl board + * + * @author Rakendra Thapa + */ + +#ifndef __PERIPH_CONF_H +#define __PERIPH_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Timer configuration + * @{ + */ +#define TIMER_NUMOF (2U) +#define TIMER_0_EN 1 +#define TIMER_1_EN 0 +#define TIMER_IRQ_PRIO 1 + +/* Timer 0 configuration */ +//#define TIMER_0_DEV TIM2 +#define TIMER_0_CHANNELS 2 +#define TIMER_0_PRESCALER (39U) +#define TIMER_0_MAX_VALUE (0xffffffff) +#define TIMER_0_ISR WTIMER0IntHandler +#define TIMER_0_IRQ_CHAN Timer0A_IRQn + +/* Timer 1 configuration */ +#define TIMER_1_CHANNELS 2 +#define TIMER_1_PRESCALER (39U) +#define TIMER_1_MAX_VALUE (0xffffffff) +#define TIMER_1_ISR TIMER1IntHandler +#define TIMER_1_IRQ_CHAN Timer1A_IRQn +/** @} */ + +/** @} */ + +/** + * @name UART configuration + * @{ + */ +#define UART_NUMOF (1U) +#define UART_0_EN 1 +#define UART_1_EN 0 +#define UART_IRQ_PRIO 1 +#define UART_CLK ROM_SysCtlClockGet() /*RT clock runs with 40MHz */ +/* UART 0 device configuration */ +#define UART_0_DEV UART0_BASE +#define UART_0_CLK (40000000) /* UART clock runs with 42MHz (F_CPU / 4) */ +#define UART_0_IRQ_CHAN UART0_IRQn +#define UART_0_ISR UARTIntHandler +/* UART 0 pin configuration */ +#define UART_0_PORT GPIOA +#define UART_0_TX_PIN UART_PA1_U0TX +#define UART_0_RX_PIN UART_PA0_U0RX +#define UART_0_AF 7 + + + +/* UART 1 device configuration */ +#define UART_1_DEV UART1_BASE +#define UART_1_CLK (40000000) /* UART clock runs with 40MHz (F_CPU / 4) */ +#define UART_1_IRQ_CHAN UART1_IRQn +#define UART_1_ISR UART1IntHandler +/* UART 1 pin configuration */ +#define UART_1_PORT GPIOD +#define UART_1_TX_PIN 8 +#define UART_1_RX_PIN 9 +#define UART_1_AF 7 +/** @} */ + +/** + * @name ADC configuration + * @{ + */ +#define ADC_NUMOF (2U) +#define ADC_0_EN 1 +#define ADC_1_EN 1 +#define ADC_MAX_CHANNELS 2 +/** @} */ +/* ADC 0 configuration */ +#define ADC_0_DEV ADC0_BASE +#define ADC_0_CHANNELS 2 +#define ADC_0_PORT GPIO_PORTE_BASE +/* ADC 0 channel 0 pin config */ +#define ADC_0_CH0 1 +#define ADC_0_CH0_PIN GPIO_PIN_3 +/* ADC 0 channel 1 pin config */ +#define ADC_0_CH1 4 +#define ADC_0_CH1_PIN 4 + +/* ADC 1 configuration */ +#define ADC_1_DEV ADC1_BASE +#define ADC_1_CHANNELS 2 + +#define ADC_1_PORT GPIO_PORTE_BASE +#define ADC_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN) +/* ADC 1 channel 0 pin config */ +#define ADC_1_CH0 11 +#define ADC_1_CH0_PIN GPIO_PIN_2 +/* ADC 1 channel 1 pin config */ +#define ADC_1_CH1 12 +#define ADC_1_CH1_PIN 2 +/** @} */ + + + +/** + * @name DAC configuration + * @{ + */ +#define DAC_NUMOF (1U) +#define DAC_0_EN 1 +#define DAC_MAX_CHANNELS 2 + +/* DAC 0 configuration */ +#define DAC_0_DEV DAC +#define DAC_0_CHANNELS 2 +#define DAC_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) +#define DAC_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define DAC_0_PORT GPIOA +#define DAC_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) +/* DAC 0 channel config */ +#define DAC_0_CH0_PIN 4 +#define DAC_0_CH1_PIN 5 + +/** + * @name PWM configuration + * @{ + */ +#define PWM_NUMOF (2U) +#define PWM_0_EN 1 +#define PWM_1_EN 1 +#define PWM_MAX_CHANNELS 4 + +/* PWM 0 device configuration */ +#define PWM_0_DEV TIM1 +#define PWM_0_CHANNELS 4 +#define PWM_0_CLK (168000000U) +#define PWM_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_TIM1EN) +#define PWM_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN) +/* PWM 0 pin configuration */ +#define PWM_0_PORT GPIOE +#define PWM_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN) +#define PWM_0_PIN_CH0 9 +#define PWM_0_PIN_CH1 11 +#define PWM_0_PIN_CH2 13 +#define PWM_0_PIN_CH3 14 +#define PWM_0_PIN_AF 1 + +/* PWM 1 device configuration */ +#define PWM_1_DEV TIM3 +#define PWM_1_CHANNELS 3 +#define PWM_1_CLK (84000000U) +#define PWM_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN) +#define PWM_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN) +/* PWM 1 pin configuration */ +#define PWM_1_PORT GPIOB +#define PWM_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN) +#define PWM_1_PIN_CH0 4 +#define PWM_1_PIN_CH1 5 +#define PWM_1_PIN_CH2 0 +#define PWM_1_PIN_CH3 1 +#define PWM_1_PIN_AF 2 +/** @} */ + +/** + * @name Random Number Generator configuration + * @{ + */ +#define RANDOM_NUMOF (1U) +/** @} */ + +/** + * @name SPI configuration + * @{ + */ +#define SPI_NUMOF (2U) +#define SPI_0_EN 1 +#define SPI_1_EN 1 +#define SPI_IRQ_PRIO 1 + +/* SPI 0 device config */ +#define SPI_0_DEV SPI1 +#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN) +#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN) +#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */ +#define SPI_0_IRQ SPI1_IRQn +#define SPI_0_IRQ_HANDLER isr_spi1 +/* SPI 0 pin configuration */ +#define SPI_0_SCK_PORT GPIOA +#define SPI_0_SCK_PIN 5 +#define SPI_0_SCK_AF 5 +#define SPI_0_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) +#define SPI_0_MISO_PORT GPIOA +#define SPI_0_MISO_PIN 6 +#define SPI_0_MISO_AF 5 +#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) +#define SPI_0_MOSI_PORT GPIOA +#define SPI_0_MOSI_PIN 7 +#define SPI_0_MOSI_AF 5 +#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) + +/* SPI 1 device config */ +#define SPI_1_DEV SPI2 +#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN) +#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN) +#define SPI_1_BUS_DIV 0 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */ +#define SPI_1_IRQ SPI2_IRQn +#define SPI_1_IRQ_HANDLER isr_spi2 +/* SPI 1 pin configuration */ +#define SPI_1_SCK_PORT GPIOB +#define SPI_1_SCK_PIN 13 +#define SPI_1_SCK_AF 5 +#define SPI_1_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN) +#define SPI_1_MISO_PORT GPIOB +#define SPI_1_MISO_PIN 14 +#define SPI_1_MISO_AF 5 +#define SPI_1_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN) +#define SPI_1_MOSI_PORT GPIOB +#define SPI_1_MOSI_PIN 15 +#define SPI_1_MOSI_AF 5 +#define SPI_1_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN) +/** @} */ + +/** + * @name I2C configuration + * @{ + */ +#define I2C_NUMOF (1U) +#define I2C_0_EN 1 +#define I2C_IRQ_PRIO 1 +#define I2C_APBCLK (42000000U) + +/* I2C 0 device configuration */ +#define I2C_0_DEV I2C1 +#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN) +#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define I2C_0_EVT_IRQ I2C1_EV_IRQn +#define I2C_0_EVT_ISR isr_i2c1_ev +#define I2C_0_ERR_IRQ I2C1_ER_IRQn +#define I2C_0_ERR_ISR isr_i2c1_er +/* I2C 0 pin configuration */ +#define I2C_0_SCL_PORT GPIOB +#define I2C_0_SCL_PIN 6 +#define I2C_0_SCL_AF 4 +#define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN) +#define I2C_0_SDA_PORT GPIOB +#define I2C_0_SDA_PIN 7 +#define I2C_0_SDA_AF 4 +#define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN) +/** @} */ + +/** + * @name GPIO configuration + * @{ + */ +#define GPIO_NUMOF 12 +#define GPIO_0_EN 1 +#define GPIO_1_EN 1 +#define GPIO_2_EN 1 +#define GPIO_3_EN 1 +#define GPIO_4_EN 1 +#define GPIO_5_EN 1 +#define GPIO_6_EN 1 +#define GPIO_7_EN 1 +#define GPIO_8_EN 1 +#define GPIO_9_EN 1 +#define GPIO_10_EN 1 +#define GPIO_11_EN 1 +#define GPIO_IRQ_PRIO 1 + +/* IRQ config */ +#define GPIO_IRQ_0 GPIO_0 /* alternatively GPIO_1 could be used here */ +#define GPIO_IRQ_1 GPIO_2 +#define GPIO_IRQ_2 GPIO_3 +#define GPIO_IRQ_3 GPIO_4 +#define GPIO_IRQ_4 GPIO_5 +#define GPIO_IRQ_5 GPIO_6 +#define GPIO_IRQ_6 GPIO_7 +#define GPIO_IRQ_7 GPIO_8 +#define GPIO_IRQ_8 GPIO_9 +#define GPIO_IRQ_9 GPIO_10 +#define GPIO_IRQ_10 GPIO_11 +#define GPIO_IRQ_11 -1/* not configured */ +#define GPIO_IRQ_12 -1/* not configured */ +#define GPIO_IRQ_13 -1/* not configured */ +#define GPIO_IRQ_14 -1/* not configured */ +#define GPIO_IRQ_15 -1/* not configured */ + +/* GPIO channel 0 config */ +#define GPIO_0_PORT GPIOA /* Used for user button 1 */ +#define GPIO_0_PIN 0 +#define GPIO_0_CLK 0 /* 0: PORT A, 1: B ... */ +#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA) +#define GPIO_0_IRQ EXTI0_IRQn +/* GPIO channel 1 config */ +#define GPIO_1_PORT GPIOE /* LIS302DL INT1 */ +#define GPIO_1_PIN 0 +#define GPIO_1_CLK 4 +#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PE) +#define GPIO_1_IRQ EXTI0_IRQn +/* GPIO channel 2 config */ +#define GPIO_2_PORT GPIOE /* LIS302DL INT2 */ +#define GPIO_2_PIN 1 +#define GPIO_2_CLK 4 +#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PE) +#define GPIO_2_IRQ EXTI1_IRQn +/* GPIO channel 3 config */ +#define GPIO_3_PORT GPIOE +#define GPIO_3_PIN 2 +#define GPIO_3_CLK 4 +#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PE) +#define GPIO_3_IRQ EXTI2_IRQn +/* GPIO channel 4 config */ +#define GPIO_4_PORT GPIOE /* LIS302DL CS */ +#define GPIO_4_PIN 3 +#define GPIO_4_CLK 4 +#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PE) +#define GPIO_4_IRQ EXTI3_IRQn +/* GPIO channel 5 config */ +#define GPIO_5_PORT GPIOD /* CS43L22 RESET */ +#define GPIO_5_PIN 4 +#define GPIO_5_CLK 3 +#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PD) +#define GPIO_5_IRQ EXTI4_IRQn +/* GPIO channel 6 config */ +#define GPIO_6_PORT GPIOD /* LD8 */ +#define GPIO_6_PIN 5 +#define GPIO_6_CLK 3 +#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PD) +#define GPIO_6_IRQ EXTI9_5_IRQn +/* GPIO channel 7 config */ +#define GPIO_7_PORT GPIOD +#define GPIO_7_PIN 6 +#define GPIO_7_CLK 3 +#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PD) +#define GPIO_7_IRQ EXTI9_5_IRQn +/* GPIO channel 8 config */ +#define GPIO_8_PORT GPIOD +#define GPIO_8_PIN 7 +#define GPIO_8_CLK 3 +#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PD) +#define GPIO_8_IRQ EXTI9_5_IRQn +/* GPIO channel 9 config */ +#define GPIO_9_PORT GPIOA +#define GPIO_9_PIN 8 +#define GPIO_9_CLK 0 +#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA) +#define GPIO_9_IRQ EXTI9_5_IRQn +/* GPIO channel 10 config */ +#define GPIO_10_PORT GPIOA /* LD7 */ +#define GPIO_10_PIN 9 +#define GPIO_10_CLK 0 +#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA) +#define GPIO_10_IRQ EXTI9_5_IRQn +/* GPIO channel 11 config */ +#define GPIO_11_PORT GPIOD +#define GPIO_11_PIN 10 +#define GPIO_11_CLK 3 +#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PD) +#define GPIO_11_IRQ EXTI15_10_IRQn +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PERIPH_CONF_H */ +/** @} */ diff --git a/boards/ek-lm4f120xl/tags b/boards/ek-lm4f120xl/tags new file mode 100644 index 0000000000..ed25e41e65 --- /dev/null +++ b/boards/ek-lm4f120xl/tags @@ -0,0 +1,295 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ +!_TAG_PROGRAM_NAME Exuberant Ctags // +!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ +!_TAG_PROGRAM_VERSION 5.9~svn20110310 // +ADC_0_CH0 include/periph_conf.h 119;" d +ADC_0_CH0_PIN include/periph_conf.h 120;" d +ADC_0_CH1 include/periph_conf.h 122;" d +ADC_0_CH1_PIN include/periph_conf.h 123;" d +ADC_0_CHANNELS include/periph_conf.h 113;" d +ADC_0_CLKDIS include/periph_conf.h 115;" d +ADC_0_CLKEN include/periph_conf.h 114;" d +ADC_0_DEV include/periph_conf.h 112;" d +ADC_0_EN include/periph_conf.h 107;" d +ADC_0_PORT include/periph_conf.h 116;" d +ADC_0_PORT_CLKEN include/periph_conf.h 117;" d +ADC_1_CH0 include/periph_conf.h 134;" d +ADC_1_CH0_PIN include/periph_conf.h 135;" d +ADC_1_CH1 include/periph_conf.h 137;" d +ADC_1_CH1_PIN include/periph_conf.h 138;" d +ADC_1_CHANNELS include/periph_conf.h 127;" d +ADC_1_CLKDIS include/periph_conf.h 129;" d +ADC_1_CLKEN include/periph_conf.h 128;" d +ADC_1_DEV include/periph_conf.h 126;" d +ADC_1_EN include/periph_conf.h 108;" d +ADC_1_PORT include/periph_conf.h 131;" d +ADC_1_PORT_CLKEN include/periph_conf.h 132;" d +ADC_MAX_CHANNELS include/periph_conf.h 109;" d +ADC_NUMOF include/periph_conf.h 106;" d +CLK16 include/board.h 39;" d +CLK40 include/board.h 38;" d +CLK50 include/board.h 37;" d +CLK80 include/board.h 36;" d +DAC_0_CH0_PIN include/periph_conf.h 159;" d +DAC_0_CH1_PIN include/periph_conf.h 160;" d +DAC_0_CHANNELS include/periph_conf.h 153;" d +DAC_0_CLKDIS include/periph_conf.h 155;" d +DAC_0_CLKEN include/periph_conf.h 154;" d +DAC_0_DEV include/periph_conf.h 152;" d +DAC_0_EN include/periph_conf.h 148;" d +DAC_0_PORT include/periph_conf.h 156;" d +DAC_0_PORT_CLKEN include/periph_conf.h 157;" d +DAC_MAX_CHANNELS include/periph_conf.h 149;" d +DAC_NUMOF include/periph_conf.h 147;" d +F_CPU include/board.h 35;" d +GPIO_0_CLK include/periph_conf.h 329;" d +GPIO_0_EN include/periph_conf.h 294;" d +GPIO_0_EXTI_CFG include/periph_conf.h 330;" d +GPIO_0_IRQ include/periph_conf.h 331;" d +GPIO_0_PIN include/periph_conf.h 328;" d +GPIO_0_PORT include/periph_conf.h 327;" d +GPIO_10_CLK include/periph_conf.h 389;" d +GPIO_10_EN include/periph_conf.h 304;" d +GPIO_10_EXTI_CFG include/periph_conf.h 390;" d +GPIO_10_IRQ include/periph_conf.h 391;" d +GPIO_10_PIN include/periph_conf.h 388;" d +GPIO_10_PORT include/periph_conf.h 387;" d +GPIO_11_CLK include/periph_conf.h 395;" d +GPIO_11_EN include/periph_conf.h 305;" d +GPIO_11_EXTI_CFG include/periph_conf.h 396;" d +GPIO_11_IRQ include/periph_conf.h 397;" d +GPIO_11_PIN include/periph_conf.h 394;" d +GPIO_11_PORT include/periph_conf.h 393;" d +GPIO_1_CLK include/periph_conf.h 335;" d +GPIO_1_EN include/periph_conf.h 295;" d +GPIO_1_EXTI_CFG include/periph_conf.h 336;" d +GPIO_1_IRQ include/periph_conf.h 337;" d +GPIO_1_PIN include/periph_conf.h 334;" d +GPIO_1_PORT include/periph_conf.h 333;" d +GPIO_2_CLK include/periph_conf.h 341;" d +GPIO_2_EN include/periph_conf.h 296;" d +GPIO_2_EXTI_CFG include/periph_conf.h 342;" d +GPIO_2_IRQ include/periph_conf.h 343;" d +GPIO_2_PIN include/periph_conf.h 340;" d +GPIO_2_PORT include/periph_conf.h 339;" d +GPIO_3_CLK include/periph_conf.h 347;" d +GPIO_3_EN include/periph_conf.h 297;" d +GPIO_3_EXTI_CFG include/periph_conf.h 348;" d +GPIO_3_IRQ include/periph_conf.h 349;" d +GPIO_3_PIN include/periph_conf.h 346;" d +GPIO_3_PORT include/periph_conf.h 345;" d +GPIO_4_CLK include/periph_conf.h 353;" d +GPIO_4_EN include/periph_conf.h 298;" d +GPIO_4_EXTI_CFG include/periph_conf.h 354;" d +GPIO_4_IRQ include/periph_conf.h 355;" d +GPIO_4_PIN include/periph_conf.h 352;" d +GPIO_4_PORT include/periph_conf.h 351;" d +GPIO_5_CLK include/periph_conf.h 359;" d +GPIO_5_EN include/periph_conf.h 299;" d +GPIO_5_EXTI_CFG include/periph_conf.h 360;" d +GPIO_5_IRQ include/periph_conf.h 361;" d +GPIO_5_PIN include/periph_conf.h 358;" d +GPIO_5_PORT include/periph_conf.h 357;" d +GPIO_6_CLK include/periph_conf.h 365;" d +GPIO_6_EN include/periph_conf.h 300;" d +GPIO_6_EXTI_CFG include/periph_conf.h 366;" d +GPIO_6_IRQ include/periph_conf.h 367;" d +GPIO_6_PIN include/periph_conf.h 364;" d +GPIO_6_PORT include/periph_conf.h 363;" d +GPIO_7_CLK include/periph_conf.h 371;" d +GPIO_7_EN include/periph_conf.h 301;" d +GPIO_7_EXTI_CFG include/periph_conf.h 372;" d +GPIO_7_IRQ include/periph_conf.h 373;" d +GPIO_7_PIN include/periph_conf.h 370;" d +GPIO_7_PORT include/periph_conf.h 369;" d +GPIO_8_CLK include/periph_conf.h 377;" d +GPIO_8_EN include/periph_conf.h 302;" d +GPIO_8_EXTI_CFG include/periph_conf.h 378;" d +GPIO_8_IRQ include/periph_conf.h 379;" d +GPIO_8_PIN include/periph_conf.h 376;" d +GPIO_8_PORT include/periph_conf.h 375;" d +GPIO_9_CLK include/periph_conf.h 383;" d +GPIO_9_EN include/periph_conf.h 303;" d +GPIO_9_EXTI_CFG include/periph_conf.h 384;" d +GPIO_9_IRQ include/periph_conf.h 385;" d +GPIO_9_PIN include/periph_conf.h 382;" d +GPIO_9_PORT include/periph_conf.h 381;" d +GPIO_IRQ_0 include/periph_conf.h 309;" d +GPIO_IRQ_1 include/periph_conf.h 310;" d +GPIO_IRQ_10 include/periph_conf.h 319;" d +GPIO_IRQ_11 include/periph_conf.h 320;" d +GPIO_IRQ_12 include/periph_conf.h 321;" d +GPIO_IRQ_13 include/periph_conf.h 322;" d +GPIO_IRQ_14 include/periph_conf.h 323;" d +GPIO_IRQ_15 include/periph_conf.h 324;" d +GPIO_IRQ_2 include/periph_conf.h 311;" d +GPIO_IRQ_3 include/periph_conf.h 312;" d +GPIO_IRQ_4 include/periph_conf.h 313;" d +GPIO_IRQ_5 include/periph_conf.h 314;" d +GPIO_IRQ_6 include/periph_conf.h 315;" d +GPIO_IRQ_7 include/periph_conf.h 316;" d +GPIO_IRQ_8 include/periph_conf.h 317;" d +GPIO_IRQ_9 include/periph_conf.h 318;" d +GPIO_IRQ_PRIO include/periph_conf.h 306;" d +GPIO_NUMOF include/periph_conf.h 293;" d +HW_TIMER include/board.h 53;" d +I2C_0_CLKDIS include/periph_conf.h 273;" d +I2C_0_CLKEN include/periph_conf.h 272;" d +I2C_0_DEV include/periph_conf.h 271;" d +I2C_0_EN include/periph_conf.h 266;" d +I2C_0_ERR_IRQ include/periph_conf.h 276;" d +I2C_0_ERR_ISR include/periph_conf.h 277;" d +I2C_0_EVT_IRQ include/periph_conf.h 274;" d +I2C_0_EVT_ISR include/periph_conf.h 275;" d +I2C_0_SCL_AF include/periph_conf.h 281;" d +I2C_0_SCL_CLKEN include/periph_conf.h 282;" d +I2C_0_SCL_PIN include/periph_conf.h 280;" d +I2C_0_SCL_PORT include/periph_conf.h 279;" d +I2C_0_SDA_AF include/periph_conf.h 285;" d +I2C_0_SDA_CLKEN include/periph_conf.h 286;" d +I2C_0_SDA_PIN include/periph_conf.h 284;" d +I2C_0_SDA_PORT include/periph_conf.h 283;" d +I2C_APBCLK include/periph_conf.h 268;" d +I2C_IRQ_PRIO include/periph_conf.h 267;" d +I2C_NUMOF include/periph_conf.h 265;" d +LED_BLUE_OFF include/board.h 68;" d +LED_BLUE_ON include/board.h 67;" d +LED_BLUE_PIN include/board.h 60;" d +LED_BLUE_TOGGLE include/board.h 69;" d +LED_GREEN_OFF include/board.h 64;" d +LED_GREEN_ON include/board.h 63;" d +LED_GREEN_PIN include/board.h 59;" d +LED_GREEN_TOGGLE include/board.h 65;" d +LED_RED_OFF include/board.h 72;" d +LED_RED_ON include/board.h 71;" d +LED_RED_PIN include/board.h 61;" d +LED_RED_TOGGLE include/board.h 73;" d +MODULE Makefile /^MODULE = $(BOARD)_base$/;" m +PWM_0_CHANNELS include/periph_conf.h 173;" d +PWM_0_CLK include/periph_conf.h 174;" d +PWM_0_CLKDIS include/periph_conf.h 176;" d +PWM_0_CLKEN include/periph_conf.h 175;" d +PWM_0_DEV include/periph_conf.h 172;" d +PWM_0_EN include/periph_conf.h 167;" d +PWM_0_PIN_AF include/periph_conf.h 184;" d +PWM_0_PIN_CH0 include/periph_conf.h 180;" d +PWM_0_PIN_CH1 include/periph_conf.h 181;" d +PWM_0_PIN_CH2 include/periph_conf.h 182;" d +PWM_0_PIN_CH3 include/periph_conf.h 183;" d +PWM_0_PORT include/periph_conf.h 178;" d +PWM_0_PORT_CLKEN include/periph_conf.h 179;" d +PWM_1_CHANNELS include/periph_conf.h 188;" d +PWM_1_CLK include/periph_conf.h 189;" d +PWM_1_CLKDIS include/periph_conf.h 191;" d +PWM_1_CLKEN include/periph_conf.h 190;" d +PWM_1_DEV include/periph_conf.h 187;" d +PWM_1_EN include/periph_conf.h 168;" d +PWM_1_PIN_AF include/periph_conf.h 199;" d +PWM_1_PIN_CH0 include/periph_conf.h 195;" d +PWM_1_PIN_CH1 include/periph_conf.h 196;" d +PWM_1_PIN_CH2 include/periph_conf.h 197;" d +PWM_1_PIN_CH3 include/periph_conf.h 198;" d +PWM_1_PORT include/periph_conf.h 193;" d +PWM_1_PORT_CLKEN include/periph_conf.h 194;" d +PWM_MAX_CHANNELS include/periph_conf.h 169;" d +PWM_NUMOF include/periph_conf.h 166;" d +RANDOM_NUMOF include/periph_conf.h 206;" d +SPI_0_BUS_DIV include/periph_conf.h 222;" d +SPI_0_CLKDIS include/periph_conf.h 221;" d +SPI_0_CLKEN include/periph_conf.h 220;" d +SPI_0_DEV include/periph_conf.h 219;" d +SPI_0_EN include/periph_conf.h 214;" d +SPI_0_IRQ include/periph_conf.h 223;" d +SPI_0_IRQ_HANDLER include/periph_conf.h 224;" d +SPI_0_MISO_AF include/periph_conf.h 232;" d +SPI_0_MISO_PIN include/periph_conf.h 231;" d +SPI_0_MISO_PORT include/periph_conf.h 230;" d +SPI_0_MISO_PORT_CLKEN include/periph_conf.h 233;" d +SPI_0_MOSI_AF include/periph_conf.h 236;" d +SPI_0_MOSI_PIN include/periph_conf.h 235;" d +SPI_0_MOSI_PORT include/periph_conf.h 234;" d +SPI_0_MOSI_PORT_CLKEN include/periph_conf.h 237;" d +SPI_0_SCK_AF include/periph_conf.h 228;" d +SPI_0_SCK_PIN include/periph_conf.h 227;" d +SPI_0_SCK_PORT include/periph_conf.h 226;" d +SPI_0_SCK_PORT_CLKEN include/periph_conf.h 229;" d +SPI_1_BUS_DIV include/periph_conf.h 243;" d +SPI_1_CLKDIS include/periph_conf.h 242;" d +SPI_1_CLKEN include/periph_conf.h 241;" d +SPI_1_DEV include/periph_conf.h 240;" d +SPI_1_EN include/periph_conf.h 215;" d +SPI_1_IRQ include/periph_conf.h 244;" d +SPI_1_IRQ_HANDLER include/periph_conf.h 245;" d +SPI_1_MISO_AF include/periph_conf.h 253;" d +SPI_1_MISO_PIN include/periph_conf.h 252;" d +SPI_1_MISO_PORT include/periph_conf.h 251;" d +SPI_1_MISO_PORT_CLKEN include/periph_conf.h 254;" d +SPI_1_MOSI_AF include/periph_conf.h 257;" d +SPI_1_MOSI_PIN include/periph_conf.h 256;" d +SPI_1_MOSI_PORT include/periph_conf.h 255;" d +SPI_1_MOSI_PORT_CLKEN include/periph_conf.h 258;" d +SPI_1_SCK_AF include/periph_conf.h 249;" d +SPI_1_SCK_PIN include/periph_conf.h 248;" d +SPI_1_SCK_PORT include/periph_conf.h 247;" d +SPI_1_SCK_PORT_CLKEN include/periph_conf.h 250;" d +SPI_IRQ_PRIO include/periph_conf.h 216;" d +SPI_NUMOF include/periph_conf.h 213;" d +STDIO include/board.h 45;" d +STDIO_BAUDRATE include/board.h 46;" d +STDIO_RX_BUFSIZE include/board.h 47;" d +SetupClock board.c /^void SetupClock(int clk)$/;" f +SetupFPU board.c /^void SetupFPU(void)$/;" f +TIMER_0_CHANNELS include/periph_conf.h 43;" d +TIMER_0_CLKEN include/periph_conf.h 46;" d +TIMER_0_DEV include/periph_conf.h 42;" d +TIMER_0_EN include/periph_conf.h 37;" d +TIMER_0_IRQ_CHAN include/periph_conf.h 48;" d +TIMER_0_ISR include/periph_conf.h 47;" d +TIMER_0_MAX_VALUE include/periph_conf.h 45;" d +TIMER_0_PRESCALER include/periph_conf.h 44;" d +TIMER_1_CHANNELS include/periph_conf.h 52;" d +TIMER_1_CLKEN include/periph_conf.h 55;" d +TIMER_1_DEV include/periph_conf.h 51;" d +TIMER_1_EN include/periph_conf.h 38;" d +TIMER_1_IRQ_CHAN include/periph_conf.h 57;" d +TIMER_1_ISR include/periph_conf.h 56;" d +TIMER_1_MAX_VALUE include/periph_conf.h 54;" d +TIMER_1_PRESCALER include/periph_conf.h 53;" d +TIMER_IRQ_PRIO include/periph_conf.h 39;" d +TIMER_NUMOF include/periph_conf.h 36;" d +TRACE include/board.h 75;" d +UART_0_AF include/periph_conf.h 83;" d +UART_0_CLK include/periph_conf.h 75;" d +UART_0_CLKDIS include/periph_conf.h 74;" d +UART_0_CLKEN include/periph_conf.h 73;" d +UART_0_DEV include/periph_conf.h 72;" d +UART_0_EN include/periph_conf.h 67;" d +UART_0_IRQ_CHAN include/periph_conf.h 76;" d +UART_0_ISR include/periph_conf.h 77;" d +UART_0_PORT include/periph_conf.h 80;" d +UART_0_PORT_CLKEN include/periph_conf.h 79;" d +UART_0_RX_PIN include/periph_conf.h 82;" d +UART_0_TX_PIN include/periph_conf.h 81;" d +UART_1_AF include/periph_conf.h 99;" d +UART_1_CLK include/periph_conf.h 91;" d +UART_1_CLKDIS include/periph_conf.h 90;" d +UART_1_CLKEN include/periph_conf.h 89;" d +UART_1_DEV include/periph_conf.h 88;" d +UART_1_EN include/periph_conf.h 68;" d +UART_1_IRQ_CHAN include/periph_conf.h 92;" d +UART_1_ISR include/periph_conf.h 93;" d +UART_1_PORT include/periph_conf.h 96;" d +UART_1_PORT_CLKEN include/periph_conf.h 95;" d +UART_1_RX_PIN include/periph_conf.h 98;" d +UART_1_TX_PIN include/periph_conf.h 97;" d +UART_CLK include/periph_conf.h 70;" d +UART_IRQ_PRIO include/periph_conf.h 69;" d +UART_NUMOF include/periph_conf.h 66;" d +VAL_I include/board.h 76;" d +VAL_S include/board.h 78;" d +VAL_X include/board.h 77;" d +__BOARD_H include/board.h 22;" d +__PERIPH_CONF_H include/periph_conf.h 20;" d +board_init board.c /^void board_init(void)$/;" f diff --git a/cpu/lm4f120/1 b/cpu/lm4f120/1 new file mode 100644 index 0000000000..4203d56c5a --- /dev/null +++ b/cpu/lm4f120/1 @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __LM4F120H5QR_H__ +#define __LM4F120H5QR_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< LM4F120H5QR provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< LM4F120H5QR uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup cpu_specific_Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief LM4F120H5QR Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) /* FPU present for parser */ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include "cpu_conf.h" +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/cpu/lm4f120/Makefile b/cpu/lm4f120/Makefile new file mode 100644 index 0000000000..21f0d18719 --- /dev/null +++ b/cpu/lm4f120/Makefile @@ -0,0 +1,7 @@ +# define the module that is build +MODULE = cpu + +# add a list of subdirectories, that should also be build +DIRS = periph $(RIOTCPU)/cortexm_common + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/lm4f120/Makefile.include b/cpu/lm4f120/Makefile.include new file mode 100644 index 0000000000..ed4584a485 --- /dev/null +++ b/cpu/lm4f120/Makefile.include @@ -0,0 +1,6 @@ +export CPU_ARCH = cortex-m4f + +# use hwtimer compatibility module +USEMODULE += hwtimer_compat + +include $(RIOTCPU)/Makefile.include.cortexm_common diff --git a/cpu/lm4f120/cpu.c b/cpu/lm4f120/cpu.c new file mode 100644 index 0000000000..a360be785a --- /dev/null +++ b/cpu/lm4f120/cpu.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * @} + */ + +#include "cpu.h" +#include "irq.h" +#include "kernel.h" +#include "kernel_internal.h" +#include "sched.h" +#include "thread.h" +#include "arch/thread_arch.h" +#include "arch/irq_arch.h" + +unsigned long __attribute__((naked)) +CPUipsrGet(void) +{ + unsigned long ulRet; + + // + // Read IPSR + // + __asm(" mrs r0, IPSR\n" + " bx lr\n" + : "=r" (ulRet)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ulRet); +} + +void __attribute__((naked)) +DisableInterrupts(void) +{ + __asm(" CPSID I\n" + " BX LR\n"); +} + +void __attribute__((naked)) +EnableInterrupts(void) +{ + __asm(" CPSIE I\n" + " BX LR\n"); +} +/** + * @brief Initialize the CPU, set IRQ priorities + */ +void cpu_init(void) +{ + // initializes the Cortex-M core + cortexm_init(); + + /* initialize the clock system */ + cpu_clock_init(CLK40); +} + +void setup_fpu(void) +{ + ROM_FPUEnable(); + ROM_FPULazyStackingEnable(); +} + +void cpu_clock_init(int clk) +{ + setup_fpu(); + switch(clk){ + case CLK80: + ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN); + break; + case CLK50: + ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN); + break; + case CLK40: + ROM_SysCtlClockSet(SYSCTL_SYSDIV_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN); + break; + case CLK16: + ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN); + break; + case CLK1: + ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_1MHZ | SYSCTL_OSC_MAIN); + break; + default: + ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN); + break; + } +} + + diff --git a/cpu/lm4f120/include/cpu_conf.h b/cpu/lm4f120/include/cpu_conf.h new file mode 100644 index 0000000000..84ac1d3f26 --- /dev/null +++ b/cpu/lm4f120/include/cpu_conf.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + */ + +#ifndef __CPU_CONF_H +#define __CPU_CONF_H + +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_nvic.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "lm4f120h5qr.h" +#include "cortex-m4-def.h" +#include "stellaris_periph/cpu.h" +#include "stellaris_periph/debug.h" +#include "stellaris_periph/interrupt.h" +#include "stellaris_periph/sysctl.h" +#include "stellaris_periph/adc.h" +#include "stellaris_periph/gpio.h" +#include "stellaris_periph/timer.h" +#include "stellaris_periph/pin_map.h" +#include "stellaris_periph/uart.h" +#include "stellaris_periph/fpu.h" +#include "stellaris_periph/rom.h" +#include "hwtimer_cpu.h" +#include "periph/uart.h" +#include "stdio.h" +#include "stdlib.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ARM Cortex-M specific CPU configuration + * @{ + */ +#define CPU_DEFAULT_IRQ_PRIO (1U) +#define CPU_IRQ_NUMOF (48U) +#define CPU_FLASH_BASE FLASH_BASE +/** @} */ + +/** + * @brief Length for reading CPU_ID + */ +#define CPUID_ID_LEN (12) +#define CPUID_ADDR NVIC_CPUID + +/** + * @name CC110X buffer size definitions for the stm32f4 + * @{ + */ +#ifdef MODULE_CC110X +#define TRANSCEIVER_BUFFER_SIZE (10) +#define RX_BUF_SIZE (10) +#endif + +/** + * @name Define the nominal CPU core clock in this board + */ +#define F_CPU 1000000 +#define CLK80 1 +#define CLK50 2 +#define CLK40 3 +#define CLK16 4 +#define CLK1 5 + + +extern unsigned long CPUipsrGet(void); +extern void DisableInterrupts(void); +extern void EnableInterrupts(void); +extern void setup_fpu(void); +extern void cpu_clock_init(int); +extern int uart_init_testing(uart_t uart, uint32_t baudrate); +extern void UARTSend(const unsigned char *pucBuffer, unsigned long ulCount); + +#ifdef __cplusplus +} +#endif + +#endif /* __CPU_CONF_H */ +/** @} */ diff --git a/cpu/lm4f120/include/hwtimer_cpu.h b/cpu/lm4f120/include/hwtimer_cpu.h new file mode 100644 index 0000000000..ff84ae3f91 --- /dev/null +++ b/cpu/lm4f120/include/hwtimer_cpu.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + */ + +#ifndef __HWTIMER_CPU_H +#define __HWTIMER_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Hardware timer configuration + * @{ + */ +#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 4 HW timers */ +#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */ +#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */ +#define HWTIMER_MSEC (HWTIMER_SPEED/1000) +#define HWTIMER_SEC (HWTIMER_SPEED/1000000) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HWTIMER_CPU_H */ +/** @} */ diff --git a/cpu/lm4f120/include/lm4f120h5qr.h b/cpu/lm4f120/include/lm4f120h5qr.h new file mode 100644 index 0000000000..ea4b27b504 --- /dev/null +++ b/cpu/lm4f120/include/lm4f120h5qr.h @@ -0,0 +1,150 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __LM4F120H5QR_H__ +#define __LM4F120H5QR_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< LM4F120H5QR provides an MPU */ +#define __NVIC_PRIO_BITS 3 /*!< LM4F120H5QR uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup cpu_specific_Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief LM4F120H5QR Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** LM4F specific Interrupt Numbers **********************************************************************/ + GPIOPortA_IRQn = 0, + GPIOPortB_IRQn = 1, + GPIOPortC_IRQn = 2, + GPIOPortD_IRQn = 3, + GPIOPortE_IRQn = 4, + UART0_IRQn = 5, + UART1_IRQn = 6, + SSI0_IRQn = 7, + I2C0_IRQn = 8, + PWMFault_IRQn = 9, + PWM0_IRQn = 10, + PWM1_IRQn = 11, + PWM2_IRQn = 12, + Quadrature0_IRQn = 13, + ADC0_IRQn = 14, + ADC1_IRQn = 15, + ADC2_IRQn = 16, + ADC3_IRQn = 17, + WDT_IRQn = 18, + Timer0A_IRQn = 19, + Timer0B_IRQn = 20, + Timer1A_IRQn = 21, + Timer1B_IRQn = 22, + Timer2A_IRQn = 23, + Timer2B_IRQn = 24, + Comp0_IRQn = 25, + Comp1_IRQn = 26, + Comp2_IRQn = 27, + SysCtl_IRQn = 28, + FlashCtl_IRQn = 29, + GPIOPortF_IRQn = 30, + GPIOPortG_IRQn = 31, + GPIOPortH_IRQn = 32, + UART2_IRQn = 33, + SSI1_IRQn = 34, + Timer3A_IRQn = 35, + Timer3B_IRQn = 36, + I2C1_IRQn = 37, + Quadrature1_IRQn = 38, + CAN0_IRQn = 39, + CAN1_IRQn = 40, + CAN2_IRQn = 41, + Ethernet_IRQn = 42, + Hibernate_IRQn = 43, + USB0_IRQn = 44, + PWM3_IRQn = 45, + uDMA_IRQn = 46, + uDMA_Error_IRQn = 47, +} IRQn_Type; + + + /* +typedef enum +{ +// ****** Cortex-M4 Processor Exceptions Numbers **************************************************************** + NonMaskableInt_IRQn = 2, //!< 2 Non Maskable Interrupt + MemoryManagement_IRQn = 4, //!< 4 Cortex-M4 Memory Management Interrupt + BusFault_IRQn = 5, //!< 5 Cortex-M4 Bus Fault Interrupt + UsageFault_IRQn = 6, //!< 6 Cortex-M4 Usage Fault Interrupt + SVCall_IRQn = 11, //!< 11 Cortex-M4 SV Call Interrupt + DebugMonitor_IRQn = 12, //!< 12 Cortex-M4 Debug Monitor Interrupt + PendSV_IRQn = 14, //!< 14 Cortex-M4 Pend SV Interrupt + SysTick_IRQn = 15, //!< 15 Cortex-M4 System Tick Interrupt +} IRQn_Type; +*/ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include /* standard types definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + + diff --git a/cpu/lm4f120/ldscripts/lm4f120.ld b/cpu/lm4f120/ldscripts/lm4f120.ld new file mode 100644 index 0000000000..49d1231c68 --- /dev/null +++ b/cpu/lm4f120/ldscripts/lm4f120.ld @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * + * @} + */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +INCLUDE cortexm_base.ld diff --git a/cpu/lm4f120/lpm_arch.c b/cpu/lm4f120/lpm_arch.c new file mode 100644 index 0000000000..5d6992c2c4 --- /dev/null +++ b/cpu/lm4f120/lpm_arch.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * + * @} + */ + +#include "cpu.h" +#include "arch/lpm_arch.h" + +void lpm_arch_init(void) +{ + /* TODO */ +} + +enum lpm_mode lpm_arch_set(enum lpm_mode target) +{ + /* TODO */ + return 0; +} + +enum lpm_mode lpm_arch_get(void) +{ + /* TODO */ + return 0; +} + +void lpm_arch_awake(void) +{ + /* TODO*/ +} + +void lpm_arch_begin_awake(void) +{ + /* TODO */ +} + +void lpm_arch_end_awake(void) +{ + /* TODO */ +} diff --git a/cpu/lm4f120/periph/Makefile b/cpu/lm4f120/periph/Makefile new file mode 100644 index 0000000000..6d1887b640 --- /dev/null +++ b/cpu/lm4f120/periph/Makefile @@ -0,0 +1,3 @@ +MODULE = periph + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/lm4f120/periph/adc.c b/cpu/lm4f120/periph/adc.c new file mode 100644 index 0000000000..c9226db964 --- /dev/null +++ b/cpu/lm4f120/periph/adc.c @@ -0,0 +1,221 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * + * @} + */ + +#include "cpu.h" +#include "periph/adc.h" +#include "periph_conf.h" + +/* guard in case that no ADC device is defined */ +#if ADC_NUMOF + +typedef struct { + int max_value; +} adc_config_t; + +adc_config_t adc_config[ADC_NUMOF]; + +int adc_init(adc_t dev, adc_precision_t precision) +{ + adc_poweron(dev); + // ADC0 is used with AIN0 on port E3. + // ADC1 is used with AIN1 on port E2. + // GPIO port E needs to be enabled so that these pinds can be used + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); + + // Set the ADC to 125KSPS. + // This requires less power and produce longer samping time, + // creating accurate conversions + ROM_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_125KSPS); + + switch (precision) { + case ADC_RES_6BIT: + case ADC_RES_8BIT: + case ADC_RES_10BIT: +#if ADC_0_EN + ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_10BIT_S); +#endif +#if ADC_1_EN + ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_10BIT_S); +#endif + adc_config[dev].max_value = 0x3ff; + break; + case ADC_RES_12BIT: +#if ADC_0_EN + ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_12BIT_S); +#endif +#if ADC_1_EN + ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_12BIT_S); +#endif + adc_config[dev].max_value = 0xfff; + break; + case ADC_RES_14BIT: + case ADC_RES_16BIT: + break; + } + switch (dev) { +#if ADC_0_EN + case ADC_0: + // Select the Analog ADC Function for these pins. + ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3); + + // Before configuring the sequencer, we need to disable ita to prevent errorneous execution + ROM_ADCSequenceDisable(ADC0_BASE, 3); + + // Enable Sample Sequence 3 with a Software Start (Processor signal trigger). + // The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3. + // Sequence 3 will do a single sample when the processor sends a signal to start the conversion. + ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0); + + // Configure step 0 on sequence 3. + // Sample channel 0 (ADC_CTL_CH0) in single-ended mode and configure the interrupt flag. + // (ADC_CTL_IE) to be set to enable Interrupt. + ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0, + ADC_CTL_CH0 | ADC_CTL_IE | ADC_CTL_END); + + // Clear the interrupt status flag. This is done to make sure + // the interrupt flag is cleared before we sample. + ROM_ADCIntClear(ADC0_BASE, 3); + + // Since sample sequence 3 is now configured, it must be enabled. + ROM_ADCSequenceEnable(ADC0_BASE, 3); + + break; +#endif +#if ADC_1_EN + case ADC_1: + // Select the Analog ADC Function for these pins. + ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2); + + // Before configuring the sequencer, we need to disable ita to prevent errorneous execution + ROM_ADCSequenceDisable(ADC1_BASE, 3); + + // Enable Sample Sequence 3 with a Software Start (Processor signal trigger). + // The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3. + // Sequence 3 will do a single sample when the processor sends a signal to start the conversion. + ROM_ADCSequenceConfigure(ADC1_BASE, 3, ADC_TRIGGER_PROCESSOR, 0); + + // Configure step 0 on sequence 3. + // Sample channel 0 (ADC_CTL_CH1) in single-ended mode and configure the interrupt flag. + // (ADC_CTL_IE) to be set to enable Interrupt. + ROM_ADCSequenceStepConfigure(ADC1_BASE, 3, 0, + ADC_CTL_CH1 | ADC_CTL_IE | ADC_CTL_END); + + // Clear the interrupt status flag. This is done to make sure + // the interrupt flag is cleared before we sample. + ROM_ADCIntClear(ADC1_BASE, 3); + + // Since sample sequence 3 is now configured, it must be enabled. + ROM_ADCSequenceEnable(ADC1_BASE, 3); + + break; +#endif + default: + return -1; + } + return 0; +} + +int adc_sample(adc_t dev, int channel) +{ + unsigned long ulADC_val=0; + + switch (dev) { +#if ADC_0_EN + case ADC_0: + // Trigger the ADC conversion + ROM_ADCProcessorTrigger(ADC0_BASE, 3); + + // Wait for conversion to be completed. + while(!ROM_ADCIntStatus(ADC0_BASE, 3, false)); + + // Read ADC value. + ROM_ADCSequenceDataGet(ADC0_BASE, 3, &ulADC_val); + + // Clear the ADC interrupt flag + ROM_ADCIntClear(ADC0_BASE, 3); + break; +#endif +#if ADC_1_EN + case ADC_1: + // Trigger the ADC conversion + ROM_ADCProcessorTrigger(ADC1_BASE, 3); + + // Wait for conversion to be completed. + while(!ROM_ADCIntStatus(ADC1_BASE, 3, false)); + + // Read ADC value. + ROM_ADCSequenceDataGet(ADC1_BASE, 3, &ulADC_val); + + // Clear the ADC interrupt flag + ROM_ADCIntClear(ADC1_BASE, 3); + break; +#endif + default: + return -1; + } + + /* return result */ + return ((int)ulADC_val); +} + +void adc_poweron(adc_t dev) +{ + switch (dev) { +#if ADC_0_EN + case ADC_0: + // The ADC0 Peripheral must be enabled for use + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); + break; +#endif +#if ADC_1_EN + case ADC_1: + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1); + break; +#endif + } +} + +void adc_poweroff(adc_t dev) +{ + switch (dev) { +#if ADC_0_EN + case ADC_0: + ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0); + break; +#endif +#if ADC_1_EN + case ADC_1: + ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0); + break; +#endif + } +} + +int adc_map(adc_t dev, int value, int min, int max) +{ + return (int)adc_mapf(dev, value, (float)min, (float)max); +} + +float adc_mapf(adc_t dev, int value, float min, float max) +{ + return ((max - min) / ((float)adc_config[dev].max_value)) * value; +} + +#endif /* ADC_NUMOF */ diff --git a/cpu/lm4f120/periph/cpuid.c b/cpu/lm4f120/periph/cpuid.c new file mode 100644 index 0000000000..a8d2c4a924 --- /dev/null +++ b/cpu/lm4f120/periph/cpuid.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + */ + +#include +#include "cpu_conf.h" + +#include "periph/cpuid.h" + +void cpuid_get(void *id) +{ + memcpy(id, (void *)(CPUID_ADDR), CPUID_ID_LEN); +} + +/** @} */ diff --git a/cpu/lm4f120/periph/timer.c b/cpu/lm4f120/periph/timer.c new file mode 100644 index 0000000000..35f93386dd --- /dev/null +++ b/cpu/lm4f120/periph/timer.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * @} + */ + +#include + +#include "cpu.h" +#include "sched.h" +#include "thread.h" +#include "periph_conf.h" +#include "periph/timer.h" + +/* guard file in case no timers are defined */ +#if TIMER_0_EN + +/** + * @brief Struct holding the configuration data + */ +typedef struct { + void (*cb)(int); /**< timeout callback */ +} timer_conf_t; + +static timer_conf_t config[TIMER_NUMOF]; + +int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int)) +{ + if (dev == TIMER_0) { + config[dev].cb = callback; // User Function + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); //Activate Timer0 + WTIMER0_CTL_R &= ~0x00000001; // Disable timer0A during setup + WTIMER0_CFG_R = TIMER_CFG_16_BIT; + WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // | TIMER_TAMR_TACDIR); // Configure for periodic mode + WTIMER0_TAPR_R = 39; // 1us timer0A + WTIMER0_ICR_R = 0x00000001; // clear timer0A timeout flag + WTIMER0_IMR_R |= 0x00000001; // arm timeout interrupt +// NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO); + ROM_IntPrioritySet(INT_WTIMER0A, 32); + ROM_IntEnable(INT_WTIMER0A); + ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT); +// timer_irq_enable(dev); + timer_start(dev); + DEBUG("startTimeout Value=%lu\n", ROM_TimerValueGet(WTIMER0_BASE, TIMER_A)); + return 1; + } + return -1; +} + +int timer_set(tim_t dev, int channel, unsigned int timeout) +{ + if (dev == TIMER_0) { + unsigned int now = timer_read(dev); + DEBUG("timer_set now=%u\n",now); + DEBUG("timer_set timeout=%u\n", timeout); + return timer_set_absolute(dev, channel, HWTIMER_MAXTICKS-1-now+timeout); + } + return -1; +} + +int timer_set_absolute(tim_t dev, int channel, unsigned int value) +{ + if (dev == TIMER_0) { + WTIMER0_TAILR_R = 0x00000000 | value; // period; Reload value + DEBUG("Setting timer absolute value=%u\n", value); + return 1; + } + return -1; +} + +int timer_clear(tim_t dev, int channel) +{ + if (dev == TIMER_0){ + WTIMER0_TAILR_R = 0x00000000; // period; Reload value + return 1; + } + return -1; +} + +unsigned int timer_read(tim_t dev) +{ + if (dev == TIMER_0) { + unsigned int currTimer0Val=0; + currTimer0Val = (unsigned int)ROM_TimerValueGet(WTIMER0_BASE, TIMER_A); + return (HWTIMER_MAXTICKS - currTimer0Val); + } + return 0; +} + +void timer_start(tim_t dev) +{ + if (dev == TIMER_0) { + DEBUG("Starting the timer\n"); + ROM_TimerEnable(WTIMER0_BASE, TIMER_A); + } +} + +void timer_stop(tim_t dev) +{ + if (dev == TIMER_0) { + ROM_TimerDisable(WTIMER0_BASE, TIMER_A); + } +} + +void timer_irq_enable(tim_t dev) +{ + if (dev == TIMER_0) { + DEBUG("Enabling Timer Interrupts\n"); + ROM_IntEnable(INT_WTIMER0A); + ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT); + } +} + +void timer_irq_disable(tim_t dev) +{ + if (dev == TIMER_0) { + DEBUG("Disabling Timer Interrupts\n"); + ROM_IntDisable(INT_WTIMER0A); + } +} + +void timer_reset(tim_t dev) +{ + if (dev == TIMER_0) { + // Performs a software reset of a peripheral + ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WTIMER0); + } +} + +#if TIMER_0_EN +void TIMER0IntHandler(void) +{ + TIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout + config[TIMER_0].cb(0); + if (sched_context_switch_request){ + thread_yield(); + } +} +void WTIMER0IntHandler(void) +{ + WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout + + config[TIMER_0].cb(0); + if (sched_context_switch_request){ + thread_yield(); + } +} +#endif + +#endif /* TIMER_0_EN */ diff --git a/cpu/lm4f120/periph/uart.c b/cpu/lm4f120/periph/uart.c new file mode 100644 index 0000000000..da406890b7 --- /dev/null +++ b/cpu/lm4f120/periph/uart.c @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * @} + */ + +#include + +#include "cpu.h" +#include "sched.h" +#include "thread.h" +#include "periph/uart.h" +#include "periph_conf.h" + +/* guard the file in case no UART is defined */ +#if (UART_0_EN) + +/** + * @brief Struct holding the configuration data for a UART device + */ +typedef struct { + uart_rx_cb_t rx_cb; /**< receive callback */ + uart_tx_cb_t tx_cb; /**< transmit callback */ + void *arg; /**< callback argument */ +} uart_conf_t; + +/** + * @brief Unified interrupt handler for all UART devices + * + * @param uartnum the number of the UART that triggered the ISR + * @param uart the UART device that triggered the ISR + */ +//static inline void irq_handler(uart_t uartnum, USART_TypeDef *uart); + +/** + * @brief UART device configurations + */ +static uart_conf_t config[UART_NUMOF]; + +/** + * The list of UART peripherals. + */ +static const unsigned long g_ulUARTPeriph[3] = +{ + SYSCTL_PERIPH_UART0, + SYSCTL_PERIPH_UART1, + SYSCTL_PERIPH_UART2 +}; + +/** + * The list of all possible base address of the console UART + */ +static const unsigned long g_ulUARTBase[3] = +{ + UART0_BASE, + UART1_BASE, + UART2_BASE +}; + +// The list of possible interrupts for the console UART. +// +//***************************************************************************** +static const unsigned long g_ulUARTInt[3] = +{ + INT_UART0, + INT_UART1, + INT_UART2 +}; + +int uart_init_testing(uart_t uart, uint32_t baudrate) +{ + // Enable lazy stacking for interrupt handlers. This allows floating point instructions to be + // used within interrupt handers, but at the expense of extra stack usuage. + const unsigned long srcClock = ROM_SysCtlClockGet(); + + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + ROM_UARTDisable(UART0_BASE); + ROM_UARTConfigSetExpClk(UART0_BASE,srcClock, baudrate, + (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | + UART_CONFIG_WLEN_8)); + + //Enable the UART interrupt + ROM_UARTEnable(UART0_BASE); + + // Prompt for text to be entered. + // + //UARTSend((unsigned char *)"\033[2JEnter text: ", 16); + + // + // Loop forever echoing data through the UART. + // + printf("Passed Testing\n"); + return 1; +} + +void UARTSend(const unsigned char *pucBuffer, unsigned long ulCount) +{ + // + // Loop while there are more characters to send. + // + while(ulCount--) + { + // + // Write the next character to the UART. + // + ROM_UARTCharPutNonBlocking(UART0_BASE, *pucBuffer++); + } +} + + + + +/**********************************************************************************/ +/* Configuring the UART console + */ +int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg) +{ + // The base address of the Choosen UART + // unsigned long ulBase=0; + + // Check the arguments + ASSERT(uart == 0); + + // Check to make sure the UART peripheral is present + if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)) + { + return -1; + } + + int res = uart_init_blocking(uart, baudrate); + if(res < 0){ + return res; + } + + +/* save callbacks */ + config[uart].rx_cb = rx_cb; + config[uart].tx_cb = tx_cb; + config[uart].arg = arg; + +// Select the base address of the UART +// ulBase = g_ulUARTBase[uart]; + + // Configure the relevant UART pins for operations as a UART rather than GPIOs. + /* enable recieve interrupt */ + switch (uart){ +#if UART_0_EN + case UART_0: + NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO); + // Enable the UART interrupt + NVIC_EnableIRQ(UART_0_IRQ_CHAN); + //ROM_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT); + //ROM_IntEnable(INT_UART0); + break; +#endif +#if UART_1_EN + case UART_1: + NVIC_SetPriority(UART_1_IRQ_CHAN, UART_IRQ_PRIO); + // Enable the UART interrupt + NVIC_EnableIRQ(UART_1_IRQ_CHAN); + // ROM_UARTIntEnable(UART1_BASE, UART_INT_RX | UART_INT_RT); + // ROM_IntEnable(INT_UART1); + break; +#endif + } + return 0; +} + +int uart_init_blocking(uart_t uart, uint32_t baudrate) +{ + switch(uart){ +#if UART_0_EN + case UART_0: + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + ROM_GPIOPinConfigure(GPIO_PA0_U0RX); + ROM_GPIOPinConfigure(GPIO_PA1_U0TX); + ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + ROM_UARTDisable(UART0_BASE); + ROM_UARTConfigSetExpClk(UART0_BASE,ROM_SysCtlClockGet(), baudrate, + (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | + UART_CONFIG_WLEN_8)); + + ROM_UARTEnable(UART0_BASE); + break; +#endif + } + return 0; +} + +void uart_tx_begin(uart_t uart) +{ + // enable TX interrupt + ROM_UARTIntEnable(UART0_BASE, UART_INT_TX); +} + +int uart_write(uart_t uart, char data) +{ + ROM_UARTCharPutNonBlocking(UART0_BASE, data); + return 1; +} + +int uart_read_blocking(uart_t uart, char *data) +{ + *data = (char)ROM_UARTCharGet(UART0_BASE); + return 1; +} + +int uart_write_blocking(uart_t uart, char data) +{ + ROM_UARTCharPut(UART0_BASE, data); + return 1; +} + +void uart_poweron(uart_t uart) +{ + ROM_UARTEnable(UART0_BASE); +} + +void uart_poweroff(uart_t uart) +{ + ROM_UARTDisable(UART0_BASE); +} + +//***************************************************************************** +// +// The UART interrupt handler. +// +//***************************************************************************** + +void UARTIntHandler(void) +{ + unsigned long ulStatus; + char cChar; + long lChar; + + // Get the interrupt status + ulStatus = ROM_UARTIntStatus(UART0_BASE, true); + + // Clear the asserted interrupts + ROM_UARTIntClear(UART0_BASE, ulStatus); + + // Are we interrupted due to TX done + if(ulStatus & UART_INT_TX) + { + // Turn off the Transmit Interrupt + if (config[UART_0].tx_cb(config[UART_0].arg) == 0){ + ROM_UARTIntDisable(UART0_BASE, UART_INT_TX); + } + } + + // Are we interrupted due to a recieved character + if(ulStatus & (UART_INT_RX | UART_INT_RT)) + { + // Get all the available characters from the UART + while(ROM_UARTCharsAvail(UART0_BASE)) + { + // Read a character + lChar = ROM_UARTCharGetNonBlocking(UART0_BASE); + cChar = (unsigned char)(lChar & 0xFF); + config[UART_0].rx_cb(config[UART_0].arg, cChar); + } + } + if (sched_context_switch_request) { + thread_yield(); + } +} + + + + +#endif /* (UART_0_EN || UART_1_EN) */ diff --git a/cpu/lm4f120/startup.c b/cpu/lm4f120/startup.c new file mode 100644 index 0000000000..ecbd99588e --- /dev/null +++ b/cpu/lm4f120/startup.c @@ -0,0 +1,315 @@ +/* + * Copyright (C) 2015 Rakendra Thapa + * + * @} + */ + +#include +#include "cpu.h" + +/** + * memory markers as defined in the linker script + */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + + +//----------------------------------------------------------------------------- +// Functions declarations +//----------------------------------------------------------------------------- +void reset_handler(void); +static void NmiSR(void); +static void FaultISR(void); +extern void empty_def_handler(void); + + +extern void board_init(void); +extern void kernel_init(void); +extern void __libc_init_array(void); + +/** + * Required by g++ cross compiler + */ +void *__dso_handle; + + +// External declaration for the interrupt handler used by the application +extern void UARTIntHandler(void); // UART 0 21 +extern void UART1IntHandler(void); // UART 1 21 +extern void TIMER0IntHandler(void); // 16 bit timer 0 A +extern void WTIMER0IntHandler(void); // 32 bit timer 0 A +extern void TIMER1IntHandler(void); // 16 bit timer 1 A +extern void isr_svc(void); // SV call +extern void isr_pendsv(void); // PendSV +extern void isr_bus_fault(void); // Bus Fault +extern void isr_usage_fault(void); // Usage Fault + +/* interrupt vector table */ +__attribute__ ((section(".vectors"))) +const void *interrupt_vector[] = { + /* Stack pointer */ + (void*) (&_estack), /* pointer to the top of the empty stack */ + /* Cortex-M4 handlers */ + (void*) reset_handler, /* entry point of the program */ + NmiSR, // NMI handler. 2 + FaultISR, // hard fault handler. 3 + // Configurable priority interruts handler start here. + empty_def_handler, // Memory Management Fault 4 + isr_bus_fault, // Bus Fault 5 + isr_usage_fault, // Usage Fault 6 + 0, // Reserved 7 + 0, // Reserved 8 + 0, // Reserved 9 + 0, // Reserved 10 + isr_svc, // SV call 11 + empty_def_handler, // Debug monitor 12 + 0, // Reserved 13 + isr_pendsv, // PendSV 14 + empty_def_handler, // SysTick 15 + // Peripherial interrupts start here. + empty_def_handler, // GPIO Port A 16 + empty_def_handler, // GPIO Port B 17 + empty_def_handler, // GPIO Port C 18 + empty_def_handler, // GPIO Port D 19 + empty_def_handler, // GPIO Port E 20 + UARTIntHandler, // UART 0 21 + UART1IntHandler, // UART 1 22 + empty_def_handler, // SSI 0 23 + empty_def_handler, // I2C 0 24 + 0, // Reserved 25 + 0, // Reserved 26 + 0, // Reserved 27 + 0, // Reserved 28 + 0, // Reserved 29 + empty_def_handler, // ADC 0 Seq 0 30 + empty_def_handler, // ADC 0 Seq 1 31 + empty_def_handler, // ADC 0 Seq 2 32 + empty_def_handler, // ADC 0 Seq 3 33 + empty_def_handler, // WDT 0 and 1 34 + TIMER0IntHandler, // 16/32 bit timer 0 A 35 + empty_def_handler, // 16/32 bit timer 0 B 36 + TIMER1IntHandler, // 16/32 bit timer 1 A 37 + empty_def_handler, // 16/32 bit timer 1 B 38 + empty_def_handler, // 16/32 bit timer 2 A 39 + empty_def_handler, // 16/32 bit timer 2 B 40 + empty_def_handler, // Analog comparator 0 41 + empty_def_handler, // Analog comparator 1 42 + 0, // Reserved 43 + empty_def_handler, // System control 44 + empty_def_handler, // Flash + EEPROM control 45 + empty_def_handler, // GPIO Port F 46 + 0, // Reserved 47 + 0, // Reserved 48 + empty_def_handler, // UART 2 49 + empty_def_handler, // SSI 1 50 + empty_def_handler, // 16/32 bit timer 3 A 51 + empty_def_handler, // 16/32 bit timer 3 B 52 + empty_def_handler, // I2C 1 53 + 0, // Reserved 54 + empty_def_handler, // CAN 0 55 + 0, // Reserved 56 + 0, // Reserved 57 + 0, // Reserved 58 + empty_def_handler, // Hibernation module 59 + empty_def_handler, // USB 60 + 0, // Reserved 61 + empty_def_handler, // UDMA SW 62 + empty_def_handler, // UDMA Error 63 + empty_def_handler, // ADC 1 Seq 0 64 + empty_def_handler, // ADC 1 Seq 1 65 + empty_def_handler, // ADC 1 Seq 2 66 + empty_def_handler, // ADC 1 Seq 3 67 + 0, // Reserved 68 + 0, // Reserved 69 + 0, // Reserved 70 + 0, // Reserved 71 + 0, // Reserved 72 + empty_def_handler, // SSI 2 73 + empty_def_handler, // SSI 2 74 + empty_def_handler, // UART 3 75 + empty_def_handler, // UART 4 76 + empty_def_handler, // UART 5 77 + empty_def_handler, // UART 6 78 + empty_def_handler, // UART 7 79 + 0, // Reserved 80 + 0, // Reserved 81 + 0, // Reserved 82 + 0, // Reserved 83 + empty_def_handler, // I2C 2 84 + empty_def_handler, // I2C 4 85 + empty_def_handler, // 16/32 bit timer 4 A 86 + empty_def_handler, // 16/32 bit timer 4 B 87 + 0, // Reserved 88 + 0, // Reserved 89 + 0, // Reserved 90 + 0, // Reserved 91 + 0, // Reserved 92 + 0, // Reserved 93 + 0, // Reserved 94 + 0, // Reserved 95 + 0, // Reserved 96 + 0, // Reserved 97 + 0, // Reserved 98 + 0, // Reserved 99 + 0, // Reserved 100 + 0, // Reserved 101 + 0, // Reserved 102 + 0, // Reserved 103 + 0, // Reserved 104 + 0, // Reserved 105 + 0, // Reserved 106 + 0, // Reserved 107 + empty_def_handler, // 16/32 bit timer 5 A 108 + empty_def_handler, // 16/32 bit timer 5 B 109 + WTIMER0IntHandler, // 32/64 bit timer 0 A 110 + empty_def_handler, // 32/64 bit timer 0 B 111 + empty_def_handler, // 32/64 bit timer 1 A 112 + empty_def_handler, // 32/64 bit timer 1 B 113 + empty_def_handler, // 32/64 bit timer 2 A 114 + empty_def_handler, // 32/64 bit timer 2 B 115 + empty_def_handler, // 32/64 bit timer 3 A 116 + empty_def_handler, // 32/64 bit timer 3 B 117 + empty_def_handler, // 32/64 bit timer 4 A 118 + empty_def_handler, // 32/64 bit timer 4 B 119 + empty_def_handler, // 32/64 bit timer 5 A 120 + empty_def_handler, // 32/64 bit timer 5 B 121 + empty_def_handler, // System Exception 122 + 0, // Reserved 123 + 0, // Reserved 124 + 0, // Reserved 125 + 0, // Reserved 126 + 0, // Reserved 127 + 0, // Reserved 128 + 0, // Reserved 129 + 0, // Reserved 130 + 0, // Reserved 131 + 0, // Reserved 132 + 0, // Reserved 133 + 0, // Reserved 134 + 0, // Reserved 135 + 0, // Reserved 136 + 0, // Reserved 137 + 0, // Reserved 138 + 0, // Reserved 139 + 0, // Reserved 140 + 0, // Reserved 141 + 0, // Reserved 142 + 0, // Reserved 143 + 0, // Reserved 144 + 0, // Reserved 145 + 0, // Reserved 146 + 0, // Reserved 147 + 0, // Reserved 148 + 0, // Reserved 149 + 0, // Reserved 150 + 0, // Reserved 151 + 0, // Reserved 152 + 0, // Reserved 153 + 0 // Reserved 154 +}; +// +//----------------------------------------------------------------------------- +// Function implementations. +//----------------------------------------------------------------------------- +/** + * @brief This function is the entry point after a system reset + * + * After a system reset, the following steps are necessary and carried out: + * 1. load data section from flash to ram + * 2. overwrite uninitialized data section (BSS) with zeros + * 3. initialize the newlib + * 4. initialize the board (sync clock, setup std-IO) + * 5. initialize and start RIOTs kernel + */ + +void reset_handler(void) +{ + uint32_t *dst; + uint32_t *src = &_etext; + + /* load data section from flash to ram */ + for (dst = &_srelocate; dst < &_erelocate; ) { + *(dst++) = *(src++); + } + + /* default bss section to zero */ + for (dst = &_szero; dst < &_ezero; ) { + *(dst++) = 0; + } + + /* initialize the board and startup the kernel */ + board_init(); + /* initialize std-c library (this should be done after board_init) */ + __libc_init_array(); + /* startup the kernel */ + kernel_init(); +} + +// NMI Exception handler code NVIC 2 +static +void NmiSR(void){ + // Just loop forever, so if you want to debug the processor it's running. + while(1){ + } +} + +// Hard fault handler code NVIC 3 +static +void FaultISR(void){ + // Just loop forever, so if you want to debug the processor it's running. + while(1){ + } +} + +void isr_bus_fault(void){ // Bus Fault +// Bus fault handler code + // Just loop forever, so if you want to debug the processor it's running. + while(1){ + } +} + +void isr_usage_fault(void){ // Usage Fault +// Usage fault handler code +// Just loop forever, so if you want to debug the processor it's running. + while(1){ + } +} + +// Empty handler used as default. +void empty_def_handler(void){ + // Just loop forever, so if you want to debug the processor it's running. + while(1){ + } +} + +void TIMER1IntHandler(void){ +// Just loop forever, so if you want to debug the processor it's running. + while(1){ + } +} + +void UART1IntHandler(void){ + while(1){ + } +} diff --git a/cpu/stellaris_common/EULA.txt b/cpu/stellaris_common/EULA.txt new file mode 100644 index 0000000000..352ec12532 --- /dev/null +++ b/cpu/stellaris_common/EULA.txt @@ -0,0 +1,400 @@ +TI StellarisWare Clickwrap Software License Agreement (SLA) + +Important - This is a legally binding agreement. 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You hereby agree that unless prior authorization +is obtained from the U.S. Department of Commerce, neither you nor your +subsidiaries or affiliates shall knowingly export, re-export, or release, +directly or indirectly, any technology, software, or software source code (as +defined in Part 772 of the Export Administration Regulations of the U.S. +Department of Commerce ("EAR")), received from TI or any of its affiliated +companies, or export, directly or indirectly, any direct product of such +technology, software, or software source code (as defined in Part 734 of the +EAR), to any destination or country to which the export, re-export, or release +of the technology, software, software source code, or direct product is +prohibited by the EAR. + +(ii). Assurance of Compliance. You understand and acknowledge that products, +technology (regardless of the form in which it is provided), software or +software source code, received from TI or any of its affiliates under this +Agreement may be under export control of the United States or other countries. +You shall comply with the United States and other applicable non-U.S. laws and +regulations governing the export, re-export and release of any products, +technology, software, or software source code received under this Agreement +from TI or its affiliates. You shall not undertake any action that is +prohibited by the EAR. Without limiting the generality of the foregoing, you +specifically agree that you shall not transfer or release products, technology, +software, or software source code of TI or its affiliates to, or for use by, +military end users or for use in military, missile, nuclear, biological, or +chemical weapons end uses. + +(iii). Licenses. Each party shall secure at its own expense, such licenses and +export and import documents as are necessary for each respective party to +fulfill its obligations under this Agreement. If such licenses or government +approvals cannot be obtained, TI may terminate this Agreement, or shall +otherwise be excused from the performance of any obligations it may have under +this Agreement for which the licenses or government approvals are required. + +13. Entire Agreement. This is the entire Agreement between you and TI, and +absent a signed and effective software license agreement related to the subject +matter of this Agreement, this Agreement supersedes any prior agreement between +the parties related to the subject matter of this Agreement. Notwithstanding +the foregoing, any signed and effective software license agreement relating to +the subject matter hereof will supersede the terms of this Agreement. No +amendment or modification of this Agreement will be effective unless in writing +and signed by a duly authorized representative of TI. You hereby warrant and +represent that you have obtained all authorizations and other applicable +consents required empowering you to enter into this Agreement. + diff --git a/cpu/stellaris_common/TI-BSD-EULA.txt b/cpu/stellaris_common/TI-BSD-EULA.txt new file mode 100644 index 0000000000..5b6e8fce24 --- /dev/null +++ b/cpu/stellaris_common/TI-BSD-EULA.txt @@ -0,0 +1,29 @@ +Software License Agreement + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the original copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the original copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/cpu/stellaris_common/include/cortex-m4-def.h b/cpu/stellaris_common/include/cortex-m4-def.h new file mode 100644 index 0000000000..f0580d87da --- /dev/null +++ b/cpu/stellaris_common/include/cortex-m4-def.h @@ -0,0 +1,10025 @@ +//***************************************************************************** +// +// lm4f120h5qr.h - LM4F120H5QR Register Definitions +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __CORTEX_M4_DEF_H__ +#define __CORTEX_M4_DEF_H__ + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG0) +// +//***************************************************************************** +#define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000)) +#define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004)) +#define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008)) +#define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C)) +#define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010)) +#define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014)) +#define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418)) +#define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00)) + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG1) +// +//***************************************************************************** +#define WATCHDOG1_LOAD_R (*((volatile unsigned long *)0x40001000)) +#define WATCHDOG1_VALUE_R (*((volatile unsigned long *)0x40001004)) +#define WATCHDOG1_CTL_R (*((volatile unsigned long *)0x40001008)) +#define WATCHDOG1_ICR_R (*((volatile unsigned long *)0x4000100C)) +#define WATCHDOG1_RIS_R (*((volatile unsigned long *)0x40001010)) +#define WATCHDOG1_MIS_R (*((volatile unsigned long *)0x40001014)) +#define WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418)) +#define WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00)) + +//***************************************************************************** +// +// GPIO registers (PORTA) +// +//***************************************************************************** +#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000) +#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC)) +#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400)) +#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404)) +#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408)) +#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C)) +#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410)) +#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414)) +#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418)) +#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C)) +#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420)) +#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500)) +#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504)) +#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508)) +#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C)) +#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510)) +#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514)) +#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518)) +#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C)) +#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520)) +#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524)) +#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528)) +#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C)) +#define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530)) +#define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534)) +#define GPIO_PORTA_SI_R (*((volatile unsigned long *)0x40004538)) + +//***************************************************************************** +// +// GPIO registers (PORTB) +// +//***************************************************************************** +#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000) +#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC)) +#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400)) +#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404)) +#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408)) +#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C)) +#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410)) +#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414)) +#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418)) +#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C)) +#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420)) +#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500)) +#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504)) +#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508)) +#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C)) +#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510)) +#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514)) +#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518)) +#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C)) +#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520)) +#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524)) +#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528)) +#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C)) +#define GPIO_PORTB_ADCCTL_R (*((volatile unsigned long *)0x40005530)) +#define GPIO_PORTB_DMACTL_R (*((volatile unsigned long *)0x40005534)) +#define GPIO_PORTB_SI_R (*((volatile unsigned long *)0x40005538)) + +//***************************************************************************** +// +// GPIO registers (PORTC) +// +//***************************************************************************** +#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000) +#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC)) +#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400)) +#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404)) +#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408)) +#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C)) +#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410)) +#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414)) +#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418)) +#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C)) +#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420)) +#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500)) +#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504)) +#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508)) +#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C)) +#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510)) +#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514)) +#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518)) +#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C)) +#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520)) +#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524)) +#define GPIO_PORTC_AMSEL_R (*((volatile unsigned long *)0x40006528)) +#define GPIO_PORTC_PCTL_R (*((volatile unsigned long *)0x4000652C)) +#define GPIO_PORTC_ADCCTL_R (*((volatile unsigned long *)0x40006530)) +#define GPIO_PORTC_DMACTL_R (*((volatile unsigned long *)0x40006534)) +#define GPIO_PORTC_SI_R (*((volatile unsigned long *)0x40006538)) + +//***************************************************************************** +// +// GPIO registers (PORTD) +// +//***************************************************************************** +#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000) +#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC)) +#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400)) +#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404)) +#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408)) +#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C)) +#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410)) +#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414)) +#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418)) +#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C)) +#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420)) +#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500)) +#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504)) +#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508)) +#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C)) +#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510)) +#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514)) +#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518)) +#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C)) +#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520)) +#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524)) +#define GPIO_PORTD_AMSEL_R (*((volatile unsigned long *)0x40007528)) +#define GPIO_PORTD_PCTL_R (*((volatile unsigned long *)0x4000752C)) +#define GPIO_PORTD_ADCCTL_R (*((volatile unsigned long *)0x40007530)) +#define GPIO_PORTD_DMACTL_R (*((volatile unsigned long *)0x40007534)) +#define GPIO_PORTD_SI_R (*((volatile unsigned long *)0x40007538)) + +//***************************************************************************** +// +// SSI registers (SSI0) +// +//***************************************************************************** +#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000)) +#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004)) +#define SSI0_DR_R (*((volatile unsigned long *)0x40008008)) +#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C)) +#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010)) +#define SSI0_IM_R (*((volatile unsigned long *)0x40008014)) +#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018)) +#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C)) +#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020)) +#define SSI0_DMACTL_R (*((volatile unsigned long *)0x40008024)) +#define SSI0_CC_R (*((volatile unsigned long *)0x40008FC8)) + +//***************************************************************************** +// +// SSI registers (SSI1) +// +//***************************************************************************** +#define SSI1_CR0_R (*((volatile unsigned long *)0x40009000)) +#define SSI1_CR1_R (*((volatile unsigned long *)0x40009004)) +#define SSI1_DR_R (*((volatile unsigned long *)0x40009008)) +#define SSI1_SR_R (*((volatile unsigned long *)0x4000900C)) +#define SSI1_CPSR_R (*((volatile unsigned long *)0x40009010)) +#define SSI1_IM_R (*((volatile unsigned long *)0x40009014)) +#define SSI1_RIS_R (*((volatile unsigned long *)0x40009018)) +#define SSI1_MIS_R (*((volatile unsigned long *)0x4000901C)) +#define SSI1_ICR_R (*((volatile unsigned long *)0x40009020)) +#define SSI1_DMACTL_R (*((volatile unsigned long *)0x40009024)) +#define SSI1_CC_R (*((volatile unsigned long *)0x40009FC8)) + +//***************************************************************************** +// +// SSI registers (SSI2) +// +//***************************************************************************** +#define SSI2_CR0_R (*((volatile unsigned long *)0x4000A000)) +#define SSI2_CR1_R (*((volatile unsigned long *)0x4000A004)) +#define SSI2_DR_R (*((volatile unsigned long *)0x4000A008)) +#define SSI2_SR_R (*((volatile unsigned long *)0x4000A00C)) +#define SSI2_CPSR_R (*((volatile unsigned long *)0x4000A010)) +#define SSI2_IM_R (*((volatile unsigned long *)0x4000A014)) +#define SSI2_RIS_R (*((volatile unsigned long *)0x4000A018)) +#define SSI2_MIS_R (*((volatile unsigned long *)0x4000A01C)) +#define SSI2_ICR_R (*((volatile unsigned long *)0x4000A020)) +#define SSI2_DMACTL_R (*((volatile unsigned long *)0x4000A024)) +#define SSI2_CC_R (*((volatile unsigned long *)0x4000AFC8)) + +//***************************************************************************** +// +// SSI registers (SSI3) +// +//***************************************************************************** +#define SSI3_CR0_R (*((volatile unsigned long *)0x4000B000)) +#define SSI3_CR1_R (*((volatile unsigned long *)0x4000B004)) +#define SSI3_DR_R (*((volatile unsigned long *)0x4000B008)) +#define SSI3_SR_R (*((volatile unsigned long *)0x4000B00C)) +#define SSI3_CPSR_R (*((volatile unsigned long *)0x4000B010)) +#define SSI3_IM_R (*((volatile unsigned long *)0x4000B014)) +#define SSI3_RIS_R (*((volatile unsigned long *)0x4000B018)) +#define SSI3_MIS_R (*((volatile unsigned long *)0x4000B01C)) +#define SSI3_ICR_R (*((volatile unsigned long *)0x4000B020)) +#define SSI3_DMACTL_R (*((volatile unsigned long *)0x4000B024)) +#define SSI3_CC_R (*((volatile unsigned long *)0x4000BFC8)) + +//***************************************************************************** +// +// UART registers (UART0) +// +//***************************************************************************** +#define UART0_DR_R (*((volatile unsigned long *)0x4000C000)) +#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004)) +#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004)) +#define UART0_FR_R (*((volatile unsigned long *)0x4000C018)) +#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020)) +#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024)) +#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028)) +#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C)) +#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030)) +#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034)) +#define UART0_IM_R (*((volatile unsigned long *)0x4000C038)) +#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C)) +#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040)) +#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044)) +#define UART0_DMACTL_R (*((volatile unsigned long *)0x4000C048)) +#define UART0_LCTL_R (*((volatile unsigned long *)0x4000C090)) +#define UART0_LSS_R (*((volatile unsigned long *)0x4000C094)) +#define UART0_LTIM_R (*((volatile unsigned long *)0x4000C098)) +#define UART0_9BITADDR_R (*((volatile unsigned long *)0x4000C0A4)) +#define UART0_9BITAMASK_R (*((volatile unsigned long *)0x4000C0A8)) +#define UART0_PP_R (*((volatile unsigned long *)0x4000CFC0)) +#define UART0_CC_R (*((volatile unsigned long *)0x4000CFC8)) + +//***************************************************************************** +// +// UART registers (UART1) +// +//***************************************************************************** +#define UART1_DR_R (*((volatile unsigned long *)0x4000D000)) +#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004)) +#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004)) +#define UART1_FR_R (*((volatile unsigned long *)0x4000D018)) +#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020)) +#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024)) +#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028)) +#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C)) +#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030)) +#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034)) +#define UART1_IM_R (*((volatile unsigned long *)0x4000D038)) +#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C)) +#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040)) +#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044)) +#define UART1_DMACTL_R (*((volatile unsigned long *)0x4000D048)) +#define UART1_LCTL_R (*((volatile unsigned long *)0x4000D090)) +#define UART1_LSS_R (*((volatile unsigned long *)0x4000D094)) +#define UART1_LTIM_R (*((volatile unsigned long *)0x4000D098)) +#define UART1_9BITADDR_R (*((volatile unsigned long *)0x4000D0A4)) +#define UART1_9BITAMASK_R (*((volatile unsigned long *)0x4000D0A8)) +#define UART1_PP_R (*((volatile unsigned long *)0x4000DFC0)) +#define UART1_CC_R (*((volatile unsigned long *)0x4000DFC8)) + +//***************************************************************************** +// +// UART registers (UART2) +// +//***************************************************************************** +#define UART2_DR_R (*((volatile unsigned long *)0x4000E000)) +#define UART2_RSR_R (*((volatile unsigned long *)0x4000E004)) +#define UART2_ECR_R (*((volatile unsigned long *)0x4000E004)) +#define UART2_FR_R (*((volatile unsigned long *)0x4000E018)) +#define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020)) +#define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024)) +#define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028)) +#define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C)) +#define UART2_CTL_R (*((volatile unsigned long *)0x4000E030)) +#define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034)) +#define UART2_IM_R (*((volatile unsigned long *)0x4000E038)) +#define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C)) +#define UART2_MIS_R (*((volatile unsigned long *)0x4000E040)) +#define UART2_ICR_R (*((volatile unsigned long *)0x4000E044)) +#define UART2_DMACTL_R (*((volatile unsigned long *)0x4000E048)) +#define UART2_LCTL_R (*((volatile unsigned long *)0x4000E090)) +#define UART2_LSS_R (*((volatile unsigned long *)0x4000E094)) +#define UART2_LTIM_R (*((volatile unsigned long *)0x4000E098)) +#define UART2_9BITADDR_R (*((volatile unsigned long *)0x4000E0A4)) +#define UART2_9BITAMASK_R (*((volatile unsigned long *)0x4000E0A8)) +#define UART2_PP_R (*((volatile unsigned long *)0x4000EFC0)) +#define UART2_CC_R (*((volatile unsigned long *)0x4000EFC8)) + +//***************************************************************************** +// +// UART registers (UART3) +// +//***************************************************************************** +#define UART3_DR_R (*((volatile unsigned long *)0x4000F000)) +#define UART3_RSR_R (*((volatile unsigned long *)0x4000F004)) +#define UART3_ECR_R (*((volatile unsigned long *)0x4000F004)) +#define UART3_FR_R (*((volatile unsigned long *)0x4000F018)) +#define UART3_ILPR_R (*((volatile unsigned long *)0x4000F020)) +#define UART3_IBRD_R (*((volatile unsigned long *)0x4000F024)) +#define UART3_FBRD_R (*((volatile unsigned long *)0x4000F028)) +#define UART3_LCRH_R (*((volatile unsigned long *)0x4000F02C)) +#define UART3_CTL_R (*((volatile unsigned long *)0x4000F030)) +#define UART3_IFLS_R (*((volatile unsigned long *)0x4000F034)) +#define UART3_IM_R (*((volatile unsigned long *)0x4000F038)) +#define UART3_RIS_R (*((volatile unsigned long *)0x4000F03C)) +#define UART3_MIS_R (*((volatile unsigned long *)0x4000F040)) +#define UART3_ICR_R (*((volatile unsigned long *)0x4000F044)) +#define UART3_DMACTL_R (*((volatile unsigned long *)0x4000F048)) +#define UART3_LCTL_R (*((volatile unsigned long *)0x4000F090)) +#define UART3_LSS_R (*((volatile unsigned long *)0x4000F094)) +#define UART3_LTIM_R (*((volatile unsigned long *)0x4000F098)) +#define UART3_9BITADDR_R (*((volatile unsigned long *)0x4000F0A4)) +#define UART3_9BITAMASK_R (*((volatile unsigned long *)0x4000F0A8)) +#define UART3_PP_R (*((volatile unsigned long *)0x4000FFC0)) +#define UART3_CC_R (*((volatile unsigned long *)0x4000FFC8)) + +//***************************************************************************** +// +// UART registers (UART4) +// +//***************************************************************************** +#define UART4_DR_R (*((volatile unsigned long *)0x40010000)) +#define UART4_RSR_R (*((volatile unsigned long *)0x40010004)) +#define UART4_ECR_R (*((volatile unsigned long *)0x40010004)) +#define UART4_FR_R (*((volatile unsigned long *)0x40010018)) +#define UART4_ILPR_R (*((volatile unsigned long *)0x40010020)) +#define UART4_IBRD_R (*((volatile unsigned long *)0x40010024)) +#define UART4_FBRD_R (*((volatile unsigned long *)0x40010028)) +#define UART4_LCRH_R (*((volatile unsigned long *)0x4001002C)) +#define UART4_CTL_R (*((volatile unsigned long *)0x40010030)) +#define UART4_IFLS_R (*((volatile unsigned long *)0x40010034)) +#define UART4_IM_R (*((volatile unsigned long *)0x40010038)) +#define UART4_RIS_R (*((volatile unsigned long *)0x4001003C)) +#define UART4_MIS_R (*((volatile unsigned long *)0x40010040)) +#define UART4_ICR_R (*((volatile unsigned long *)0x40010044)) +#define UART4_DMACTL_R (*((volatile unsigned long *)0x40010048)) +#define UART4_LCTL_R (*((volatile unsigned long *)0x40010090)) +#define UART4_LSS_R (*((volatile unsigned long *)0x40010094)) +#define UART4_LTIM_R (*((volatile unsigned long *)0x40010098)) +#define UART4_9BITADDR_R (*((volatile unsigned long *)0x400100A4)) +#define UART4_9BITAMASK_R (*((volatile unsigned long *)0x400100A8)) +#define UART4_PP_R (*((volatile unsigned long *)0x40010FC0)) +#define UART4_CC_R (*((volatile unsigned long *)0x40010FC8)) + +//***************************************************************************** +// +// UART registers (UART5) +// +//***************************************************************************** +#define UART5_DR_R (*((volatile unsigned long *)0x40011000)) +#define UART5_RSR_R (*((volatile unsigned long *)0x40011004)) +#define UART5_ECR_R (*((volatile unsigned long *)0x40011004)) +#define UART5_FR_R (*((volatile unsigned long *)0x40011018)) +#define UART5_ILPR_R (*((volatile unsigned long *)0x40011020)) +#define UART5_IBRD_R (*((volatile unsigned long *)0x40011024)) +#define UART5_FBRD_R (*((volatile unsigned long *)0x40011028)) +#define UART5_LCRH_R (*((volatile unsigned long *)0x4001102C)) +#define UART5_CTL_R (*((volatile unsigned long *)0x40011030)) +#define UART5_IFLS_R (*((volatile unsigned long *)0x40011034)) +#define UART5_IM_R (*((volatile unsigned long *)0x40011038)) +#define UART5_RIS_R (*((volatile unsigned long *)0x4001103C)) +#define UART5_MIS_R (*((volatile unsigned long *)0x40011040)) +#define UART5_ICR_R (*((volatile unsigned long *)0x40011044)) +#define UART5_DMACTL_R (*((volatile unsigned long *)0x40011048)) +#define UART5_LCTL_R (*((volatile unsigned long *)0x40011090)) +#define UART5_LSS_R (*((volatile unsigned long *)0x40011094)) +#define UART5_LTIM_R (*((volatile unsigned long *)0x40011098)) +#define UART5_9BITADDR_R (*((volatile unsigned long *)0x400110A4)) +#define UART5_9BITAMASK_R (*((volatile unsigned long *)0x400110A8)) +#define UART5_PP_R (*((volatile unsigned long *)0x40011FC0)) +#define UART5_CC_R (*((volatile unsigned long *)0x40011FC8)) + +//***************************************************************************** +// +// UART registers (UART6) +// +//***************************************************************************** +#define UART6_DR_R (*((volatile unsigned long *)0x40012000)) +#define UART6_RSR_R (*((volatile unsigned long *)0x40012004)) +#define UART6_ECR_R (*((volatile unsigned long *)0x40012004)) +#define UART6_FR_R (*((volatile unsigned long *)0x40012018)) +#define UART6_ILPR_R (*((volatile unsigned long *)0x40012020)) +#define UART6_IBRD_R (*((volatile unsigned long *)0x40012024)) +#define UART6_FBRD_R (*((volatile unsigned long *)0x40012028)) +#define UART6_LCRH_R (*((volatile unsigned long *)0x4001202C)) +#define UART6_CTL_R (*((volatile unsigned long *)0x40012030)) +#define UART6_IFLS_R (*((volatile unsigned long *)0x40012034)) +#define UART6_IM_R (*((volatile unsigned long *)0x40012038)) +#define UART6_RIS_R (*((volatile unsigned long *)0x4001203C)) +#define UART6_MIS_R (*((volatile unsigned long *)0x40012040)) +#define UART6_ICR_R (*((volatile unsigned long *)0x40012044)) +#define UART6_DMACTL_R (*((volatile unsigned long *)0x40012048)) +#define UART6_LCTL_R (*((volatile unsigned long *)0x40012090)) +#define UART6_LSS_R (*((volatile unsigned long *)0x40012094)) +#define UART6_LTIM_R (*((volatile unsigned long *)0x40012098)) +#define UART6_9BITADDR_R (*((volatile unsigned long *)0x400120A4)) +#define UART6_9BITAMASK_R (*((volatile unsigned long *)0x400120A8)) +#define UART6_PP_R (*((volatile unsigned long *)0x40012FC0)) +#define UART6_CC_R (*((volatile unsigned long *)0x40012FC8)) + +//***************************************************************************** +// +// UART registers (UART7) +// +//***************************************************************************** +#define UART7_DR_R (*((volatile unsigned long *)0x40013000)) +#define UART7_RSR_R (*((volatile unsigned long *)0x40013004)) +#define UART7_ECR_R (*((volatile unsigned long *)0x40013004)) +#define UART7_FR_R (*((volatile unsigned long *)0x40013018)) +#define UART7_ILPR_R (*((volatile unsigned long *)0x40013020)) +#define UART7_IBRD_R (*((volatile unsigned long *)0x40013024)) +#define UART7_FBRD_R (*((volatile unsigned long *)0x40013028)) +#define UART7_LCRH_R (*((volatile unsigned long *)0x4001302C)) +#define UART7_CTL_R (*((volatile unsigned long *)0x40013030)) +#define UART7_IFLS_R (*((volatile unsigned long *)0x40013034)) +#define UART7_IM_R (*((volatile unsigned long *)0x40013038)) +#define UART7_RIS_R (*((volatile unsigned long *)0x4001303C)) +#define UART7_MIS_R (*((volatile unsigned long *)0x40013040)) +#define UART7_ICR_R (*((volatile unsigned long *)0x40013044)) +#define UART7_DMACTL_R (*((volatile unsigned long *)0x40013048)) +#define UART7_LCTL_R (*((volatile unsigned long *)0x40013090)) +#define UART7_LSS_R (*((volatile unsigned long *)0x40013094)) +#define UART7_LTIM_R (*((volatile unsigned long *)0x40013098)) +#define UART7_9BITADDR_R (*((volatile unsigned long *)0x400130A4)) +#define UART7_9BITAMASK_R (*((volatile unsigned long *)0x400130A8)) +#define UART7_PP_R (*((volatile unsigned long *)0x40013FC0)) +#define UART7_CC_R (*((volatile unsigned long *)0x40013FC8)) + +//***************************************************************************** +// +// I2C registers (I2C0 MASTER) +// +//***************************************************************************** +#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000)) +#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004)) +#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008)) +#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C)) +#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010)) +#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014)) +#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018)) +#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C)) +#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020)) +#define I2C0_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40020024)) +#define I2C0_MASTER_MBMON_R (*((volatile unsigned long *)0x4002002C)) + +//***************************************************************************** +// +// I2C registers (I2C0 SLAVE) +// +//***************************************************************************** +#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800)) +#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804)) +#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808)) +#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C)) +#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810)) +#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814)) +#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818)) +#define I2C0_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002081C)) +#define I2C0_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40020820)) + +//***************************************************************************** +// +// I2C registers (I2C1 MASTER) +// +//***************************************************************************** +#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000)) +#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004)) +#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008)) +#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C)) +#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010)) +#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014)) +#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018)) +#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C)) +#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020)) +#define I2C1_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40021024)) +#define I2C1_MASTER_MBMON_R (*((volatile unsigned long *)0x4002102C)) + +//***************************************************************************** +// +// I2C registers (I2C1 SLAVE) +// +//***************************************************************************** +#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800)) +#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804)) +#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808)) +#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C)) +#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810)) +#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814)) +#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818)) +#define I2C1_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002181C)) +#define I2C1_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40021820)) + +//***************************************************************************** +// +// I2C registers (I2C2 MASTER) +// +//***************************************************************************** +#define I2C2_MASTER_MSA_R (*((volatile unsigned long *)0x40022000)) +#define I2C2_MASTER_MCS_R (*((volatile unsigned long *)0x40022004)) +#define I2C2_MASTER_MDR_R (*((volatile unsigned long *)0x40022008)) +#define I2C2_MASTER_MTPR_R (*((volatile unsigned long *)0x4002200C)) +#define I2C2_MASTER_MIMR_R (*((volatile unsigned long *)0x40022010)) +#define I2C2_MASTER_MRIS_R (*((volatile unsigned long *)0x40022014)) +#define I2C2_MASTER_MMIS_R (*((volatile unsigned long *)0x40022018)) +#define I2C2_MASTER_MICR_R (*((volatile unsigned long *)0x4002201C)) +#define I2C2_MASTER_MCR_R (*((volatile unsigned long *)0x40022020)) +#define I2C2_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40022024)) +#define I2C2_MASTER_MBMON_R (*((volatile unsigned long *)0x4002202C)) + +//***************************************************************************** +// +// I2C registers (I2C2 SLAVE) +// +//***************************************************************************** +#define I2C2_SLAVE_SOAR_R (*((volatile unsigned long *)0x40022800)) +#define I2C2_SLAVE_SCSR_R (*((volatile unsigned long *)0x40022804)) +#define I2C2_SLAVE_SDR_R (*((volatile unsigned long *)0x40022808)) +#define I2C2_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002280C)) +#define I2C2_SLAVE_SRIS_R (*((volatile unsigned long *)0x40022810)) +#define I2C2_SLAVE_SMIS_R (*((volatile unsigned long *)0x40022814)) +#define I2C2_SLAVE_SICR_R (*((volatile unsigned long *)0x40022818)) +#define I2C2_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002281C)) +#define I2C2_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40022820)) + +//***************************************************************************** +// +// I2C registers (I2C3 MASTER) +// +//***************************************************************************** +#define I2C3_MASTER_MSA_R (*((volatile unsigned long *)0x40023000)) +#define I2C3_MASTER_MCS_R (*((volatile unsigned long *)0x40023004)) +#define I2C3_MASTER_MDR_R (*((volatile unsigned long *)0x40023008)) +#define I2C3_MASTER_MTPR_R (*((volatile unsigned long *)0x4002300C)) +#define I2C3_MASTER_MIMR_R (*((volatile unsigned long *)0x40023010)) +#define I2C3_MASTER_MRIS_R (*((volatile unsigned long *)0x40023014)) +#define I2C3_MASTER_MMIS_R (*((volatile unsigned long *)0x40023018)) +#define I2C3_MASTER_MICR_R (*((volatile unsigned long *)0x4002301C)) +#define I2C3_MASTER_MCR_R (*((volatile unsigned long *)0x40023020)) +#define I2C3_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40023024)) +#define I2C3_MASTER_MBMON_R (*((volatile unsigned long *)0x4002302C)) + +//***************************************************************************** +// +// I2C registers (I2C3 SLAVE) +// +//***************************************************************************** +#define I2C3_SLAVE_SOAR_R (*((volatile unsigned long *)0x40023800)) +#define I2C3_SLAVE_SCSR_R (*((volatile unsigned long *)0x40023804)) +#define I2C3_SLAVE_SDR_R (*((volatile unsigned long *)0x40023808)) +#define I2C3_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002380C)) +#define I2C3_SLAVE_SRIS_R (*((volatile unsigned long *)0x40023810)) +#define I2C3_SLAVE_SMIS_R (*((volatile unsigned long *)0x40023814)) +#define I2C3_SLAVE_SICR_R (*((volatile unsigned long *)0x40023818)) +#define I2C3_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002381C)) +#define I2C3_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40023820)) + +//***************************************************************************** +// +// GPIO registers (PORTE) +// +//***************************************************************************** +#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000) +#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC)) +#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400)) +#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404)) +#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408)) +#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C)) +#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410)) +#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414)) +#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418)) +#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C)) +#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420)) +#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500)) +#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504)) +#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508)) +#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C)) +#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510)) +#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514)) +#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518)) +#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C)) +#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520)) +#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524)) +#define GPIO_PORTE_AMSEL_R (*((volatile unsigned long *)0x40024528)) +#define GPIO_PORTE_PCTL_R (*((volatile unsigned long *)0x4002452C)) +#define GPIO_PORTE_ADCCTL_R (*((volatile unsigned long *)0x40024530)) +#define GPIO_PORTE_DMACTL_R (*((volatile unsigned long *)0x40024534)) +#define GPIO_PORTE_SI_R (*((volatile unsigned long *)0x40024538)) + +//***************************************************************************** +// +// GPIO registers (PORTF) +// +//***************************************************************************** +#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000) +#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC)) +#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400)) +#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404)) +#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408)) +#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C)) +#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410)) +#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414)) +#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418)) +#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C)) +#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420)) +#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500)) +#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504)) +#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508)) +#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C)) +#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510)) +#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514)) +#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518)) +#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C)) +#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520)) +#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524)) +#define GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528)) +#define GPIO_PORTF_PCTL_R (*((volatile unsigned long *)0x4002552C)) +#define GPIO_PORTF_ADCCTL_R (*((volatile unsigned long *)0x40025530)) +#define GPIO_PORTF_DMACTL_R (*((volatile unsigned long *)0x40025534)) +#define GPIO_PORTF_SI_R (*((volatile unsigned long *)0x40025538)) + +//***************************************************************************** +// +// Timer registers (TIMER0) +// +//***************************************************************************** +#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000)) +#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004)) +#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008)) +#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C)) +#define TIMER0_SYNC_R (*((volatile unsigned long *)0x40030010)) +#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018)) +#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C)) +#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020)) +#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024)) +#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028)) +#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C)) +#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030)) +#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034)) +#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038)) +#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C)) +#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040)) +#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044)) +#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048)) +#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C)) +#define TIMER0_TAV_R (*((volatile unsigned long *)0x40030050)) +#define TIMER0_TBV_R (*((volatile unsigned long *)0x40030054)) +#define TIMER0_RTCPD_R (*((volatile unsigned long *)0x40030058)) +#define TIMER0_TAPS_R (*((volatile unsigned long *)0x4003005C)) +#define TIMER0_TBPS_R (*((volatile unsigned long *)0x40030060)) +#define TIMER0_TAPV_R (*((volatile unsigned long *)0x40030064)) +#define TIMER0_TBPV_R (*((volatile unsigned long *)0x40030068)) +#define TIMER0_PP_R (*((volatile unsigned long *)0x40030FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER1) +// +//***************************************************************************** +#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000)) +#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004)) +#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008)) +#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C)) +#define TIMER1_SYNC_R (*((volatile unsigned long *)0x40031010)) +#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018)) +#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C)) +#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020)) +#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024)) +#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028)) +#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C)) +#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030)) +#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034)) +#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038)) +#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C)) +#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040)) +#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044)) +#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048)) +#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C)) +#define TIMER1_TAV_R (*((volatile unsigned long *)0x40031050)) +#define TIMER1_TBV_R (*((volatile unsigned long *)0x40031054)) +#define TIMER1_RTCPD_R (*((volatile unsigned long *)0x40031058)) +#define TIMER1_TAPS_R (*((volatile unsigned long *)0x4003105C)) +#define TIMER1_TBPS_R (*((volatile unsigned long *)0x40031060)) +#define TIMER1_TAPV_R (*((volatile unsigned long *)0x40031064)) +#define TIMER1_TBPV_R (*((volatile unsigned long *)0x40031068)) +#define TIMER1_PP_R (*((volatile unsigned long *)0x40031FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER2) +// +//***************************************************************************** +#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000)) +#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004)) +#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008)) +#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C)) +#define TIMER2_SYNC_R (*((volatile unsigned long *)0x40032010)) +#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018)) +#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C)) +#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020)) +#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024)) +#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028)) +#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C)) +#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030)) +#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034)) +#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038)) +#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C)) +#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040)) +#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044)) +#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048)) +#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C)) +#define TIMER2_TAV_R (*((volatile unsigned long *)0x40032050)) +#define TIMER2_TBV_R (*((volatile unsigned long *)0x40032054)) +#define TIMER2_RTCPD_R (*((volatile unsigned long *)0x40032058)) +#define TIMER2_TAPS_R (*((volatile unsigned long *)0x4003205C)) +#define TIMER2_TBPS_R (*((volatile unsigned long *)0x40032060)) +#define TIMER2_TAPV_R (*((volatile unsigned long *)0x40032064)) +#define TIMER2_TBPV_R (*((volatile unsigned long *)0x40032068)) +#define TIMER2_PP_R (*((volatile unsigned long *)0x40032FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER3) +// +//***************************************************************************** +#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000)) +#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004)) +#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008)) +#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C)) +#define TIMER3_SYNC_R (*((volatile unsigned long *)0x40033010)) +#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018)) +#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C)) +#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020)) +#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024)) +#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028)) +#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C)) +#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030)) +#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034)) +#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038)) +#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C)) +#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040)) +#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044)) +#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048)) +#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C)) +#define TIMER3_TAV_R (*((volatile unsigned long *)0x40033050)) +#define TIMER3_TBV_R (*((volatile unsigned long *)0x40033054)) +#define TIMER3_RTCPD_R (*((volatile unsigned long *)0x40033058)) +#define TIMER3_TAPS_R (*((volatile unsigned long *)0x4003305C)) +#define TIMER3_TBPS_R (*((volatile unsigned long *)0x40033060)) +#define TIMER3_TAPV_R (*((volatile unsigned long *)0x40033064)) +#define TIMER3_TBPV_R (*((volatile unsigned long *)0x40033068)) +#define TIMER3_PP_R (*((volatile unsigned long *)0x40033FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER4) +// +//***************************************************************************** +#define TIMER4_CFG_R (*((volatile unsigned long *)0x40034000)) +#define TIMER4_TAMR_R (*((volatile unsigned long *)0x40034004)) +#define TIMER4_TBMR_R (*((volatile unsigned long *)0x40034008)) +#define TIMER4_CTL_R (*((volatile unsigned long *)0x4003400C)) +#define TIMER4_SYNC_R (*((volatile unsigned long *)0x40034010)) +#define TIMER4_IMR_R (*((volatile unsigned long *)0x40034018)) +#define TIMER4_RIS_R (*((volatile unsigned long *)0x4003401C)) +#define TIMER4_MIS_R (*((volatile unsigned long *)0x40034020)) +#define TIMER4_ICR_R (*((volatile unsigned long *)0x40034024)) +#define TIMER4_TAILR_R (*((volatile unsigned long *)0x40034028)) +#define TIMER4_TBILR_R (*((volatile unsigned long *)0x4003402C)) +#define TIMER4_TAMATCHR_R (*((volatile unsigned long *)0x40034030)) +#define TIMER4_TBMATCHR_R (*((volatile unsigned long *)0x40034034)) +#define TIMER4_TAPR_R (*((volatile unsigned long *)0x40034038)) +#define TIMER4_TBPR_R (*((volatile unsigned long *)0x4003403C)) +#define TIMER4_TAPMR_R (*((volatile unsigned long *)0x40034040)) +#define TIMER4_TBPMR_R (*((volatile unsigned long *)0x40034044)) +#define TIMER4_TAR_R (*((volatile unsigned long *)0x40034048)) +#define TIMER4_TBR_R (*((volatile unsigned long *)0x4003404C)) +#define TIMER4_TAV_R (*((volatile unsigned long *)0x40034050)) +#define TIMER4_TBV_R (*((volatile unsigned long *)0x40034054)) +#define TIMER4_RTCPD_R (*((volatile unsigned long *)0x40034058)) +#define TIMER4_TAPS_R (*((volatile unsigned long *)0x4003405C)) +#define TIMER4_TBPS_R (*((volatile unsigned long *)0x40034060)) +#define TIMER4_TAPV_R (*((volatile unsigned long *)0x40034064)) +#define TIMER4_TBPV_R (*((volatile unsigned long *)0x40034068)) +#define TIMER4_PP_R (*((volatile unsigned long *)0x40034FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER5) +// +//***************************************************************************** +#define TIMER5_CFG_R (*((volatile unsigned long *)0x40035000)) +#define TIMER5_TAMR_R (*((volatile unsigned long *)0x40035004)) +#define TIMER5_TBMR_R (*((volatile unsigned long *)0x40035008)) +#define TIMER5_CTL_R (*((volatile unsigned long *)0x4003500C)) +#define TIMER5_SYNC_R (*((volatile unsigned long *)0x40035010)) +#define TIMER5_IMR_R (*((volatile unsigned long *)0x40035018)) +#define TIMER5_RIS_R (*((volatile unsigned long *)0x4003501C)) +#define TIMER5_MIS_R (*((volatile unsigned long *)0x40035020)) +#define TIMER5_ICR_R (*((volatile unsigned long *)0x40035024)) +#define TIMER5_TAILR_R (*((volatile unsigned long *)0x40035028)) +#define TIMER5_TBILR_R (*((volatile unsigned long *)0x4003502C)) +#define TIMER5_TAMATCHR_R (*((volatile unsigned long *)0x40035030)) +#define TIMER5_TBMATCHR_R (*((volatile unsigned long *)0x40035034)) +#define TIMER5_TAPR_R (*((volatile unsigned long *)0x40035038)) +#define TIMER5_TBPR_R (*((volatile unsigned long *)0x4003503C)) +#define TIMER5_TAPMR_R (*((volatile unsigned long *)0x40035040)) +#define TIMER5_TBPMR_R (*((volatile unsigned long *)0x40035044)) +#define TIMER5_TAR_R (*((volatile unsigned long *)0x40035048)) +#define TIMER5_TBR_R (*((volatile unsigned long *)0x4003504C)) +#define TIMER5_TAV_R (*((volatile unsigned long *)0x40035050)) +#define TIMER5_TBV_R (*((volatile unsigned long *)0x40035054)) +#define TIMER5_RTCPD_R (*((volatile unsigned long *)0x40035058)) +#define TIMER5_TAPS_R (*((volatile unsigned long *)0x4003505C)) +#define TIMER5_TBPS_R (*((volatile unsigned long *)0x40035060)) +#define TIMER5_TAPV_R (*((volatile unsigned long *)0x40035064)) +#define TIMER5_TBPV_R (*((volatile unsigned long *)0x40035068)) +#define TIMER5_PP_R (*((volatile unsigned long *)0x40035FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER0) +// +//***************************************************************************** +#define WTIMER0_CFG_R (*((volatile unsigned long *)0x40036000)) +#define WTIMER0_TAMR_R (*((volatile unsigned long *)0x40036004)) +#define WTIMER0_TBMR_R (*((volatile unsigned long *)0x40036008)) +#define WTIMER0_CTL_R (*((volatile unsigned long *)0x4003600C)) +#define WTIMER0_SYNC_R (*((volatile unsigned long *)0x40036010)) +#define WTIMER0_IMR_R (*((volatile unsigned long *)0x40036018)) +#define WTIMER0_RIS_R (*((volatile unsigned long *)0x4003601C)) +#define WTIMER0_MIS_R (*((volatile unsigned long *)0x40036020)) +#define WTIMER0_ICR_R (*((volatile unsigned long *)0x40036024)) +#define WTIMER0_TAILR_R (*((volatile unsigned long *)0x40036028)) +#define WTIMER0_TBILR_R (*((volatile unsigned long *)0x4003602C)) +#define WTIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40036030)) +#define WTIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40036034)) +#define WTIMER0_TAPR_R (*((volatile unsigned long *)0x40036038)) +#define WTIMER0_TBPR_R (*((volatile unsigned long *)0x4003603C)) +#define WTIMER0_TAPMR_R (*((volatile unsigned long *)0x40036040)) +#define WTIMER0_TBPMR_R (*((volatile unsigned long *)0x40036044)) +#define WTIMER0_TAR_R (*((volatile unsigned long *)0x40036048)) +#define WTIMER0_TBR_R (*((volatile unsigned long *)0x4003604C)) +#define WTIMER0_TAV_R (*((volatile unsigned long *)0x40036050)) +#define WTIMER0_TBV_R (*((volatile unsigned long *)0x40036054)) +#define WTIMER0_RTCPD_R (*((volatile unsigned long *)0x40036058)) +#define WTIMER0_TAPS_R (*((volatile unsigned long *)0x4003605C)) +#define WTIMER0_TBPS_R (*((volatile unsigned long *)0x40036060)) +#define WTIMER0_TAPV_R (*((volatile unsigned long *)0x40036064)) +#define WTIMER0_TBPV_R (*((volatile unsigned long *)0x40036068)) +#define WTIMER0_PP_R (*((volatile unsigned long *)0x40036FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER1) +// +//***************************************************************************** +#define WTIMER1_CFG_R (*((volatile unsigned long *)0x40037000)) +#define WTIMER1_TAMR_R (*((volatile unsigned long *)0x40037004)) +#define WTIMER1_TBMR_R (*((volatile unsigned long *)0x40037008)) +#define WTIMER1_CTL_R (*((volatile unsigned long *)0x4003700C)) +#define WTIMER1_SYNC_R (*((volatile unsigned long *)0x40037010)) +#define WTIMER1_IMR_R (*((volatile unsigned long *)0x40037018)) +#define WTIMER1_RIS_R (*((volatile unsigned long *)0x4003701C)) +#define WTIMER1_MIS_R (*((volatile unsigned long *)0x40037020)) +#define WTIMER1_ICR_R (*((volatile unsigned long *)0x40037024)) +#define WTIMER1_TAILR_R (*((volatile unsigned long *)0x40037028)) +#define WTIMER1_TBILR_R (*((volatile unsigned long *)0x4003702C)) +#define WTIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40037030)) +#define WTIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40037034)) +#define WTIMER1_TAPR_R (*((volatile unsigned long *)0x40037038)) +#define WTIMER1_TBPR_R (*((volatile unsigned long *)0x4003703C)) +#define WTIMER1_TAPMR_R (*((volatile unsigned long *)0x40037040)) +#define WTIMER1_TBPMR_R (*((volatile unsigned long *)0x40037044)) +#define WTIMER1_TAR_R (*((volatile unsigned long *)0x40037048)) +#define WTIMER1_TBR_R (*((volatile unsigned long *)0x4003704C)) +#define WTIMER1_TAV_R (*((volatile unsigned long *)0x40037050)) +#define WTIMER1_TBV_R (*((volatile unsigned long *)0x40037054)) +#define WTIMER1_RTCPD_R (*((volatile unsigned long *)0x40037058)) +#define WTIMER1_TAPS_R (*((volatile unsigned long *)0x4003705C)) +#define WTIMER1_TBPS_R (*((volatile unsigned long *)0x40037060)) +#define WTIMER1_TAPV_R (*((volatile unsigned long *)0x40037064)) +#define WTIMER1_TBPV_R (*((volatile unsigned long *)0x40037068)) +#define WTIMER1_PP_R (*((volatile unsigned long *)0x40037FC0)) + +//***************************************************************************** +// +// ADC registers (ADC0) +// +//***************************************************************************** +#define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000)) +#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004)) +#define ADC0_IM_R (*((volatile unsigned long *)0x40038008)) +#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C)) +#define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010)) +#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014)) +#define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018)) +#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020)) +#define ADC0_SPC_R (*((volatile unsigned long *)0x40038024)) +#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028)) +#define ADC0_SAC_R (*((volatile unsigned long *)0x40038030)) +#define ADC0_DCISC_R (*((volatile unsigned long *)0x40038034)) +#define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040)) +#define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044)) +#define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048)) +#define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C)) +#define ADC0_SSOP0_R (*((volatile unsigned long *)0x40038050)) +#define ADC0_SSDC0_R (*((volatile unsigned long *)0x40038054)) +#define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060)) +#define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064)) +#define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068)) +#define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C)) +#define ADC0_SSOP1_R (*((volatile unsigned long *)0x40038070)) +#define ADC0_SSDC1_R (*((volatile unsigned long *)0x40038074)) +#define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080)) +#define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084)) +#define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088)) +#define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C)) +#define ADC0_SSOP2_R (*((volatile unsigned long *)0x40038090)) +#define ADC0_SSDC2_R (*((volatile unsigned long *)0x40038094)) +#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0)) +#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4)) +#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8)) +#define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC)) +#define ADC0_SSOP3_R (*((volatile unsigned long *)0x400380B0)) +#define ADC0_SSDC3_R (*((volatile unsigned long *)0x400380B4)) +#define ADC0_DCRIC_R (*((volatile unsigned long *)0x40038D00)) +#define ADC0_DCCTL0_R (*((volatile unsigned long *)0x40038E00)) +#define ADC0_DCCTL1_R (*((volatile unsigned long *)0x40038E04)) +#define ADC0_DCCTL2_R (*((volatile unsigned long *)0x40038E08)) +#define ADC0_DCCTL3_R (*((volatile unsigned long *)0x40038E0C)) +#define ADC0_DCCTL4_R (*((volatile unsigned long *)0x40038E10)) +#define ADC0_DCCTL5_R (*((volatile unsigned long *)0x40038E14)) +#define ADC0_DCCTL6_R (*((volatile unsigned long *)0x40038E18)) +#define ADC0_DCCTL7_R (*((volatile unsigned long *)0x40038E1C)) +#define ADC0_DCCMP0_R (*((volatile unsigned long *)0x40038E40)) +#define ADC0_DCCMP1_R (*((volatile unsigned long *)0x40038E44)) +#define ADC0_DCCMP2_R (*((volatile unsigned long *)0x40038E48)) +#define ADC0_DCCMP3_R (*((volatile unsigned long *)0x40038E4C)) +#define ADC0_DCCMP4_R (*((volatile unsigned long *)0x40038E50)) +#define ADC0_DCCMP5_R (*((volatile unsigned long *)0x40038E54)) +#define ADC0_DCCMP6_R (*((volatile unsigned long *)0x40038E58)) +#define ADC0_DCCMP7_R (*((volatile unsigned long *)0x40038E5C)) +#define ADC0_PP_R (*((volatile unsigned long *)0x40038FC0)) +#define ADC0_PC_R (*((volatile unsigned long *)0x40038FC4)) +#define ADC0_CC_R (*((volatile unsigned long *)0x40038FC8)) + +//***************************************************************************** +// +// ADC registers (ADC1) +// +//***************************************************************************** +#define ADC1_ACTSS_R (*((volatile unsigned long *)0x40039000)) +#define ADC1_RIS_R (*((volatile unsigned long *)0x40039004)) +#define ADC1_IM_R (*((volatile unsigned long *)0x40039008)) +#define ADC1_ISC_R (*((volatile unsigned long *)0x4003900C)) +#define ADC1_OSTAT_R (*((volatile unsigned long *)0x40039010)) +#define ADC1_EMUX_R (*((volatile unsigned long *)0x40039014)) +#define ADC1_USTAT_R (*((volatile unsigned long *)0x40039018)) +#define ADC1_SSPRI_R (*((volatile unsigned long *)0x40039020)) +#define ADC1_SPC_R (*((volatile unsigned long *)0x40039024)) +#define ADC1_PSSI_R (*((volatile unsigned long *)0x40039028)) +#define ADC1_SAC_R (*((volatile unsigned long *)0x40039030)) +#define ADC1_DCISC_R (*((volatile unsigned long *)0x40039034)) +#define ADC1_SSMUX0_R (*((volatile unsigned long *)0x40039040)) +#define ADC1_SSCTL0_R (*((volatile unsigned long *)0x40039044)) +#define ADC1_SSFIFO0_R (*((volatile unsigned long *)0x40039048)) +#define ADC1_SSFSTAT0_R (*((volatile unsigned long *)0x4003904C)) +#define ADC1_SSOP0_R (*((volatile unsigned long *)0x40039050)) +#define ADC1_SSDC0_R (*((volatile unsigned long *)0x40039054)) +#define ADC1_SSMUX1_R (*((volatile unsigned long *)0x40039060)) +#define ADC1_SSCTL1_R (*((volatile unsigned long *)0x40039064)) +#define ADC1_SSFIFO1_R (*((volatile unsigned long *)0x40039068)) +#define ADC1_SSFSTAT1_R (*((volatile unsigned long *)0x4003906C)) +#define ADC1_SSOP1_R (*((volatile unsigned long *)0x40039070)) +#define ADC1_SSDC1_R (*((volatile unsigned long *)0x40039074)) +#define ADC1_SSMUX2_R (*((volatile unsigned long *)0x40039080)) +#define ADC1_SSCTL2_R (*((volatile unsigned long *)0x40039084)) +#define ADC1_SSFIFO2_R (*((volatile unsigned long *)0x40039088)) +#define ADC1_SSFSTAT2_R (*((volatile unsigned long *)0x4003908C)) +#define ADC1_SSOP2_R (*((volatile unsigned long *)0x40039090)) +#define ADC1_SSDC2_R (*((volatile unsigned long *)0x40039094)) +#define ADC1_SSMUX3_R (*((volatile unsigned long *)0x400390A0)) +#define ADC1_SSCTL3_R (*((volatile unsigned long *)0x400390A4)) +#define ADC1_SSFIFO3_R (*((volatile unsigned long *)0x400390A8)) +#define ADC1_SSFSTAT3_R (*((volatile unsigned long *)0x400390AC)) +#define ADC1_SSOP3_R (*((volatile unsigned long *)0x400390B0)) +#define ADC1_SSDC3_R (*((volatile unsigned long *)0x400390B4)) +#define ADC1_DCRIC_R (*((volatile unsigned long *)0x40039D00)) +#define ADC1_DCCTL0_R (*((volatile unsigned long *)0x40039E00)) +#define ADC1_DCCTL1_R (*((volatile unsigned long *)0x40039E04)) +#define ADC1_DCCTL2_R (*((volatile unsigned long *)0x40039E08)) +#define ADC1_DCCTL3_R (*((volatile unsigned long *)0x40039E0C)) +#define ADC1_DCCTL4_R (*((volatile unsigned long *)0x40039E10)) +#define ADC1_DCCTL5_R (*((volatile unsigned long *)0x40039E14)) +#define ADC1_DCCTL6_R (*((volatile unsigned long *)0x40039E18)) +#define ADC1_DCCTL7_R (*((volatile unsigned long *)0x40039E1C)) +#define ADC1_DCCMP0_R (*((volatile unsigned long *)0x40039E40)) +#define ADC1_DCCMP1_R (*((volatile unsigned long *)0x40039E44)) +#define ADC1_DCCMP2_R (*((volatile unsigned long *)0x40039E48)) +#define ADC1_DCCMP3_R (*((volatile unsigned long *)0x40039E4C)) +#define ADC1_DCCMP4_R (*((volatile unsigned long *)0x40039E50)) +#define ADC1_DCCMP5_R (*((volatile unsigned long *)0x40039E54)) +#define ADC1_DCCMP6_R (*((volatile unsigned long *)0x40039E58)) +#define ADC1_DCCMP7_R (*((volatile unsigned long *)0x40039E5C)) +#define ADC1_PP_R (*((volatile unsigned long *)0x40039FC0)) +#define ADC1_PC_R (*((volatile unsigned long *)0x40039FC4)) +#define ADC1_CC_R (*((volatile unsigned long *)0x40039FC8)) + +//***************************************************************************** +// +// Comparator registers (COMP) +// +//***************************************************************************** +#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000)) +#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004)) +#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008)) +#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010)) +#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020)) +#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024)) +#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040)) +#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044)) +#define COMP_PP_R (*((volatile unsigned long *)0x4003CFC0)) + +//***************************************************************************** +// +// CAN registers (CAN0) +// +//***************************************************************************** +#define CAN0_CTL_R (*((volatile unsigned long *)0x40040000)) +#define CAN0_STS_R (*((volatile unsigned long *)0x40040004)) +#define CAN0_ERR_R (*((volatile unsigned long *)0x40040008)) +#define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C)) +#define CAN0_INT_R (*((volatile unsigned long *)0x40040010)) +#define CAN0_TST_R (*((volatile unsigned long *)0x40040014)) +#define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018)) +#define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020)) +#define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024)) +#define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028)) +#define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C)) +#define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030)) +#define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034)) +#define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038)) +#define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C)) +#define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040)) +#define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044)) +#define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048)) +#define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080)) +#define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084)) +#define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088)) +#define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C)) +#define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090)) +#define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094)) +#define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098)) +#define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C)) +#define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0)) +#define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4)) +#define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8)) +#define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100)) +#define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104)) +#define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120)) +#define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124)) +#define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140)) +#define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144)) +#define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160)) +#define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164)) + +//***************************************************************************** +// +// Timer registers (WTIMER2) +// +//***************************************************************************** +#define WTIMER2_CFG_R (*((volatile unsigned long *)0x4004C000)) +#define WTIMER2_TAMR_R (*((volatile unsigned long *)0x4004C004)) +#define WTIMER2_TBMR_R (*((volatile unsigned long *)0x4004C008)) +#define WTIMER2_CTL_R (*((volatile unsigned long *)0x4004C00C)) +#define WTIMER2_SYNC_R (*((volatile unsigned long *)0x4004C010)) +#define WTIMER2_IMR_R (*((volatile unsigned long *)0x4004C018)) +#define WTIMER2_RIS_R (*((volatile unsigned long *)0x4004C01C)) +#define WTIMER2_MIS_R (*((volatile unsigned long *)0x4004C020)) +#define WTIMER2_ICR_R (*((volatile unsigned long *)0x4004C024)) +#define WTIMER2_TAILR_R (*((volatile unsigned long *)0x4004C028)) +#define WTIMER2_TBILR_R (*((volatile unsigned long *)0x4004C02C)) +#define WTIMER2_TAMATCHR_R (*((volatile unsigned long *)0x4004C030)) +#define WTIMER2_TBMATCHR_R (*((volatile unsigned long *)0x4004C034)) +#define WTIMER2_TAPR_R (*((volatile unsigned long *)0x4004C038)) +#define WTIMER2_TBPR_R (*((volatile unsigned long *)0x4004C03C)) +#define WTIMER2_TAPMR_R (*((volatile unsigned long *)0x4004C040)) +#define WTIMER2_TBPMR_R (*((volatile unsigned long *)0x4004C044)) +#define WTIMER2_TAR_R (*((volatile unsigned long *)0x4004C048)) +#define WTIMER2_TBR_R (*((volatile unsigned long *)0x4004C04C)) +#define WTIMER2_TAV_R (*((volatile unsigned long *)0x4004C050)) +#define WTIMER2_TBV_R (*((volatile unsigned long *)0x4004C054)) +#define WTIMER2_RTCPD_R (*((volatile unsigned long *)0x4004C058)) +#define WTIMER2_TAPS_R (*((volatile unsigned long *)0x4004C05C)) +#define WTIMER2_TBPS_R (*((volatile unsigned long *)0x4004C060)) +#define WTIMER2_TAPV_R (*((volatile unsigned long *)0x4004C064)) +#define WTIMER2_TBPV_R (*((volatile unsigned long *)0x4004C068)) +#define WTIMER2_PP_R (*((volatile unsigned long *)0x4004CFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER3) +// +//***************************************************************************** +#define WTIMER3_CFG_R (*((volatile unsigned long *)0x4004D000)) +#define WTIMER3_TAMR_R (*((volatile unsigned long *)0x4004D004)) +#define WTIMER3_TBMR_R (*((volatile unsigned long *)0x4004D008)) +#define WTIMER3_CTL_R (*((volatile unsigned long *)0x4004D00C)) +#define WTIMER3_SYNC_R (*((volatile unsigned long *)0x4004D010)) +#define WTIMER3_IMR_R (*((volatile unsigned long *)0x4004D018)) +#define WTIMER3_RIS_R (*((volatile unsigned long *)0x4004D01C)) +#define WTIMER3_MIS_R (*((volatile unsigned long *)0x4004D020)) +#define WTIMER3_ICR_R (*((volatile unsigned long *)0x4004D024)) +#define WTIMER3_TAILR_R (*((volatile unsigned long *)0x4004D028)) +#define WTIMER3_TBILR_R (*((volatile unsigned long *)0x4004D02C)) +#define WTIMER3_TAMATCHR_R (*((volatile unsigned long *)0x4004D030)) +#define WTIMER3_TBMATCHR_R (*((volatile unsigned long *)0x4004D034)) +#define WTIMER3_TAPR_R (*((volatile unsigned long *)0x4004D038)) +#define WTIMER3_TBPR_R (*((volatile unsigned long *)0x4004D03C)) +#define WTIMER3_TAPMR_R (*((volatile unsigned long *)0x4004D040)) +#define WTIMER3_TBPMR_R (*((volatile unsigned long *)0x4004D044)) +#define WTIMER3_TAR_R (*((volatile unsigned long *)0x4004D048)) +#define WTIMER3_TBR_R (*((volatile unsigned long *)0x4004D04C)) +#define WTIMER3_TAV_R (*((volatile unsigned long *)0x4004D050)) +#define WTIMER3_TBV_R (*((volatile unsigned long *)0x4004D054)) +#define WTIMER3_RTCPD_R (*((volatile unsigned long *)0x4004D058)) +#define WTIMER3_TAPS_R (*((volatile unsigned long *)0x4004D05C)) +#define WTIMER3_TBPS_R (*((volatile unsigned long *)0x4004D060)) +#define WTIMER3_TAPV_R (*((volatile unsigned long *)0x4004D064)) +#define WTIMER3_TBPV_R (*((volatile unsigned long *)0x4004D068)) +#define WTIMER3_PP_R (*((volatile unsigned long *)0x4004DFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER4) +// +//***************************************************************************** +#define WTIMER4_CFG_R (*((volatile unsigned long *)0x4004E000)) +#define WTIMER4_TAMR_R (*((volatile unsigned long *)0x4004E004)) +#define WTIMER4_TBMR_R (*((volatile unsigned long *)0x4004E008)) +#define WTIMER4_CTL_R (*((volatile unsigned long *)0x4004E00C)) +#define WTIMER4_SYNC_R (*((volatile unsigned long *)0x4004E010)) +#define WTIMER4_IMR_R (*((volatile unsigned long *)0x4004E018)) +#define WTIMER4_RIS_R (*((volatile unsigned long *)0x4004E01C)) +#define WTIMER4_MIS_R (*((volatile unsigned long *)0x4004E020)) +#define WTIMER4_ICR_R (*((volatile unsigned long *)0x4004E024)) +#define WTIMER4_TAILR_R (*((volatile unsigned long *)0x4004E028)) +#define WTIMER4_TBILR_R (*((volatile unsigned long *)0x4004E02C)) +#define WTIMER4_TAMATCHR_R (*((volatile unsigned long *)0x4004E030)) +#define WTIMER4_TBMATCHR_R (*((volatile unsigned long *)0x4004E034)) +#define WTIMER4_TAPR_R (*((volatile unsigned long *)0x4004E038)) +#define WTIMER4_TBPR_R (*((volatile unsigned long *)0x4004E03C)) +#define WTIMER4_TAPMR_R (*((volatile unsigned long *)0x4004E040)) +#define WTIMER4_TBPMR_R (*((volatile unsigned long *)0x4004E044)) +#define WTIMER4_TAR_R (*((volatile unsigned long *)0x4004E048)) +#define WTIMER4_TBR_R (*((volatile unsigned long *)0x4004E04C)) +#define WTIMER4_TAV_R (*((volatile unsigned long *)0x4004E050)) +#define WTIMER4_TBV_R (*((volatile unsigned long *)0x4004E054)) +#define WTIMER4_RTCPD_R (*((volatile unsigned long *)0x4004E058)) +#define WTIMER4_TAPS_R (*((volatile unsigned long *)0x4004E05C)) +#define WTIMER4_TBPS_R (*((volatile unsigned long *)0x4004E060)) +#define WTIMER4_TAPV_R (*((volatile unsigned long *)0x4004E064)) +#define WTIMER4_TBPV_R (*((volatile unsigned long *)0x4004E068)) +#define WTIMER4_PP_R (*((volatile unsigned long *)0x4004EFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER5) +// +//***************************************************************************** +#define WTIMER5_CFG_R (*((volatile unsigned long *)0x4004F000)) +#define WTIMER5_TAMR_R (*((volatile unsigned long *)0x4004F004)) +#define WTIMER5_TBMR_R (*((volatile unsigned long *)0x4004F008)) +#define WTIMER5_CTL_R (*((volatile unsigned long *)0x4004F00C)) +#define WTIMER5_SYNC_R (*((volatile unsigned long *)0x4004F010)) +#define WTIMER5_IMR_R (*((volatile unsigned long *)0x4004F018)) +#define WTIMER5_RIS_R (*((volatile unsigned long *)0x4004F01C)) +#define WTIMER5_MIS_R (*((volatile unsigned long *)0x4004F020)) +#define WTIMER5_ICR_R (*((volatile unsigned long *)0x4004F024)) +#define WTIMER5_TAILR_R (*((volatile unsigned long *)0x4004F028)) +#define WTIMER5_TBILR_R (*((volatile unsigned long *)0x4004F02C)) +#define WTIMER5_TAMATCHR_R (*((volatile unsigned long *)0x4004F030)) +#define WTIMER5_TBMATCHR_R (*((volatile unsigned long *)0x4004F034)) +#define WTIMER5_TAPR_R (*((volatile unsigned long *)0x4004F038)) +#define WTIMER5_TBPR_R (*((volatile unsigned long *)0x4004F03C)) +#define WTIMER5_TAPMR_R (*((volatile unsigned long *)0x4004F040)) +#define WTIMER5_TBPMR_R (*((volatile unsigned long *)0x4004F044)) +#define WTIMER5_TAR_R (*((volatile unsigned long *)0x4004F048)) +#define WTIMER5_TBR_R (*((volatile unsigned long *)0x4004F04C)) +#define WTIMER5_TAV_R (*((volatile unsigned long *)0x4004F050)) +#define WTIMER5_TBV_R (*((volatile unsigned long *)0x4004F054)) +#define WTIMER5_RTCPD_R (*((volatile unsigned long *)0x4004F058)) +#define WTIMER5_TAPS_R (*((volatile unsigned long *)0x4004F05C)) +#define WTIMER5_TBPS_R (*((volatile unsigned long *)0x4004F060)) +#define WTIMER5_TAPV_R (*((volatile unsigned long *)0x4004F064)) +#define WTIMER5_TBPV_R (*((volatile unsigned long *)0x4004F068)) +#define WTIMER5_PP_R (*((volatile unsigned long *)0x4004FFC0)) + +//***************************************************************************** +// +// Univeral Serial Bus registers (USB0) +// +//***************************************************************************** +#define USB0_FADDR_R (*((volatile unsigned char *)0x40050000)) +#define USB0_POWER_R (*((volatile unsigned char *)0x40050001)) +#define USB0_TXIS_R (*((volatile unsigned short *)0x40050002)) +#define USB0_RXIS_R (*((volatile unsigned short *)0x40050004)) +#define USB0_TXIE_R (*((volatile unsigned short *)0x40050006)) +#define USB0_RXIE_R (*((volatile unsigned short *)0x40050008)) +#define USB0_IS_R (*((volatile unsigned char *)0x4005000A)) +#define USB0_IE_R (*((volatile unsigned char *)0x4005000B)) +#define USB0_FRAME_R (*((volatile unsigned short *)0x4005000C)) +#define USB0_EPIDX_R (*((volatile unsigned char *)0x4005000E)) +#define USB0_TEST_R (*((volatile unsigned char *)0x4005000F)) +#define USB0_FIFO0_R (*((volatile unsigned long *)0x40050020)) +#define USB0_FIFO1_R (*((volatile unsigned long *)0x40050024)) +#define USB0_FIFO2_R (*((volatile unsigned long *)0x40050028)) +#define USB0_FIFO3_R (*((volatile unsigned long *)0x4005002C)) +#define USB0_FIFO4_R (*((volatile unsigned long *)0x40050030)) +#define USB0_FIFO5_R (*((volatile unsigned long *)0x40050034)) +#define USB0_FIFO6_R (*((volatile unsigned long *)0x40050038)) +#define USB0_FIFO7_R (*((volatile unsigned long *)0x4005003C)) +#define USB0_TXFIFOSZ_R (*((volatile unsigned char *)0x40050062)) +#define USB0_RXFIFOSZ_R (*((volatile unsigned char *)0x40050063)) +#define USB0_TXFIFOADD_R (*((volatile unsigned short *)0x40050064)) +#define USB0_RXFIFOADD_R (*((volatile unsigned short *)0x40050066)) +#define USB0_CONTIM_R (*((volatile unsigned char *)0x4005007A)) +#define USB0_FSEOF_R (*((volatile unsigned char *)0x4005007D)) +#define USB0_LSEOF_R (*((volatile unsigned char *)0x4005007E)) +#define USB0_CSRL0_R (*((volatile unsigned char *)0x40050102)) +#define USB0_CSRH0_R (*((volatile unsigned char *)0x40050103)) +#define USB0_COUNT0_R (*((volatile unsigned char *)0x40050108)) +#define USB0_TXMAXP1_R (*((volatile unsigned short *)0x40050110)) +#define USB0_TXCSRL1_R (*((volatile unsigned char *)0x40050112)) +#define USB0_TXCSRH1_R (*((volatile unsigned char *)0x40050113)) +#define USB0_RXMAXP1_R (*((volatile unsigned short *)0x40050114)) +#define USB0_RXCSRL1_R (*((volatile unsigned char *)0x40050116)) +#define USB0_RXCSRH1_R (*((volatile unsigned char *)0x40050117)) +#define USB0_RXCOUNT1_R (*((volatile unsigned short *)0x40050118)) +#define USB0_TXMAXP2_R (*((volatile unsigned short *)0x40050120)) +#define USB0_TXCSRL2_R (*((volatile unsigned char *)0x40050122)) +#define USB0_TXCSRH2_R (*((volatile unsigned char *)0x40050123)) +#define USB0_RXMAXP2_R (*((volatile unsigned short *)0x40050124)) +#define USB0_RXCSRL2_R (*((volatile unsigned char *)0x40050126)) +#define USB0_RXCSRH2_R (*((volatile unsigned char *)0x40050127)) +#define USB0_RXCOUNT2_R (*((volatile unsigned short *)0x40050128)) +#define USB0_TXMAXP3_R (*((volatile unsigned short *)0x40050130)) +#define USB0_TXCSRL3_R (*((volatile unsigned char *)0x40050132)) +#define USB0_TXCSRH3_R (*((volatile unsigned char *)0x40050133)) +#define USB0_RXMAXP3_R (*((volatile unsigned short *)0x40050134)) +#define USB0_RXCSRL3_R (*((volatile unsigned char *)0x40050136)) +#define USB0_RXCSRH3_R (*((volatile unsigned char *)0x40050137)) +#define USB0_RXCOUNT3_R (*((volatile unsigned short *)0x40050138)) +#define USB0_TXMAXP4_R (*((volatile unsigned short *)0x40050140)) +#define USB0_TXCSRL4_R (*((volatile unsigned char *)0x40050142)) +#define USB0_TXCSRH4_R (*((volatile unsigned char *)0x40050143)) +#define USB0_RXMAXP4_R (*((volatile unsigned short *)0x40050144)) +#define USB0_RXCSRL4_R (*((volatile unsigned char *)0x40050146)) +#define USB0_RXCSRH4_R (*((volatile unsigned char *)0x40050147)) +#define USB0_RXCOUNT4_R (*((volatile unsigned short *)0x40050148)) +#define USB0_TXMAXP5_R (*((volatile unsigned short *)0x40050150)) +#define USB0_TXCSRL5_R (*((volatile unsigned char *)0x40050152)) +#define USB0_TXCSRH5_R (*((volatile unsigned char *)0x40050153)) +#define USB0_RXMAXP5_R (*((volatile unsigned short *)0x40050154)) +#define USB0_RXCSRL5_R (*((volatile unsigned char *)0x40050156)) +#define USB0_RXCSRH5_R (*((volatile unsigned char *)0x40050157)) +#define USB0_RXCOUNT5_R (*((volatile unsigned short *)0x40050158)) +#define USB0_TXMAXP6_R (*((volatile unsigned short *)0x40050160)) +#define USB0_TXCSRL6_R (*((volatile unsigned char *)0x40050162)) +#define USB0_TXCSRH6_R (*((volatile unsigned char *)0x40050163)) +#define USB0_RXMAXP6_R (*((volatile unsigned short *)0x40050164)) +#define USB0_RXCSRL6_R (*((volatile unsigned char *)0x40050166)) +#define USB0_RXCSRH6_R (*((volatile unsigned char *)0x40050167)) +#define USB0_RXCOUNT6_R (*((volatile unsigned short *)0x40050168)) +#define USB0_TXMAXP7_R (*((volatile unsigned short *)0x40050170)) +#define USB0_TXCSRL7_R (*((volatile unsigned char *)0x40050172)) +#define USB0_TXCSRH7_R (*((volatile unsigned char *)0x40050173)) +#define USB0_RXMAXP7_R (*((volatile unsigned short *)0x40050174)) +#define USB0_RXCSRL7_R (*((volatile unsigned char *)0x40050176)) +#define USB0_RXCSRH7_R (*((volatile unsigned char *)0x40050177)) +#define USB0_RXCOUNT7_R (*((volatile unsigned short *)0x40050178)) +#define USB0_RXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050340)) +#define USB0_TXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050342)) +#define USB0_DRRIS_R (*((volatile unsigned long *)0x40050410)) +#define USB0_DRIM_R (*((volatile unsigned long *)0x40050414)) +#define USB0_DRISC_R (*((volatile unsigned long *)0x40050418)) +#define USB0_DMASEL_R (*((volatile unsigned long *)0x40050450)) +#define USB0_PP_R (*((volatile unsigned long *)0x40050FC0)) + +//***************************************************************************** +// +// GPIO registers (PORTA AHB) +// +//***************************************************************************** +#define GPIO_PORTA_AHB_DATA_BITS_R \ + ((volatile unsigned long *)0x40058000) +#define GPIO_PORTA_AHB_DATA_R (*((volatile unsigned long *)0x400583FC)) +#define GPIO_PORTA_AHB_DIR_R (*((volatile unsigned long *)0x40058400)) +#define GPIO_PORTA_AHB_IS_R (*((volatile unsigned long *)0x40058404)) +#define GPIO_PORTA_AHB_IBE_R (*((volatile unsigned long *)0x40058408)) +#define GPIO_PORTA_AHB_IEV_R (*((volatile unsigned long *)0x4005840C)) +#define GPIO_PORTA_AHB_IM_R (*((volatile unsigned long *)0x40058410)) +#define GPIO_PORTA_AHB_RIS_R (*((volatile unsigned long *)0x40058414)) +#define GPIO_PORTA_AHB_MIS_R (*((volatile unsigned long *)0x40058418)) +#define GPIO_PORTA_AHB_ICR_R (*((volatile unsigned long *)0x4005841C)) +#define GPIO_PORTA_AHB_AFSEL_R (*((volatile unsigned long *)0x40058420)) +#define GPIO_PORTA_AHB_DR2R_R (*((volatile unsigned long *)0x40058500)) +#define GPIO_PORTA_AHB_DR4R_R (*((volatile unsigned long *)0x40058504)) +#define GPIO_PORTA_AHB_DR8R_R (*((volatile unsigned long *)0x40058508)) +#define GPIO_PORTA_AHB_ODR_R (*((volatile unsigned long *)0x4005850C)) +#define GPIO_PORTA_AHB_PUR_R (*((volatile unsigned long *)0x40058510)) +#define GPIO_PORTA_AHB_PDR_R (*((volatile unsigned long *)0x40058514)) +#define GPIO_PORTA_AHB_SLR_R (*((volatile unsigned long *)0x40058518)) +#define GPIO_PORTA_AHB_DEN_R (*((volatile unsigned long *)0x4005851C)) +#define GPIO_PORTA_AHB_LOCK_R (*((volatile unsigned long *)0x40058520)) +#define GPIO_PORTA_AHB_CR_R (*((volatile unsigned long *)0x40058524)) +#define GPIO_PORTA_AHB_AMSEL_R (*((volatile unsigned long *)0x40058528)) +#define GPIO_PORTA_AHB_PCTL_R (*((volatile unsigned long *)0x4005852C)) +#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile unsigned long *)0x40058530)) +#define GPIO_PORTA_AHB_DMACTL_R (*((volatile unsigned long *)0x40058534)) +#define GPIO_PORTA_AHB_SI_R (*((volatile unsigned long *)0x40058538)) + +//***************************************************************************** +// +// GPIO registers (PORTB AHB) +// +//***************************************************************************** +#define GPIO_PORTB_AHB_DATA_BITS_R \ + ((volatile unsigned long *)0x40059000) +#define GPIO_PORTB_AHB_DATA_R (*((volatile unsigned long *)0x400593FC)) +#define GPIO_PORTB_AHB_DIR_R (*((volatile unsigned long *)0x40059400)) +#define GPIO_PORTB_AHB_IS_R (*((volatile unsigned long *)0x40059404)) +#define GPIO_PORTB_AHB_IBE_R (*((volatile unsigned long *)0x40059408)) +#define GPIO_PORTB_AHB_IEV_R (*((volatile unsigned long *)0x4005940C)) +#define GPIO_PORTB_AHB_IM_R (*((volatile unsigned long *)0x40059410)) +#define GPIO_PORTB_AHB_RIS_R (*((volatile unsigned long *)0x40059414)) +#define GPIO_PORTB_AHB_MIS_R (*((volatile unsigned long *)0x40059418)) +#define GPIO_PORTB_AHB_ICR_R (*((volatile unsigned long *)0x4005941C)) +#define GPIO_PORTB_AHB_AFSEL_R (*((volatile unsigned long *)0x40059420)) +#define GPIO_PORTB_AHB_DR2R_R (*((volatile unsigned long *)0x40059500)) +#define GPIO_PORTB_AHB_DR4R_R (*((volatile unsigned long *)0x40059504)) +#define GPIO_PORTB_AHB_DR8R_R (*((volatile unsigned long *)0x40059508)) +#define GPIO_PORTB_AHB_ODR_R (*((volatile unsigned long *)0x4005950C)) +#define GPIO_PORTB_AHB_PUR_R (*((volatile unsigned long *)0x40059510)) +#define GPIO_PORTB_AHB_PDR_R (*((volatile unsigned long *)0x40059514)) +#define GPIO_PORTB_AHB_SLR_R (*((volatile unsigned long *)0x40059518)) +#define GPIO_PORTB_AHB_DEN_R (*((volatile unsigned long *)0x4005951C)) +#define GPIO_PORTB_AHB_LOCK_R (*((volatile unsigned long *)0x40059520)) +#define GPIO_PORTB_AHB_CR_R (*((volatile unsigned long *)0x40059524)) +#define GPIO_PORTB_AHB_AMSEL_R (*((volatile unsigned long *)0x40059528)) +#define GPIO_PORTB_AHB_PCTL_R (*((volatile unsigned long *)0x4005952C)) +#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile unsigned long *)0x40059530)) +#define GPIO_PORTB_AHB_DMACTL_R (*((volatile unsigned long *)0x40059534)) +#define GPIO_PORTB_AHB_SI_R (*((volatile unsigned long *)0x40059538)) + +//***************************************************************************** +// +// GPIO registers (PORTC AHB) +// +//***************************************************************************** +#define GPIO_PORTC_AHB_DATA_BITS_R \ + ((volatile unsigned long *)0x4005A000) +#define GPIO_PORTC_AHB_DATA_R (*((volatile unsigned long *)0x4005A3FC)) +#define GPIO_PORTC_AHB_DIR_R (*((volatile unsigned long *)0x4005A400)) +#define GPIO_PORTC_AHB_IS_R (*((volatile unsigned long *)0x4005A404)) +#define GPIO_PORTC_AHB_IBE_R (*((volatile unsigned long *)0x4005A408)) +#define GPIO_PORTC_AHB_IEV_R (*((volatile unsigned long *)0x4005A40C)) +#define GPIO_PORTC_AHB_IM_R (*((volatile unsigned long *)0x4005A410)) +#define GPIO_PORTC_AHB_RIS_R (*((volatile unsigned long *)0x4005A414)) +#define GPIO_PORTC_AHB_MIS_R (*((volatile unsigned long *)0x4005A418)) +#define GPIO_PORTC_AHB_ICR_R (*((volatile unsigned long *)0x4005A41C)) +#define GPIO_PORTC_AHB_AFSEL_R (*((volatile unsigned long *)0x4005A420)) +#define GPIO_PORTC_AHB_DR2R_R (*((volatile unsigned long *)0x4005A500)) +#define GPIO_PORTC_AHB_DR4R_R (*((volatile unsigned long *)0x4005A504)) +#define GPIO_PORTC_AHB_DR8R_R (*((volatile unsigned long *)0x4005A508)) +#define GPIO_PORTC_AHB_ODR_R (*((volatile unsigned long *)0x4005A50C)) +#define GPIO_PORTC_AHB_PUR_R (*((volatile unsigned long *)0x4005A510)) +#define GPIO_PORTC_AHB_PDR_R (*((volatile unsigned long *)0x4005A514)) +#define GPIO_PORTC_AHB_SLR_R (*((volatile unsigned long *)0x4005A518)) +#define GPIO_PORTC_AHB_DEN_R (*((volatile unsigned long *)0x4005A51C)) +#define GPIO_PORTC_AHB_LOCK_R (*((volatile unsigned long *)0x4005A520)) +#define GPIO_PORTC_AHB_CR_R (*((volatile unsigned long *)0x4005A524)) +#define GPIO_PORTC_AHB_AMSEL_R (*((volatile unsigned long *)0x4005A528)) +#define GPIO_PORTC_AHB_PCTL_R (*((volatile unsigned long *)0x4005A52C)) +#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005A530)) +#define GPIO_PORTC_AHB_DMACTL_R (*((volatile unsigned long *)0x4005A534)) +#define GPIO_PORTC_AHB_SI_R (*((volatile unsigned long *)0x4005A538)) + +//***************************************************************************** +// +// GPIO registers (PORTD AHB) +// +//***************************************************************************** +#define GPIO_PORTD_AHB_DATA_BITS_R \ + ((volatile unsigned long *)0x4005B000) +#define GPIO_PORTD_AHB_DATA_R (*((volatile unsigned long *)0x4005B3FC)) +#define GPIO_PORTD_AHB_DIR_R (*((volatile unsigned long *)0x4005B400)) +#define GPIO_PORTD_AHB_IS_R (*((volatile unsigned long *)0x4005B404)) +#define GPIO_PORTD_AHB_IBE_R (*((volatile unsigned long *)0x4005B408)) +#define GPIO_PORTD_AHB_IEV_R (*((volatile unsigned long *)0x4005B40C)) +#define GPIO_PORTD_AHB_IM_R (*((volatile unsigned long *)0x4005B410)) +#define GPIO_PORTD_AHB_RIS_R (*((volatile unsigned long *)0x4005B414)) +#define GPIO_PORTD_AHB_MIS_R (*((volatile unsigned long *)0x4005B418)) +#define GPIO_PORTD_AHB_ICR_R (*((volatile unsigned long *)0x4005B41C)) +#define GPIO_PORTD_AHB_AFSEL_R (*((volatile unsigned long *)0x4005B420)) +#define GPIO_PORTD_AHB_DR2R_R (*((volatile unsigned long *)0x4005B500)) +#define GPIO_PORTD_AHB_DR4R_R (*((volatile unsigned long *)0x4005B504)) +#define GPIO_PORTD_AHB_DR8R_R (*((volatile unsigned long *)0x4005B508)) +#define GPIO_PORTD_AHB_ODR_R (*((volatile unsigned long *)0x4005B50C)) +#define GPIO_PORTD_AHB_PUR_R (*((volatile unsigned long *)0x4005B510)) +#define GPIO_PORTD_AHB_PDR_R (*((volatile unsigned long *)0x4005B514)) +#define GPIO_PORTD_AHB_SLR_R (*((volatile unsigned long *)0x4005B518)) +#define GPIO_PORTD_AHB_DEN_R (*((volatile unsigned long *)0x4005B51C)) +#define GPIO_PORTD_AHB_LOCK_R (*((volatile unsigned long *)0x4005B520)) +#define GPIO_PORTD_AHB_CR_R (*((volatile unsigned long *)0x4005B524)) +#define GPIO_PORTD_AHB_AMSEL_R (*((volatile unsigned long *)0x4005B528)) +#define GPIO_PORTD_AHB_PCTL_R (*((volatile unsigned long *)0x4005B52C)) +#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005B530)) +#define GPIO_PORTD_AHB_DMACTL_R (*((volatile unsigned long *)0x4005B534)) +#define GPIO_PORTD_AHB_SI_R (*((volatile unsigned long *)0x4005B538)) + +//***************************************************************************** +// +// GPIO registers (PORTE AHB) +// +//***************************************************************************** +#define GPIO_PORTE_AHB_DATA_BITS_R \ + ((volatile unsigned long *)0x4005C000) +#define GPIO_PORTE_AHB_DATA_R (*((volatile unsigned long *)0x4005C3FC)) +#define GPIO_PORTE_AHB_DIR_R (*((volatile unsigned long *)0x4005C400)) +#define GPIO_PORTE_AHB_IS_R (*((volatile unsigned long *)0x4005C404)) +#define GPIO_PORTE_AHB_IBE_R (*((volatile unsigned long *)0x4005C408)) +#define GPIO_PORTE_AHB_IEV_R (*((volatile unsigned long *)0x4005C40C)) +#define GPIO_PORTE_AHB_IM_R (*((volatile unsigned long *)0x4005C410)) +#define GPIO_PORTE_AHB_RIS_R (*((volatile unsigned long *)0x4005C414)) +#define GPIO_PORTE_AHB_MIS_R (*((volatile unsigned long *)0x4005C418)) +#define GPIO_PORTE_AHB_ICR_R (*((volatile unsigned long *)0x4005C41C)) +#define GPIO_PORTE_AHB_AFSEL_R (*((volatile unsigned long *)0x4005C420)) +#define GPIO_PORTE_AHB_DR2R_R (*((volatile unsigned long *)0x4005C500)) +#define GPIO_PORTE_AHB_DR4R_R (*((volatile unsigned long *)0x4005C504)) +#define GPIO_PORTE_AHB_DR8R_R (*((volatile unsigned long *)0x4005C508)) +#define GPIO_PORTE_AHB_ODR_R (*((volatile unsigned long *)0x4005C50C)) +#define GPIO_PORTE_AHB_PUR_R (*((volatile unsigned long *)0x4005C510)) +#define GPIO_PORTE_AHB_PDR_R (*((volatile unsigned long *)0x4005C514)) +#define GPIO_PORTE_AHB_SLR_R (*((volatile unsigned long *)0x4005C518)) +#define GPIO_PORTE_AHB_DEN_R (*((volatile unsigned long *)0x4005C51C)) +#define GPIO_PORTE_AHB_LOCK_R (*((volatile unsigned long *)0x4005C520)) +#define GPIO_PORTE_AHB_CR_R (*((volatile unsigned long *)0x4005C524)) +#define GPIO_PORTE_AHB_AMSEL_R (*((volatile unsigned long *)0x4005C528)) +#define GPIO_PORTE_AHB_PCTL_R (*((volatile unsigned long *)0x4005C52C)) +#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005C530)) +#define GPIO_PORTE_AHB_DMACTL_R (*((volatile unsigned long *)0x4005C534)) +#define GPIO_PORTE_AHB_SI_R (*((volatile unsigned long *)0x4005C538)) + +//***************************************************************************** +// +// GPIO registers (PORTF AHB) +// +//***************************************************************************** +#define GPIO_PORTF_AHB_DATA_BITS_R \ + ((volatile unsigned long *)0x4005D000) +#define GPIO_PORTF_AHB_DATA_R (*((volatile unsigned long *)0x4005D3FC)) +#define GPIO_PORTF_AHB_DIR_R (*((volatile unsigned long *)0x4005D400)) +#define GPIO_PORTF_AHB_IS_R (*((volatile unsigned long *)0x4005D404)) +#define GPIO_PORTF_AHB_IBE_R (*((volatile unsigned long *)0x4005D408)) +#define GPIO_PORTF_AHB_IEV_R (*((volatile unsigned long *)0x4005D40C)) +#define GPIO_PORTF_AHB_IM_R (*((volatile unsigned long *)0x4005D410)) +#define GPIO_PORTF_AHB_RIS_R (*((volatile unsigned long *)0x4005D414)) +#define GPIO_PORTF_AHB_MIS_R (*((volatile unsigned long *)0x4005D418)) +#define GPIO_PORTF_AHB_ICR_R (*((volatile unsigned long *)0x4005D41C)) +#define GPIO_PORTF_AHB_AFSEL_R (*((volatile unsigned long *)0x4005D420)) +#define GPIO_PORTF_AHB_DR2R_R (*((volatile unsigned long *)0x4005D500)) +#define GPIO_PORTF_AHB_DR4R_R (*((volatile unsigned long *)0x4005D504)) +#define GPIO_PORTF_AHB_DR8R_R (*((volatile unsigned long *)0x4005D508)) +#define GPIO_PORTF_AHB_ODR_R (*((volatile unsigned long *)0x4005D50C)) +#define GPIO_PORTF_AHB_PUR_R (*((volatile unsigned long *)0x4005D510)) +#define GPIO_PORTF_AHB_PDR_R (*((volatile unsigned long *)0x4005D514)) +#define GPIO_PORTF_AHB_SLR_R (*((volatile unsigned long *)0x4005D518)) +#define GPIO_PORTF_AHB_DEN_R (*((volatile unsigned long *)0x4005D51C)) +#define GPIO_PORTF_AHB_LOCK_R (*((volatile unsigned long *)0x4005D520)) +#define GPIO_PORTF_AHB_CR_R (*((volatile unsigned long *)0x4005D524)) +#define GPIO_PORTF_AHB_AMSEL_R (*((volatile unsigned long *)0x4005D528)) +#define GPIO_PORTF_AHB_PCTL_R (*((volatile unsigned long *)0x4005D52C)) +#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005D530)) +#define GPIO_PORTF_AHB_DMACTL_R (*((volatile unsigned long *)0x4005D534)) +#define GPIO_PORTF_AHB_SI_R (*((volatile unsigned long *)0x4005D538)) + +//***************************************************************************** +// +// EEPROM registers (EEPROM) +// +//***************************************************************************** +#define EEPROM_EESIZE_R (*((volatile unsigned long *)0x400AF000)) +#define EEPROM_EEBLOCK_R (*((volatile unsigned long *)0x400AF004)) +#define EEPROM_EEOFFSET_R (*((volatile unsigned long *)0x400AF008)) +#define EEPROM_EERDWR_R (*((volatile unsigned long *)0x400AF010)) +#define EEPROM_EERDWRINC_R (*((volatile unsigned long *)0x400AF014)) +#define EEPROM_EEDONE_R (*((volatile unsigned long *)0x400AF018)) +#define EEPROM_EESUPP_R (*((volatile unsigned long *)0x400AF01C)) +#define EEPROM_EEUNLOCK_R (*((volatile unsigned long *)0x400AF020)) +#define EEPROM_EEPROT_R (*((volatile unsigned long *)0x400AF030)) +#define EEPROM_EEPASS0_R (*((volatile unsigned long *)0x400AF034)) +#define EEPROM_EEPASS1_R (*((volatile unsigned long *)0x400AF038)) +#define EEPROM_EEPASS2_R (*((volatile unsigned long *)0x400AF03C)) +#define EEPROM_EEINT_R (*((volatile unsigned long *)0x400AF040)) +#define EEPROM_EEHIDE_R (*((volatile unsigned long *)0x400AF050)) +#define EEPROM_EEDBGME_R (*((volatile unsigned long *)0x400AF080)) +#define EEPROM_PP_R (*((volatile unsigned long *)0x400AFFC0)) + +//***************************************************************************** +// +// System Exception Module registers (SYSEXC) +// +//***************************************************************************** +#define SYSEXC_RIS_R (*((volatile unsigned long *)0x400F9000)) +#define SYSEXC_IM_R (*((volatile unsigned long *)0x400F9004)) +#define SYSEXC_MIS_R (*((volatile unsigned long *)0x400F9008)) +#define SYSEXC_IC_R (*((volatile unsigned long *)0x400F900C)) + +//***************************************************************************** +// +// Hibernation module registers (HIB) +// +//***************************************************************************** +#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000)) +#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004)) +#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C)) +#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010)) +#define HIB_IM_R (*((volatile unsigned long *)0x400FC014)) +#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018)) +#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C)) +#define HIB_IC_R (*((volatile unsigned long *)0x400FC020)) +#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024)) +#define HIB_RTCSS_R (*((volatile unsigned long *)0x400FC028)) +#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030)) + +//***************************************************************************** +// +// FLASH registers (FLASH CTRL) +// +//***************************************************************************** +#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000)) +#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004)) +#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008)) +#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C)) +#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010)) +#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014)) +#define FLASH_FMC2_R (*((volatile unsigned long *)0x400FD020)) +#define FLASH_FWBVAL_R (*((volatile unsigned long *)0x400FD030)) +#define FLASH_FWBN_R (*((volatile unsigned long *)0x400FD100)) +#define FLASH_FSIZE_R (*((volatile unsigned long *)0x400FDFC0)) +#define FLASH_SSIZE_R (*((volatile unsigned long *)0x400FDFC4)) +#define FLASH_ROMSWMAP_R (*((volatile unsigned long *)0x400FDFCC)) +#define FLASH_RMCTL_R (*((volatile unsigned long *)0x400FE0F0)) +#define FLASH_BOOTCFG_R (*((volatile unsigned long *)0x400FE1D0)) +#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0)) +#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4)) +#define FLASH_USERREG2_R (*((volatile unsigned long *)0x400FE1E8)) +#define FLASH_USERREG3_R (*((volatile unsigned long *)0x400FE1EC)) +#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200)) +#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204)) +#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208)) +#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C)) +#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400)) +#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404)) +#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408)) +#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C)) + +//***************************************************************************** +// +// System Control registers (SYSCTL) +// +//***************************************************************************** +#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000)) +#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004)) +#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008)) +#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010)) +#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014)) +#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018)) +#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C)) +#define SYSCTL_DC5_R (*((volatile unsigned long *)0x400FE020)) +#define SYSCTL_DC6_R (*((volatile unsigned long *)0x400FE024)) +#define SYSCTL_DC7_R (*((volatile unsigned long *)0x400FE028)) +#define SYSCTL_DC8_R (*((volatile unsigned long *)0x400FE02C)) +#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030)) +#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040)) +#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044)) +#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048)) +#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050)) +#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054)) +#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058)) +#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C)) +#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060)) +#define SYSCTL_GPIOHBCTL_R (*((volatile unsigned long *)0x400FE06C)) +#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070)) +#define SYSCTL_MOSCCTL_R (*((volatile unsigned long *)0x400FE07C)) +#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100)) +#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104)) +#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108)) +#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110)) +#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114)) +#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118)) +#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120)) +#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124)) +#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128)) +#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144)) +#define SYSCTL_SYSPROP_R (*((volatile unsigned long *)0x400FE14C)) +#define SYSCTL_PIOSCCAL_R (*((volatile unsigned long *)0x400FE150)) +#define SYSCTL_PIOSCSTAT_R (*((volatile unsigned long *)0x400FE154)) +#define SYSCTL_PLLFREQ0_R (*((volatile unsigned long *)0x400FE160)) +#define SYSCTL_PLLFREQ1_R (*((volatile unsigned long *)0x400FE164)) +#define SYSCTL_PLLSTAT_R (*((volatile unsigned long *)0x400FE168)) +#define SYSCTL_DC9_R (*((volatile unsigned long *)0x400FE190)) +#define SYSCTL_NVMSTAT_R (*((volatile unsigned long *)0x400FE1A0)) +#define SYSCTL_PPWD_R (*((volatile unsigned long *)0x400FE300)) +#define SYSCTL_PPTIMER_R (*((volatile unsigned long *)0x400FE304)) +#define SYSCTL_PPGPIO_R (*((volatile unsigned long *)0x400FE308)) +#define SYSCTL_PPDMA_R (*((volatile unsigned long *)0x400FE30C)) +#define SYSCTL_PPHIB_R (*((volatile unsigned long *)0x400FE314)) +#define SYSCTL_PPUART_R (*((volatile unsigned long *)0x400FE318)) +#define SYSCTL_PPSSI_R (*((volatile unsigned long *)0x400FE31C)) +#define SYSCTL_PPI2C_R (*((volatile unsigned long *)0x400FE320)) +#define SYSCTL_PPUSB_R (*((volatile unsigned long *)0x400FE328)) +#define SYSCTL_PPCAN_R (*((volatile unsigned long *)0x400FE334)) +#define SYSCTL_PPADC_R (*((volatile unsigned long *)0x400FE338)) +#define SYSCTL_PPACMP_R (*((volatile unsigned long *)0x400FE33C)) +#define SYSCTL_PPPWM_R (*((volatile unsigned long *)0x400FE340)) +#define SYSCTL_PPQEI_R (*((volatile unsigned long *)0x400FE344)) +#define SYSCTL_PPEEPROM_R (*((volatile unsigned long *)0x400FE358)) +#define SYSCTL_PPWTIMER_R (*((volatile unsigned long *)0x400FE35C)) +#define SYSCTL_SRWD_R (*((volatile unsigned long *)0x400FE500)) +#define SYSCTL_SRTIMER_R (*((volatile unsigned long *)0x400FE504)) +#define SYSCTL_SRGPIO_R (*((volatile unsigned long *)0x400FE508)) +#define SYSCTL_SRDMA_R (*((volatile unsigned long *)0x400FE50C)) +#define SYSCTL_SRHIB_R (*((volatile unsigned long *)0x400FE514)) +#define SYSCTL_SRUART_R (*((volatile unsigned long *)0x400FE518)) +#define SYSCTL_SRSSI_R (*((volatile unsigned long *)0x400FE51C)) +#define SYSCTL_SRI2C_R (*((volatile unsigned long *)0x400FE520)) +#define SYSCTL_SRUSB_R (*((volatile unsigned long *)0x400FE528)) +#define SYSCTL_SRCAN_R (*((volatile unsigned long *)0x400FE534)) +#define SYSCTL_SRADC_R (*((volatile unsigned long *)0x400FE538)) +#define SYSCTL_SRACMP_R (*((volatile unsigned long *)0x400FE53C)) +#define SYSCTL_SREEPROM_R (*((volatile unsigned long *)0x400FE558)) +#define SYSCTL_SRWTIMER_R (*((volatile unsigned long *)0x400FE55C)) +#define SYSCTL_RCGCWD_R (*((volatile unsigned long *)0x400FE600)) +#define SYSCTL_RCGCTIMER_R (*((volatile unsigned long *)0x400FE604)) +#define SYSCTL_RCGCGPIO_R (*((volatile unsigned long *)0x400FE608)) +#define SYSCTL_RCGCDMA_R (*((volatile unsigned long *)0x400FE60C)) +#define SYSCTL_RCGCHIB_R (*((volatile unsigned long *)0x400FE614)) +#define SYSCTL_RCGCUART_R (*((volatile unsigned long *)0x400FE618)) +#define SYSCTL_RCGCSSI_R (*((volatile unsigned long *)0x400FE61C)) +#define SYSCTL_RCGCI2C_R (*((volatile unsigned long *)0x400FE620)) +#define SYSCTL_RCGCUSB_R (*((volatile unsigned long *)0x400FE628)) +#define SYSCTL_RCGCCAN_R (*((volatile unsigned long *)0x400FE634)) +#define SYSCTL_RCGCADC_R (*((volatile unsigned long *)0x400FE638)) +#define SYSCTL_RCGCACMP_R (*((volatile unsigned long *)0x400FE63C)) +#define SYSCTL_RCGCEEPROM_R (*((volatile unsigned long *)0x400FE658)) +#define SYSCTL_RCGCWTIMER_R (*((volatile unsigned long *)0x400FE65C)) +#define SYSCTL_SCGCWD_R (*((volatile unsigned long *)0x400FE700)) +#define SYSCTL_SCGCTIMER_R (*((volatile unsigned long *)0x400FE704)) +#define SYSCTL_SCGCGPIO_R (*((volatile unsigned long *)0x400FE708)) +#define SYSCTL_SCGCDMA_R (*((volatile unsigned long *)0x400FE70C)) +#define SYSCTL_SCGCHIB_R (*((volatile unsigned long *)0x400FE714)) +#define SYSCTL_SCGCUART_R (*((volatile unsigned long *)0x400FE718)) +#define SYSCTL_SCGCSSI_R (*((volatile unsigned long *)0x400FE71C)) +#define SYSCTL_SCGCI2C_R (*((volatile unsigned long *)0x400FE720)) +#define SYSCTL_SCGCUSB_R (*((volatile unsigned long *)0x400FE728)) +#define SYSCTL_SCGCCAN_R (*((volatile unsigned long *)0x400FE734)) +#define SYSCTL_SCGCADC_R (*((volatile unsigned long *)0x400FE738)) +#define SYSCTL_SCGCACMP_R (*((volatile unsigned long *)0x400FE73C)) +#define SYSCTL_SCGCEEPROM_R (*((volatile unsigned long *)0x400FE758)) +#define SYSCTL_SCGCWTIMER_R (*((volatile unsigned long *)0x400FE75C)) +#define SYSCTL_DCGCWD_R (*((volatile unsigned long *)0x400FE800)) +#define SYSCTL_DCGCTIMER_R (*((volatile unsigned long *)0x400FE804)) +#define SYSCTL_DCGCGPIO_R (*((volatile unsigned long *)0x400FE808)) +#define SYSCTL_DCGCDMA_R (*((volatile unsigned long *)0x400FE80C)) +#define SYSCTL_DCGCHIB_R (*((volatile unsigned long *)0x400FE814)) +#define SYSCTL_DCGCUART_R (*((volatile unsigned long *)0x400FE818)) +#define SYSCTL_DCGCSSI_R (*((volatile unsigned long *)0x400FE81C)) +#define SYSCTL_DCGCI2C_R (*((volatile unsigned long *)0x400FE820)) +#define SYSCTL_DCGCUSB_R (*((volatile unsigned long *)0x400FE828)) +#define SYSCTL_DCGCCAN_R (*((volatile unsigned long *)0x400FE834)) +#define SYSCTL_DCGCADC_R (*((volatile unsigned long *)0x400FE838)) +#define SYSCTL_DCGCACMP_R (*((volatile unsigned long *)0x400FE83C)) +#define SYSCTL_DCGCEEPROM_R (*((volatile unsigned long *)0x400FE858)) +#define SYSCTL_DCGCWTIMER_R (*((volatile unsigned long *)0x400FE85C)) +#define SYSCTL_PCWD_R (*((volatile unsigned long *)0x400FE900)) +#define SYSCTL_PCTIMER_R (*((volatile unsigned long *)0x400FE904)) +#define SYSCTL_PCGPIO_R (*((volatile unsigned long *)0x400FE908)) +#define SYSCTL_PCDMA_R (*((volatile unsigned long *)0x400FE90C)) +#define SYSCTL_PCHIB_R (*((volatile unsigned long *)0x400FE914)) +#define SYSCTL_PCUART_R (*((volatile unsigned long *)0x400FE918)) +#define SYSCTL_PCSSI_R (*((volatile unsigned long *)0x400FE91C)) +#define SYSCTL_PCI2C_R (*((volatile unsigned long *)0x400FE920)) +#define SYSCTL_PCUSB_R (*((volatile unsigned long *)0x400FE928)) +#define SYSCTL_PCCAN_R (*((volatile unsigned long *)0x400FE934)) +#define SYSCTL_PCADC_R (*((volatile unsigned long *)0x400FE938)) +#define SYSCTL_PCACMP_R (*((volatile unsigned long *)0x400FE93C)) +#define SYSCTL_PCEEPROM_R (*((volatile unsigned long *)0x400FE958)) +#define SYSCTL_PCWTIMER_R (*((volatile unsigned long *)0x400FE95C)) +#define SYSCTL_PRWD_R (*((volatile unsigned long *)0x400FEA00)) +#define SYSCTL_PRTIMER_R (*((volatile unsigned long *)0x400FEA04)) +#define SYSCTL_PRGPIO_R (*((volatile unsigned long *)0x400FEA08)) +#define SYSCTL_PRDMA_R (*((volatile unsigned long *)0x400FEA0C)) +#define SYSCTL_PRHIB_R (*((volatile unsigned long *)0x400FEA14)) +#define SYSCTL_PRUART_R (*((volatile unsigned long *)0x400FEA18)) +#define SYSCTL_PRSSI_R (*((volatile unsigned long *)0x400FEA1C)) +#define SYSCTL_PRI2C_R (*((volatile unsigned long *)0x400FEA20)) +#define SYSCTL_PRUSB_R (*((volatile unsigned long *)0x400FEA28)) +#define SYSCTL_PRCAN_R (*((volatile unsigned long *)0x400FEA34)) +#define SYSCTL_PRADC_R (*((volatile unsigned long *)0x400FEA38)) +#define SYSCTL_PRACMP_R (*((volatile unsigned long *)0x400FEA3C)) +#define SYSCTL_PREEPROM_R (*((volatile unsigned long *)0x400FEA58)) +#define SYSCTL_PRWTIMER_R (*((volatile unsigned long *)0x400FEA5C)) + +//***************************************************************************** +// +// Micro Direct Memory Access registers (UDMA) +// +//***************************************************************************** +#define UDMA_STAT_R (*((volatile unsigned long *)0x400FF000)) +#define UDMA_CFG_R (*((volatile unsigned long *)0x400FF004)) +#define UDMA_CTLBASE_R (*((volatile unsigned long *)0x400FF008)) +#define UDMA_ALTBASE_R (*((volatile unsigned long *)0x400FF00C)) +#define UDMA_WAITSTAT_R (*((volatile unsigned long *)0x400FF010)) +#define UDMA_SWREQ_R (*((volatile unsigned long *)0x400FF014)) +#define UDMA_USEBURSTSET_R (*((volatile unsigned long *)0x400FF018)) +#define UDMA_USEBURSTCLR_R (*((volatile unsigned long *)0x400FF01C)) +#define UDMA_REQMASKSET_R (*((volatile unsigned long *)0x400FF020)) +#define UDMA_REQMASKCLR_R (*((volatile unsigned long *)0x400FF024)) +#define UDMA_ENASET_R (*((volatile unsigned long *)0x400FF028)) +#define UDMA_ENACLR_R (*((volatile unsigned long *)0x400FF02C)) +#define UDMA_ALTSET_R (*((volatile unsigned long *)0x400FF030)) +#define UDMA_ALTCLR_R (*((volatile unsigned long *)0x400FF034)) +#define UDMA_PRIOSET_R (*((volatile unsigned long *)0x400FF038)) +#define UDMA_PRIOCLR_R (*((volatile unsigned long *)0x400FF03C)) +#define UDMA_ERRCLR_R (*((volatile unsigned long *)0x400FF04C)) +#define UDMA_CHASGN_R (*((volatile unsigned long *)0x400FF500)) +#define UDMA_CHIS_R (*((volatile unsigned long *)0x400FF504)) +#define UDMA_CHMAP0_R (*((volatile unsigned long *)0x400FF510)) +#define UDMA_CHMAP1_R (*((volatile unsigned long *)0x400FF514)) +#define UDMA_CHMAP2_R (*((volatile unsigned long *)0x400FF518)) +#define UDMA_CHMAP3_R (*((volatile unsigned long *)0x400FF51C)) + +//***************************************************************************** +// +// Micro Direct Memory Access (uDMA) offsets (UDMA) +// +//***************************************************************************** +#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// NVIC registers (NVIC) +// +//***************************************************************************** +#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004)) +#define NVIC_ACTLR_R (*((volatile unsigned long *)0xE000E008)) +#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010)) +#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014)) +#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018)) +#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C)) +#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) +#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104)) +#define NVIC_EN2_R (*((volatile unsigned long *)0xE000E108)) +#define NVIC_EN3_R (*((volatile unsigned long *)0xE000E10C)) +#define NVIC_EN4_R (*((volatile unsigned long *)0xE000E110)) +#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180)) +#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184)) +#define NVIC_DIS2_R (*((volatile unsigned long *)0xE000E188)) +#define NVIC_DIS3_R (*((volatile unsigned long *)0xE000E18C)) +#define NVIC_DIS4_R (*((volatile unsigned long *)0xE000E190)) +#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200)) +#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204)) +#define NVIC_PEND2_R (*((volatile unsigned long *)0xE000E208)) +#define NVIC_PEND3_R (*((volatile unsigned long *)0xE000E20C)) +#define NVIC_PEND4_R (*((volatile unsigned long *)0xE000E210)) +#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280)) +#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284)) +#define NVIC_UNPEND2_R (*((volatile unsigned long *)0xE000E288)) +#define NVIC_UNPEND3_R (*((volatile unsigned long *)0xE000E28C)) +#define NVIC_UNPEND4_R (*((volatile unsigned long *)0xE000E290)) +#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300)) +#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304)) +#define NVIC_ACTIVE2_R (*((volatile unsigned long *)0xE000E308)) +#define NVIC_ACTIVE3_R (*((volatile unsigned long *)0xE000E30C)) +#define NVIC_ACTIVE4_R (*((volatile unsigned long *)0xE000E310)) +#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400)) +#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404)) +#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408)) +#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C)) +#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410)) +#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414)) +#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418)) +#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C)) +#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420)) +#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424)) +#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428)) +#define NVIC_PRI11_R (*((volatile unsigned long *)0xE000E42C)) +#define NVIC_PRI12_R (*((volatile unsigned long *)0xE000E430)) +#define NVIC_PRI13_R (*((volatile unsigned long *)0xE000E434)) +#define NVIC_PRI14_R (*((volatile unsigned long *)0xE000E438)) +#define NVIC_PRI15_R (*((volatile unsigned long *)0xE000E43C)) +#define NVIC_PRI16_R (*((volatile unsigned long *)0xE000E440)) +#define NVIC_PRI17_R (*((volatile unsigned long *)0xE000E444)) +#define NVIC_PRI18_R (*((volatile unsigned long *)0xE000E448)) +#define NVIC_PRI19_R (*((volatile unsigned long *)0xE000E44C)) +#define NVIC_PRI20_R (*((volatile unsigned long *)0xE000E450)) +#define NVIC_PRI21_R (*((volatile unsigned long *)0xE000E454)) +#define NVIC_PRI22_R (*((volatile unsigned long *)0xE000E458)) +#define NVIC_PRI23_R (*((volatile unsigned long *)0xE000E45C)) +#define NVIC_PRI24_R (*((volatile unsigned long *)0xE000E460)) +#define NVIC_PRI25_R (*((volatile unsigned long *)0xE000E464)) +#define NVIC_PRI26_R (*((volatile unsigned long *)0xE000E468)) +#define NVIC_PRI27_R (*((volatile unsigned long *)0xE000E46C)) +#define NVIC_PRI28_R (*((volatile unsigned long *)0xE000E470)) +#define NVIC_PRI29_R (*((volatile unsigned long *)0xE000E474)) +#define NVIC_PRI30_R (*((volatile unsigned long *)0xE000E478)) +#define NVIC_PRI31_R (*((volatile unsigned long *)0xE000E47C)) +#define NVIC_PRI32_R (*((volatile unsigned long *)0xE000E480)) +#define NVIC_PRI33_R (*((volatile unsigned long *)0xE000E484)) +#define NVIC_PRI34_R (*((volatile unsigned long *)0xE000E488)) +#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00)) +#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04)) +#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08)) +#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C)) +#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10)) +#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14)) +#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18)) +#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C)) +#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20)) +#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24)) +#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28)) +#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C)) +#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30)) +#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34)) +#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38)) +#define NVIC_CPAC_R (*((volatile unsigned long *)0xE000ED88)) +#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90)) +#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94)) +#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98)) +#define NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C)) +#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0)) +#define NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4)) +#define NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8)) +#define NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC)) +#define NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0)) +#define NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4)) +#define NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8)) +#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0)) +#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4)) +#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8)) +#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC)) +#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00)) +#define NVIC_FPCC_R (*((volatile unsigned long *)0xE000EF34)) +#define NVIC_FPCA_R (*((volatile unsigned long *)0xE000EF38)) +#define NVIC_FPDSC_R (*((volatile unsigned long *)0xE000EF3C)) + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable +#define GPIO_IM_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status +#define GPIO_RIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status +#define GPIO_MIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear +#define GPIO_ICR_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock +#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked + // and may be modified +#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked + // and may not be modified +#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_SI register. +// +//***************************************************************************** +#define GPIO_SI_SUM 0x00000001 // Summary Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port A. +// +//***************************************************************************** +#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask +#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7 +#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask +#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6 +#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask +#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5 +#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask +#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4 +#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask +#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3 +#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask +#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2 +#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask +#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1 +#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask +#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port B. +// +//***************************************************************************** +#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask +#define GPIO_PCTL_PB7_SSI2TX 0x20000000 // SSI2TX on PB7 +#define GPIO_PCTL_PB7_T0CCP1 0x70000000 // T0CCP1 on PB7 +#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask +#define GPIO_PCTL_PB6_SSI2RX 0x02000000 // SSI2RX on PB6 +#define GPIO_PCTL_PB6_T0CCP0 0x07000000 // T0CCP0 on PB6 +#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask +#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5 +#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5 +#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5 +#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask +#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4 +#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4 +#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4 +#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask +#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3 +#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3 +#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask +#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2 +#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2 +#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask +#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1 +#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1 +#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask +#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0 +#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port C. +// +//***************************************************************************** +#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask +#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7 +#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7 +#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask +#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6 +#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6 +#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask +#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5 +#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5 +#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5 +#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5 +#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask +#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4 +#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4 +#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4 +#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4 +#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask +#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3 +#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3 +#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask +#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2 +#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2 +#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask +#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1 +#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1 +#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask +#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0 +#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port D. +// +//***************************************************************************** +#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask +#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7 +#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7 +#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7 +#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask +#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6 +#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6 +#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask +#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5 +#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5 +#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask +#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4 +#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4 +#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask +#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3 +#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3 +#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3 +#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask +#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2 +#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2 +#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2 +#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask +#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1 +#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1 +#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1 +#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1 +#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask +#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0 +#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0 +#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0 +#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port E. +// +//***************************************************************************** +#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask +#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5 +#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5 +#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5 +#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask +#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4 +#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4 +#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4 +#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask +#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask +#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask +#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1 +#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask +#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port F. +// +//***************************************************************************** +#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask +#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4 +#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask +#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3 +#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3 +#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3 +#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3 +#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask +#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2 +#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2 +#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2 +#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask +#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1 +#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1 +#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1 +#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1 +#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1 +#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask +#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0 +#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0 +#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0 +#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0 +#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0 +#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0 +#define GPIO_PCTL_PF0_TRD2 0x0000000E // TRD2 on PF0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate +#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase +#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity +#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select +#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format +#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous + // Serial Frame Format +#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select +#define SSI_CR0_DSS_4 0x00000003 // 4-bit data +#define SSI_CR0_DSS_5 0x00000004 // 5-bit data +#define SSI_CR0_DSS_6 0x00000005 // 6-bit data +#define SSI_CR0_DSS_7 0x00000006 // 7-bit data +#define SSI_CR0_DSS_8 0x00000007 // 8-bit data +#define SSI_CR0_DSS_9 0x00000008 // 9-bit data +#define SSI_CR0_DSS_10 0x00000009 // 10-bit data +#define SSI_CR0_DSS_11 0x0000000A // 11-bit data +#define SSI_CR0_DSS_12 0x0000000B // 12-bit data +#define SSI_CR0_DSS_13 0x0000000C // 13-bit data +#define SSI_CR0_DSS_14 0x0000000D // 14-bit data +#define SSI_CR0_DSS_15 0x0000000E // 15-bit data +#define SSI_CR0_DSS_16 0x0000000F // 16-bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +#define SSI_CR1_EOT 0x00000010 // End of Transmission +#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable +#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select +#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port + // Enable +#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI Busy Bit +#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full +#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty +#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full +#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the + // PLL bypass is in effect) or the + // PLL output (default) +#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_CTS 0x00000001 // Clear To Send + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_LIN 0x00000040 // LIN Mode Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full +#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full +#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) +#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full +#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full +#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full +#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) +#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full +#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask +#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask +#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt + // Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt + // Status +#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt + // Status +#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw + // Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt + // Status +#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt + // Status +#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked + // Interrupt Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCTL register. +// +//***************************************************************************** +#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length +#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits + // (default) +#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits +#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits +#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits +#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LSS register. +// +//***************************************************************************** +#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot +#define UART_LSS_TSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LTIM register. +// +//***************************************************************************** +#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value +#define UART_LTIM_TIMER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default) +#define UART_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_RS 0x00000001 // Receive not send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +#define I2C_SCSR_RREQ 0x00000001 // Receive Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_STOP 0x00000004 // Generate STOP +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_START 0x00000002 // Generate START +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable +#define I2C_MCS_BUSY 0x00000001 // I2C Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) + // counter configuration +#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The + // function is controlled by bits + // 1:0 of GPTMTAMR and GPTMTBMR + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer + // 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer + // 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer + // 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer + // 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer + // 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer + // 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 0 is triggered + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error + // Interrupt Mask +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt + // Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt + // Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw + // Interrupt +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked + // Interrupt +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Clear +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt + // Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt + // Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +#define TIMER_TAILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +#define TIMER_TAMATCHR_TAMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +#define TIMER_TBMATCHR_TBMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +#define TIMER_TAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +#define TIMER_TBR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +#define TIMER_TAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status +#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3 +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2 +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1 +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0 +#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0 +#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4) +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4) +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4) +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4) +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the + // PLL bypass is in effect) or the + // 16 MHz clock derived from PLL / + // 25 (default) +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference + // (VIREF) +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present +#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present +#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present +#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present +#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present +#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus-Off Status +#define CAN_STS_EWARN 0x00000040 // Warning Status +#define CAN_STS_EPASS 0x00000020 // Error Passive +#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully +#define CAN_STS_TXOK 0x00000008 // Transmitted a Message + // Successfully +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No Error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error +#define CAN_STS_LEC_FORM 0x00000002 // Format Error +#define CAN_STS_LEC_ACK 0x00000003 // ACK Error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error +#define CAN_STS_LEC_CRC 0x00000006 // CRC Error +#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Received Error Passive +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter +#define CAN_ERR_REC_S 8 +#define CAN_ERR_TEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier +#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // Receive Observation +#define CAN_TST_TX_M 0x00000060 // Transmit Control +#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point +#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low +#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High +#define CAN_TST_LBACK 0x00000010 // Loopback Mode +#define CAN_TST_SILENT 0x00000008 // Silent Mode +#define CAN_TST_BASIC 0x00000004 // Basic Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF1CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF2CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG2VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_DISCON 0x00000020 // Session Disconnect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks +#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words +#define EEPROM_EESIZE_BLKCNT_S 16 +#define EEPROM_EESIZE_WORDCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block +#define EEPROM_EEBLOCK_BLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +#define EEPROM_EEOFFSET_OFFSET_M \ + 0x0000000F // Current Address Offset +#define EEPROM_EEOFFSET_OFFSET_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data +#define EEPROM_EERDWR_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +#define EEPROM_EERDWRINC_VALUE_M \ + 0xFFFFFFFF // EEPROM Read or Write Data with + // Increment +#define EEPROM_EERDWRINC_VALUE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level +#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy +#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission +#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy +#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase +#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried +#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried +#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required +#define EEPROM_EESUPP_START 0x00000001 // Start Erase + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +#define EEPROM_EEUNLOCK_UNLOCK_M \ + 0xFFFFFFFF // EEPROM Unlock + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +#define EEPROM_EEPROT_ACC 0x00000008 // Access Control +#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control +#define EEPROM_EEPROT_PROT_RWNPW \ + 0x00000000 // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the + // block is readable or writable + // only when unlocked +#define EEPROM_EEPROT_PROT_RONPW \ + 0x00000002 // If there is no password, the + // block is readable, not writable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS0_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS1_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS2_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key +#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase +#define EEPROM_EEDBGME_KEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_PP register. +// +//***************************************************************************** +#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size +#define EEPROM_PP_SIZE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception + // Raw Interrupt Status +#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation + // Raw Interrupt Status +#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal + // Exception Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception + // Interrupt Mask +#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation + // Interrupt Mask +#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Mask +#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception + // Masked Interrupt Status +#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation + // Masked Interrupt Status +#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception + // Interrupt Clear +#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation + // Interrupt Clear +#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Clear +#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered +#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable +#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable +#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable +#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable +#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable +#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request +#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask +#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask +#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Mask +#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status +#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt + // Status +#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw + // Interrupt Status +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status +#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Status +#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Status +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Clear +#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Clear +#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Clear +#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit Register Value +#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory +#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory +#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status +#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status +#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt + // Status +#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status +#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask +#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask +#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask +#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCMISC register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and + // Clear +#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash +#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash +#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash +#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash +#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash +#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash +#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash +#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size +#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM +#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM +#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM +#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM +#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM +#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM +#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM +#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM +#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_BOOTCFG register. +// +//***************************************************************************** +#define FLASH_BOOTCFG_NW 0x80000000 // Not Written +#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port +#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A +#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B +#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C +#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D +#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E +#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F +#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G +#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H +#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin +#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 +#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 +#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 +#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 +#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 +#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 +#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 +#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 +#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity +#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable +#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 +#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version +#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 + // register format +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Stellaris(R) Blizzard-class + // microcontrollers +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision +#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major + // revision update +#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change +#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version +#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format + // definition, indicating a + // Stellaris LM3Snnn device +#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1 + // register format +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family +#define SYSCTL_DID1_FAM_STELLARIS \ + 0x00000000 // Stellaris family of + // microcontollers, that is, all + // devices with external part + // numbers starting with LM3S +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number +#define SYSCTL_DID1_PRTNO_LM4F120H5QR \ + 0x00040000 // LM4F120H5QR +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count +#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package +#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C + // to 70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range + // (-40C to 85C) +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C + // to 105C) +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type +#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package +#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash +#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift +#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider +#define SYSCTL_DC1_MINSYSDIV_100 \ + 0x00001000 // Divide VCO (400MHZ) by 5 minimum +#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 = + // 6 minimum +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8 +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10 +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // MPU Present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present +#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present +#define SYSCTL_DC1_PLL 0x00000010 // PLL Present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present +#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present +#define SYSCTL_DC1_SWD 0x00000002 // SWD Present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present +#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present +#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed +#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed +#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present +#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present +#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present +#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present +#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present +#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present +#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable +#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate +#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present +#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present +#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present +#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_DMACH30 0x40000000 // SW +#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX +#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX +#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3 +#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2 +#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1 +#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0 +#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX +#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX +#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO +#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO +#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B +#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A +#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3 +#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2 +#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B +#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A +#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX +#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX +#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX +#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX +#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX +#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX +#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B +#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A +#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B +#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A +#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B +#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A +#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX +#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control +#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control +#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control +#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control +#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw + // Interrupt Status +#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt + // Mask +#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked + // Interrupt Status +#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset +#define SYSCTL_RESC_SW 0x00000010 // Software Reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset +#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset +#define SYSCTL_RESC_EXT 0x00000001 // External Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable +#define SYSCTL_RCC_SYSDIV_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance + // Bus + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 + // MHz +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 +#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 +#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 +#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 +#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 +#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 +#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 +#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 +#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 +#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 +#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 +#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 +#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 +#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 +#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 +#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 +#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 +#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 +#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 +#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 +#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 +#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 +#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 +#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 +#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 +#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 +#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 +#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 +#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 +#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 +#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 +#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 +#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 +#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 +#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 +#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 +#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 +#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 +#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 +#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 +#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 +#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 +#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 +#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 +#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 +#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 +#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 +#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 +#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 +#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 +#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 +#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 +#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 +#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 +#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 +#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 +#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 +#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 +#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 +#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 +#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 +#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 +#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 +#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 +#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL +#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz +#define SYSCTL_RCC2_SYSDIV2_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_RCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_RCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_RCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override +#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1 +#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 +#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 +#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 +#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer + // Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset +#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset +#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset +#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset +#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset +#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset +#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset +#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset +#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset +#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWD register. +// +//***************************************************************************** +#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control +#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCTIMER register. +// +//***************************************************************************** +#define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control +#define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control +#define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control +#define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control +#define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control +#define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCGPIO register. +// +//***************************************************************************** +#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control +#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control +#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control +#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control +#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control +#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control +#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control +#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control +#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control +#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control +#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control +#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control +#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control +#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control +#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCDMA register. +// +//***************************************************************************** +#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCHIB register. +// +//***************************************************************************** +#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUART register. +// +//***************************************************************************** +#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control +#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control +#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control +#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control +#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control +#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control +#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control +#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCSSI register. +// +//***************************************************************************** +#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control +#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control +#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control +#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCI2C register. +// +//***************************************************************************** +#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control +#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control +#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control +#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control +#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control +#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUSB register. +// +//***************************************************************************** +#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCCAN register. +// +//***************************************************************************** +#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control +#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCADC register. +// +//***************************************************************************** +#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control +#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCACMP register. +// +//***************************************************************************** +#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control +#define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control +#define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control +#define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control +#define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control +#define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready +#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready +#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready +#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready +#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready +#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready +#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready +#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready +#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready +#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to + // clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHASGN register. +// +//***************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel + // assignment +#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel + // assignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// Deprecated defines for the EEPROM register offsets. +// +//***************************************************************************** +#define EEPROM_EEPROMPP_R (*((volatile unsigned long *)0x400AFFC0)) + +//***************************************************************************** +// +// Deprecated defines for the bit fields in the EEPROM_EEPROMPP register. +// +//***************************************************************************** +#define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size +#define EEPROM_EEPROMPP_SIZE_S 0 + +#endif + +#endif // __LM4F120H5QR_H__ diff --git a/cpu/stellaris_common/include/hw_adc.h b/cpu/stellaris_common/include/hw_adc.h new file mode 100644 index 0000000000..bb47ad96d4 --- /dev/null +++ b/cpu/stellaris_common/include/hw_adc.h @@ -0,0 +1,1352 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer +#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status +#define ADC_O_IM 0x00000008 // ADC Interrupt Mask +#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear +#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status +#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select +#define ADC_O_USTAT 0x00000018 // ADC Underflow Status +#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select +#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority +#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control +#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence + // Initiate +#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control +#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt + // Status and Clear +#define ADC_O_CTL 0x00000038 // ADC Control +#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input + // Multiplexer Select 0 +#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0 +#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO + // 0 +#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0 + // Status +#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation +#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital + // Comparator Select +#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended + // Input Multiplexer Select 0 +#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input + // Multiplexer Select 1 +#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1 +#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO + // 1 +#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1 + // Status +#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation +#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital + // Comparator Select +#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended + // Input Multiplexer Select 1 +#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input + // Multiplexer Select 2 +#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2 +#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO + // 2 +#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2 + // Status +#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation +#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital + // Comparator Select +#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended + // Input Multiplexer Select 2 +#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input + // Multiplexer Select 3 +#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3 +#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO + // 3 +#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3 + // Status +#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation +#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital + // Comparator Select +#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended + // Input Multiplexer Select 3 +#define ADC_O_TMLB 0x00000100 // ADC Test Mode Loopback +#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset + // Initial Conditions +#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0 +#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1 +#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2 +#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3 +#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4 +#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5 +#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6 +#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7 +#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0 +#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1 +#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2 +#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3 +#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4 +#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 +#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 +#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 +#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties +#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration +#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status +#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3 +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2 +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1 +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0 +#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0 +#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4) +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 +#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3 +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4) +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 +#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3 +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4) +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 +#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3 +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4) +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 +#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3 +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +#define ADC_TSSEL_PS3_M 0x30000000 // PWM Unit Select +#define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS3_1 0x10000000 // PWM Unit 1 +#define ADC_TSSEL_PS2_M 0x00300000 // PWM Unit Select +#define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS2_1 0x00100000 // PWM Unit 1 +#define ADC_TSSEL_PS1_M 0x00003000 // PWM Unit Select +#define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS1_1 0x00001000 // PWM Unit 1 +#define ADC_TSSEL_PS0_M 0x00000030 // PWM Unit Select +#define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0 +#define ADC_TSSEL_PS0_1 0x00000010 // PWM Unit 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +#define ADC_CTL_RES 0x00000010 // Sample Resolution +#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select +#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the + // voltage reference +#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is + // the voltage reference. The ADC + // conversion range is 0.0 V to the + // external reference value +#define ADC_CTL_VREF_EXT_1V 0x00000003 // A 1.0 V external VREFA input is + // the voltage reference. The ADC + // conversion range is 0.0 V to + // three times the external + // reference value +#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. +// +//***************************************************************************** +#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. +// +//***************************************************************************** +#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. +// +//***************************************************************************** +#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. +// +//***************************************************************************** +#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the + // PLL bypass is in effect) or the + // 16 MHz clock derived from PLL / + // 25 (default) +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC + +//***************************************************************************** +// +// The following are defines for the the interpretation of the data in the +// SSFIFOx when the ADC TMLB is enabled. +// +//***************************************************************************** +#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter +#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator +#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator +#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator +#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator +#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift +#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_O_EMUX +// register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_O_SSPRI +// register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask + +//***************************************************************************** +// +// The following are deprecated defines for the ADC sequence register offsets.. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSMUX0, +// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present +// in all registers.. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSCTL0, +// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present +// in all registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSFIFO0, +// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0, +// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following are deprecated defines for the the interpretation of the data +// in the SSFIFOx when the ADC TMLB is enabled. +// +//***************************************************************************** +#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter +#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator +#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator +#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator +#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator +#define ADC_TMLB_CNT_S 6 // Sample counter shift +#define ADC_TMLB_MUX_S 0 // Input channel number shift + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the loopback ADC +// data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif + +#endif // __HW_ADC_H__ diff --git a/cpu/stellaris_common/include/hw_gpio.h b/cpu/stellaris_common/include/hw_gpio.h new file mode 100644 index 0000000000..0c17b900db --- /dev/null +++ b/cpu/stellaris_common/include/hw_gpio.h @@ -0,0 +1,192 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // GPIO Data +#define GPIO_O_DIR 0x00000400 // GPIO Direction +#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense +#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges +#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event +#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask +#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status +#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status +#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear +#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select +#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select +#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select +#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select +#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select +#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select +#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select +#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select +#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable +#define GPIO_O_LOCK 0x00000520 // GPIO Lock +#define GPIO_O_CR 0x00000524 // GPIO Commit +#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select +#define GPIO_O_PCTL 0x0000052C // GPIO Port Control +#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control +#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control +#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable +#define GPIO_IM_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status +#define GPIO_RIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status +#define GPIO_MIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear +#define GPIO_ICR_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock +#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked + // and may be modified +#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked + // and may not be modified +#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register +#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on + // DustDevil-class devices and + // later + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_SI register. +// +//***************************************************************************** +#define GPIO_SI_SUM 0x00000001 // Summary Interrupt + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_PeriphID4 0x00000FD0 +#define GPIO_O_PeriphID5 0x00000FD4 +#define GPIO_O_PeriphID6 0x00000FD8 +#define GPIO_O_PeriphID7 0x00000FDC +#define GPIO_O_PeriphID0 0x00000FE0 +#define GPIO_O_PeriphID1 0x00000FE4 +#define GPIO_O_PeriphID2 0x00000FE8 +#define GPIO_O_PeriphID3 0x00000FEC +#define GPIO_O_PCellID0 0x00000FF0 +#define GPIO_O_PCellID1 0x00000FF4 +#define GPIO_O_PCellID2 0x00000FF8 +#define GPIO_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV +#define GPIO_RV_PCellID1 0x000000F0 +#define GPIO_RV_PCellID3 0x000000B1 +#define GPIO_RV_PeriphID0 0x00000061 +#define GPIO_RV_PeriphID1 0x00000010 +#define GPIO_RV_PCellID0 0x0000000D +#define GPIO_RV_PCellID2 0x00000005 +#define GPIO_RV_PeriphID2 0x00000004 +#define GPIO_RV_LOCK 0x00000001 // Lock register RV +#define GPIO_RV_PeriphID7 0x00000000 +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV +#define GPIO_RV_PeriphID4 0x00000000 +#define GPIO_RV_PeriphID5 0x00000000 +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV +#define GPIO_RV_PeriphID6 0x00000000 +#define GPIO_RV_PeriphID3 0x00000000 +#define GPIO_RV_DATA 0x00000000 // Data register reset value +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV + +#endif + +#endif // __HW_GPIO_H__ diff --git a/cpu/stellaris_common/include/hw_hibernate.h b/cpu/stellaris_common/include/hw_hibernate.h new file mode 100644 index 0000000000..a6c8e347cf --- /dev/null +++ b/cpu/stellaris_common/include/hw_hibernate.h @@ -0,0 +1,286 @@ +//***************************************************************************** +// +// hw_hibernate.h - Defines and Macros for the Hibernation module. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_HIBERNATE_H__ +#define __HW_HIBERNATE_H__ + +//***************************************************************************** +// +// The following are defines for the Hibernation module register addresses. +// +//***************************************************************************** +#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter +#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 +#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1 +#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load +#define HIB_CTL 0x400FC010 // Hibernation Control +#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask +#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status +#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt + // Status +#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear +#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim +#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds +#define HIB_DATA 0x400FC030 // Hibernation Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM1 register. +// +//***************************************************************************** +#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1 +#define HIB_RTCM1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered +#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable +#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable +#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable +#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable +#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable +#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select +#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request +#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask +#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask +#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Mask +#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask +#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status +#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt + // Status +#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw + // Interrupt Status +#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status +#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Status +#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Status +#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt + // Status +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Clear +#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Clear +#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Clear +#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt + // Clear +#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the Hibernation module register +// addresses. +// +//***************************************************************************** +#define HIB_DATA_END 0x400FC130 // end of data area, exclusive + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_RTCC +// register. +// +//***************************************************************************** +#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_RTCM0 +// register. +// +//***************************************************************************** +#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_RTCM1 +// register. +// +//***************************************************************************** +#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_RTCLD +// register. +// +//***************************************************************************** +#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_RIS +// register. +// +//***************************************************************************** +#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_MIS +// register. +// +//***************************************************************************** +#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_RTCT +// register. +// +//***************************************************************************** +#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the HIB_DATA +// register. +// +//***************************************************************************** +#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask + +#endif + +#endif // __HW_HIBERNATE_H__ diff --git a/cpu/stellaris_common/include/hw_i2c.h b/cpu/stellaris_common/include/hw_i2c.h new file mode 100644 index 0000000000..8c79b0587b --- /dev/null +++ b/cpu/stellaris_common/include/hw_i2c.h @@ -0,0 +1,489 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 // I2C Master Slave Address +#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address +#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status +#define I2C_O_MCS 0x00000004 // I2C Master Control/Status +#define I2C_O_SDR 0x00000008 // I2C Slave Data +#define I2C_O_MDR 0x00000008 // I2C Master Data +#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period +#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask +#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status +#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask +#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status +#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt + // Status +#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear +#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt + // Status +#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear +#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2 +#define I2C_O_MCR 0x00000020 // I2C Master Configuration +#define I2C_O_SACKCTL 0x00000020 // I2C Slave ACK Control +#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout + // Count +#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor +#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties +#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_RS 0x00000001 // Receive not send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +#define I2C_SCSR_RREQ 0x00000001 // Receive Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_QCMD 0x00000020 // Quick Command +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_STOP 0x00000004 // Generate STOP +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_START 0x00000002 // Generate START +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable +#define I2C_MCS_BUSY 0x00000001 // I2C Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SIMR +// register. +// +//***************************************************************************** +#define I2C_SIMR_IM 0x00000001 // Interrupt Mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SRIS +// register. +// +//***************************************************************************** +#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SMIS +// register. +// +//***************************************************************************** +#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SICR +// register. +// +//***************************************************************************** +#define I2C_SICR_IC 0x00000001 // Clear Interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the I2C master register offsets. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following are deprecated defines for the I2C slave register offsets. +// +//***************************************************************************** +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C master +// slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Control and Status register. +// +//***************************************************************************** +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ERR_MASK 0x0000001C +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run + +//***************************************************************************** +// +// The following are deprecated defines for the values used in determining the +// contents of the I2C Master Timer Period register. +// +//***************************************************************************** +#define I2C_SCL_FAST 400000 // SCL fast frequency +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Interrupt Mask register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Raw Interrupt Status register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Masked Interrupt Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Interrupt Clear register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Configuration register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave Own +// Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Control/Status register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Interrupt Mask register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave Raw +// Interrupt Status register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Masked Interrupt Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Interrupt Clear register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif + +#endif // __HW_I2C_H__ diff --git a/cpu/stellaris_common/include/hw_ints.h b/cpu/stellaris_common/include/hw_ints.h new file mode 100644 index 0000000000..6323de9e41 --- /dev/null +++ b/cpu/stellaris_common/include/hw_ints.h @@ -0,0 +1,217 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI0 23 // SSI0 Rx and Tx +#define INT_I2C0 24 // I2C0 Master and Slave +#define INT_PWM0_FAULT 25 // PWM0 Fault +#define INT_PWM0_0 26 // PWM0 Generator 0 +#define INT_PWM0_1 27 // PWM0 Generator 1 +#define INT_PWM0_2 28 // PWM0 Generator 2 +#define INT_QEI0 29 // Quadrature Encoder 0 +#define INT_ADC0SS0 30 // ADC0 Sequence 0 +#define INT_ADC0SS1 31 // ADC0 Sequence 1 +#define INT_ADC0SS2 32 // ADC0 Sequence 2 +#define INT_ADC0SS3 33 // ADC0 Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control +#define INT_GPIOF 46 // GPIO Port F +#define INT_GPIOG 47 // GPIO Port G +#define INT_GPIOH 48 // GPIO Port H +#define INT_UART2 49 // UART2 Rx and Tx +#define INT_SSI1 50 // SSI1 Rx and Tx +#define INT_TIMER3A 51 // Timer 3 subtimer A +#define INT_TIMER3B 52 // Timer 3 subtimer B +#define INT_I2C1 53 // I2C1 Master and Slave +#define INT_QEI1 54 // Quadrature Encoder 1 +#define INT_CAN0 55 // CAN0 +#define INT_CAN1 56 // CAN1 +#define INT_CAN2 57 // CAN2 +#define INT_ETH 58 // Ethernet +#define INT_HIBERNATE 59 // Hibernation module +#define INT_USB0 60 // USB 0 Controller +#define INT_PWM0_3 61 // PWM0 Generator 3 +#define INT_UDMA 62 // uDMA controller +#define INT_UDMAERR 63 // uDMA Error +#define INT_ADC1SS0 64 // ADC1 Sequence 0 +#define INT_ADC1SS1 65 // ADC1 Sequence 1 +#define INT_ADC1SS2 66 // ADC1 Sequence 2 +#define INT_ADC1SS3 67 // ADC1 Sequence 3 +#define INT_I2S0 68 // I2S0 +#define INT_EPI0 69 // EPI0 +#define INT_GPIOJ 70 // GPIO Port J +#define INT_GPIOK 71 // GPIO Port K +#define INT_GPIOL 72 // GPIO Port L +#define INT_SSI2 73 // SSI2 +#define INT_SSI3 74 // SSI3 +#define INT_UART3 75 // UART3 +#define INT_UART4 76 // UART4 +#define INT_UART5 77 // UART5 +#define INT_UART6 78 // UART6 +#define INT_UART7 79 // UART7 +#define INT_I2C2 84 // I2C2 +#define INT_I2C3 85 // I2C3 +#define INT_TIMER4A 86 // Timer 4A +#define INT_TIMER4B 87 // Timer 4B +#define INT_TIMER5A 108 // Timer 5A +#define INT_TIMER5B 109 // Timer 5B +#define INT_WTIMER0A 110 // Wide Timer 0A +#define INT_WTIMER0B 111 // Wide Timer 0B +#define INT_WTIMER1A 112 // Wide Timer 1A +#define INT_WTIMER1B 113 // Wide Timer 1B +#define INT_WTIMER2A 114 // Wide Timer 2A +#define INT_WTIMER2B 115 // Wide Timer 2B +#define INT_WTIMER3A 116 // Wide Timer 3A +#define INT_WTIMER3B 117 // Wide Timer 3B +#define INT_WTIMER4A 118 // Wide Timer 4A +#define INT_WTIMER4B 119 // Wide Timer 4B +#define INT_WTIMER5A 120 // Wide Timer 5A +#define INT_WTIMER5B 121 // Wide Timer 5B +#define INT_SYSEXC 122 // System Exception (imprecise) +#define INT_PECI0 123 // PECI 0 +#define INT_LPC0 124 // LPC 0 +#define INT_I2C4 125 // I2C4 +#define INT_I2C5 126 // I2C5 +#define INT_GPIOM 127 // GPIO Port M +#define INT_GPION 128 // GPIO Port N +#define INT_FAN0 130 // FAN 0 +#define INT_GPIOP0 132 // GPIO Port P (Summary or P0) +#define INT_GPIOP1 133 // GPIO Port P1 +#define INT_GPIOP2 134 // GPIO Port P2 +#define INT_GPIOP3 135 // GPIO Port P3 +#define INT_GPIOP4 136 // GPIO Port P4 +#define INT_GPIOP5 137 // GPIO Port P5 +#define INT_GPIOP6 138 // GPIO Port P6 +#define INT_GPIOP7 139 // GPIO Port P7 +#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1 141 // GPIO Port Q1 +#define INT_GPIOQ2 142 // GPIO Port Q2 +#define INT_GPIOQ3 143 // GPIO Port Q3 +#define INT_GPIOQ4 144 // GPIO Port Q4 +#define INT_GPIOQ5 145 // GPIO Port Q5 +#define INT_GPIOQ6 146 // GPIO Port Q6 +#define INT_GPIOQ7 147 // GPIO Port Q7 +#define INT_PWM1_0 150 // PWM1 Generator 0 +#define INT_PWM1_1 151 // PWM1 Generator 1 +#define INT_PWM1_2 152 // PWM1 Generator 2 +#define INT_PWM1_3 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT 154 // PWM1 Fault + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 155 + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_PWM3 61 // PWM Generator 3 + +#endif + +#endif // __HW_INTS_H__ diff --git a/cpu/stellaris_common/include/hw_memmap.h b/cpu/stellaris_common/include/hw_memmap.h new file mode 100644 index 0000000000..9f9201c0e0 --- /dev/null +++ b/cpu/stellaris_common/include/hw_memmap.h @@ -0,0 +1,164 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG0_BASE 0x40000000 // Watchdog0 +#define WATCHDOG1_BASE 0x40001000 // Watchdog1 +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define SSI2_BASE 0x4000A000 // SSI2 +#define SSI3_BASE 0x4000B000 // SSI3 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define UART3_BASE 0x4000F000 // UART3 +#define UART4_BASE 0x40010000 // UART4 +#define UART5_BASE 0x40011000 // UART5 +#define UART6_BASE 0x40012000 // UART6 +#define UART7_BASE 0x40013000 // UART7 +#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master +#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave +#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master +#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave +#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master +#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave +#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master +#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) +#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define TIMER4_BASE 0x40034000 // Timer4 +#define TIMER5_BASE 0x40035000 // Timer5 +#define WTIMER0_BASE 0x40036000 // Wide Timer0 +#define WTIMER1_BASE 0x40037000 // Wide Timer1 +#define ADC0_BASE 0x40038000 // ADC0 +#define ADC1_BASE 0x40039000 // ADC1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define CAN2_BASE 0x40042000 // CAN2 +#define ETH_BASE 0x40048000 // Ethernet +#define MAC_BASE 0x40048000 // Ethernet +#define WTIMER2_BASE 0x4004C000 // Wide Timer2 +#define WTIMER3_BASE 0x4004D000 // Wide Timer3 +#define WTIMER4_BASE 0x4004E000 // Wide Timer4 +#define WTIMER5_BASE 0x4004F000 // Wide Timer5 +#define USB0_BASE 0x40050000 // USB 0 Controller +#define I2S0_BASE 0x40054000 // I2S0 +#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) +#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) +#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K +#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L +#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M +#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N +#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P +#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q +#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC) +#define FAN0_BASE 0x40084000 // Fan Control (FAN) +#define EEPROM_BASE 0x400AF000 // EEPROM memory +#define PECI0_BASE 0x400B0000 // Platform Environment Control + // Interface (PECI) +#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master +#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave +#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master +#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave +#define EPI0_BASE 0x400D0000 // EPI0 +#define SYSEXC_BASE 0x400F9000 // System Exception Module +#define HIB_BASE 0x400FC000 // Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define UDMA_BASE 0x400FF000 // uDMA Controller +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the base address of the memories +// and peripherals. +// +//***************************************************************************** +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define SSI_BASE 0x40008000 // SSI +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define ADC_BASE 0x40038000 // ADC + +#endif + +#endif // __HW_MEMMAP_H__ diff --git a/cpu/stellaris_common/include/hw_nvic.h b/cpu/stellaris_common/include/hw_nvic.h new file mode 100644 index 0000000000..ae2b582e31 --- /dev/null +++ b/cpu/stellaris_common/include/hw_nvic.h @@ -0,0 +1,1717 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-138 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control +#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address +#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +#endif // __HW_NVIC_H__ diff --git a/cpu/stellaris_common/include/hw_pwm.h b/cpu/stellaris_common/include/hw_pwm.h new file mode 100644 index 0000000000..dd3b01da41 --- /dev/null +++ b/cpu/stellaris_common/include/hw_pwm.h @@ -0,0 +1,2020 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// The following are defines for the PWM register offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion +#define PWM_O_FAULT 0x00000010 // PWM Output Fault +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable +#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear +#define PWM_O_STATUS 0x00000020 // PWM Status +#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value +#define PWM_O_ENUPD 0x00000028 // PWM Enable Update +#define PWM_O_0_CTL 0x00000040 // PWM0 Control +#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger + // Enable +#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status +#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear +#define PWM_O_0_LOAD 0x00000050 // PWM0 Load +#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter +#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A +#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B +#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control +#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control +#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control +#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay +#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band + // Falling-Edge-Delay +#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 +#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 +#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period +#define PWM_O_1_CTL 0x00000080 // PWM1 Control +#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger + // Enable +#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status +#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear +#define PWM_O_1_LOAD 0x00000090 // PWM1 Load +#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter +#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A +#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B +#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control +#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control +#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control +#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay +#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band + // Falling-Edge-Delay +#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 +#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 +#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period +#define PWM_O_2_CTL 0x000000C0 // PWM2 Control +#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger + // Enable +#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status +#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear +#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load +#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter +#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A +#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B +#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control +#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control +#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control +#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay +#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band + // Falling-Edge-Delay +#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 +#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 +#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period +#define PWM_O_3_CTL 0x00000100 // PWM3 Control +#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger + // Enable +#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status +#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear +#define PWM_O_3_LOAD 0x00000110 // PWM3 Load +#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter +#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A +#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B +#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control +#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control +#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control +#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay +#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band + // Falling-Edge-Delay +#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 +#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 +#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period +#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense +#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 +#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 +#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense +#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 +#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 +#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense +#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 +#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 +#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense +#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 +#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 +#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties +#define PWM_O_PC 0x00000FC4 // PWM Peripheral Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CTL register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_SYNC register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENABLE register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable +#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INVERT register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal +#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal +#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal +#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal +#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal +#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal +#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal +#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULT register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault +#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 +#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 +#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 +#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 +#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted +#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted +#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_STATUS register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status +#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status +#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status +#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value +#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value +#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value +#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value +#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value +#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value +#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value +#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENUPD register. +// +//***************************************************************************** +#define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode +#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized +#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized +#define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode +#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized +#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized +#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode +#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized +#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized +#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode +#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized +#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized +#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode +#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized +#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized +#define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode +#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized +#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized +#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode +#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized +#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized +#define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode +#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized +#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CTL register. +// +//***************************************************************************** +#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for + // the PWMnDBFALL register +#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_0_CTL_MODE 0x00000002 // Counter Mode +#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_INTEN register. +// +//***************************************************************************** +#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B + // Down +#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B + // Up +#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A + // Down +#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A + // Up +#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load +#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator + // B Down +#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator + // B Up +#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator + // A Down +#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator + // A Up +#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load +#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_RIS register. +// +//***************************************************************************** +#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_ISC register. +// +//***************************************************************************** +#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_LOAD register. +// +//***************************************************************************** +#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_0_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_COUNT register. +// +//***************************************************************************** +#define PWM_0_COUNT_M 0x0000FFFF // Counter Value +#define PWM_0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPA register. +// +//***************************************************************************** +#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_0_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPB register. +// +//***************************************************************************** +#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_0_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENA register. +// +//***************************************************************************** +#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_0_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_0_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_0_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_0_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENB register. +// +//***************************************************************************** +#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_0_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_0_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_0_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_0_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBCTL register. +// +//***************************************************************************** +#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBRISE register. +// +//***************************************************************************** +#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_0_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBFALL register. +// +//***************************************************************************** +#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_0_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_0_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CTL register. +// +//***************************************************************************** +#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for + // the PWMnDBFALL register +#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_1_CTL_MODE 0x00000002 // Counter Mode +#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_INTEN register. +// +//***************************************************************************** +#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B + // Down +#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B + // Up +#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A + // Down +#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A + // Up +#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load +#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator + // B Down +#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator + // B Up +#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator + // A Down +#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator + // A Up +#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load +#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_RIS register. +// +//***************************************************************************** +#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_ISC register. +// +//***************************************************************************** +#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_LOAD register. +// +//***************************************************************************** +#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_1_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_COUNT register. +// +//***************************************************************************** +#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_1_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPA register. +// +//***************************************************************************** +#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_1_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPB register. +// +//***************************************************************************** +#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_1_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENA register. +// +//***************************************************************************** +#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_1_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_1_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_1_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_1_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENB register. +// +//***************************************************************************** +#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_1_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_1_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_1_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_1_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBCTL register. +// +//***************************************************************************** +#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBRISE register. +// +//***************************************************************************** +#define PWM_1_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_1_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBFALL register. +// +//***************************************************************************** +#define PWM_1_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_1_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_1_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CTL register. +// +//***************************************************************************** +#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for + // the PWMnDBFALL register +#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_2_CTL_MODE 0x00000002 // Counter Mode +#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_INTEN register. +// +//***************************************************************************** +#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B + // Down +#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B + // Up +#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A + // Down +#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A + // Up +#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load +#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator + // B Down +#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator + // B Up +#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator + // A Down +#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator + // A Up +#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load +#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_RIS register. +// +//***************************************************************************** +#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_ISC register. +// +//***************************************************************************** +#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_LOAD register. +// +//***************************************************************************** +#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_2_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_COUNT register. +// +//***************************************************************************** +#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_2_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPA register. +// +//***************************************************************************** +#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_2_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPB register. +// +//***************************************************************************** +#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_2_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENA register. +// +//***************************************************************************** +#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_2_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_2_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_2_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_2_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENB register. +// +//***************************************************************************** +#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_2_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_2_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_2_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_2_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBCTL register. +// +//***************************************************************************** +#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBRISE register. +// +//***************************************************************************** +#define PWM_2_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_2_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBFALL register. +// +//***************************************************************************** +#define PWM_2_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_2_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_2_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CTL register. +// +//***************************************************************************** +#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for + // the PWMnDBFALL register +#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_3_CTL_MODE 0x00000002 // Counter Mode +#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_INTEN register. +// +//***************************************************************************** +#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B + // Down +#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B + // Up +#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A + // Down +#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A + // Up +#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load +#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator + // B Down +#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator + // B Up +#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator + // A Down +#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator + // A Up +#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load +#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_RIS register. +// +//***************************************************************************** +#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_ISC register. +// +//***************************************************************************** +#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_LOAD register. +// +//***************************************************************************** +#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_3_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_COUNT register. +// +//***************************************************************************** +#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_3_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPA register. +// +//***************************************************************************** +#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_3_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPB register. +// +//***************************************************************************** +#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_3_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENA register. +// +//***************************************************************************** +#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_3_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_3_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_3_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_3_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENB register. +// +//***************************************************************************** +#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal +#define PWM_3_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0 +#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1 +#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal +#define PWM_3_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0 +#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1 +#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal +#define PWM_3_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0 +#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1 +#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal +#define PWM_3_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0 +#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1 +#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load +#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal +#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0 +#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1 +#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert the output signal +#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0 +#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBCTL register. +// +//***************************************************************************** +#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBRISE register. +// +//***************************************************************************** +#define PWM_3_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_3_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBFALL register. +// +//***************************************************************************** +#define PWM_3_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_3_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 +#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 +#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_3_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. +// +//***************************************************************************** +#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. +// +//***************************************************************************** +#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. +// +//***************************************************************************** +#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. +// +//***************************************************************************** +#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +#define PWM_PP_GCNT_M 0x0000000F // Generators +#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs +#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization +#define PWM_PP_EFAULT 0x00000200 // Extended Fault +#define PWM_PP_ONE 0x00000400 // One-Shot Mode +#define PWM_PP_GCNT_S 0 +#define PWM_PP_FCNT_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PC register. +// +//***************************************************************************** +#define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor +#define PWM_PC_PWMDIV_2 0x00000000 // /2 +#define PWM_PC_PWMDIV_4 0x00000001 // /4 +#define PWM_PC_PWMDIV_8 0x00000002 // /8 +#define PWM_PC_PWMDIV_16 0x00000003 // /16 +#define PWM_PC_PWMDIV_32 0x00000004 // /32 +#define PWM_PC_PWMDIV_64 0x00000007 // /64 (default) +#define PWM_PC_USEPWMDIV 0x00000100 // Enable PWM Clock Divisor + +//***************************************************************************** +// +// The following are defines for the PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg +#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition +#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition +#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base +#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CTL register. +// +//***************************************************************************** +#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_X_CTL_MODE 0x00000002 // Counter Mode +#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_INTEN register. +// +//***************************************************************************** +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_RIS register. +// +//***************************************************************************** +#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_ISC register. +// +//***************************************************************************** +#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_LOAD register. +// +//***************************************************************************** +#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_X_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_COUNT register. +// +//***************************************************************************** +#define PWM_X_COUNT_M 0x0000FFFF // Counter Value +#define PWM_X_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPA register. +// +//***************************************************************************** +#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_X_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPB register. +// +//***************************************************************************** +#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_X_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENA register. +// +//***************************************************************************** +#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_X_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_X_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_X_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_X_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_X_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_X_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_X_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_X_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENB register. +// +//***************************************************************************** +#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_X_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_X_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_X_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_X_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_X_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_X_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_X_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_X_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBCTL register. +// +//***************************************************************************** +#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBRISE register. +// +//***************************************************************************** +#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_X_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBFALL register. +// +//***************************************************************************** +#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_X_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_X_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the PWM Generator extended offsets. +// +//***************************************************************************** +#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense +#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status +#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status +#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base +#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base +#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base +#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. +// +//***************************************************************************** +#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the PWM_O_CTL +// register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the PWM_O_STATUS +// register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status + +//***************************************************************************** +// +// The following are deprecated defines for the PWM Interrupt Register bit +// definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Interrupt Status Register +// bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Generator A/B Control +// Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Generator A/B Control +// Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one +#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero +#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal +#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Dead Band Control +// Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// The following are deprecated defines for the PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output + // pins +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output + // pins +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_X_COUNT 0x00000000 // The current counter value + +#endif + +#endif // __HW_PWM_H__ diff --git a/cpu/stellaris_common/include/hw_ssi.h b/cpu/stellaris_common/include/hw_ssi.h new file mode 100644 index 0000000000..cf75bb7c37 --- /dev/null +++ b/cpu/stellaris_common/include/hw_ssi.h @@ -0,0 +1,244 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following are defines for the SSI register offsets. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // SSI Control 0 +#define SSI_O_CR1 0x00000004 // SSI Control 1 +#define SSI_O_DR 0x00000008 // SSI Data +#define SSI_O_SR 0x0000000C // SSI Status +#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale +#define SSI_O_IM 0x00000014 // SSI Interrupt Mask +#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status +#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status +#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear +#define SSI_O_DMACTL 0x00000024 // SSI DMA Control +#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate +#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase +#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity +#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select +#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format +#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous + // Serial Frame Format +#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select +#define SSI_CR0_DSS_4 0x00000003 // 4-bit data +#define SSI_CR0_DSS_5 0x00000004 // 5-bit data +#define SSI_CR0_DSS_6 0x00000005 // 6-bit data +#define SSI_CR0_DSS_7 0x00000006 // 7-bit data +#define SSI_CR0_DSS_8 0x00000007 // 8-bit data +#define SSI_CR0_DSS_9 0x00000008 // 9-bit data +#define SSI_CR0_DSS_10 0x00000009 // 10-bit data +#define SSI_CR0_DSS_11 0x0000000A // 11-bit data +#define SSI_CR0_DSS_12 0x0000000B // 12-bit data +#define SSI_CR0_DSS_13 0x0000000C // 13-bit data +#define SSI_CR0_DSS_14 0x0000000D // 14-bit data +#define SSI_CR0_DSS_15 0x0000000E // 15-bit data +#define SSI_CR0_DSS_16 0x0000000F // 16-bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +#define SSI_CR1_EOT 0x00000010 // End of Transmission +#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable +#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select +#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port + // Enable +#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI Busy Bit +#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full +#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty +#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full +#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the + // PLL bypass is in effect) or the + // PLL output (default) +#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SSI_O_CR0 +// register. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_DSS 0x0000000F // Data size select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SSI_O_CPSR +// register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following are deprecated defines for the SSI controller's FIFO size. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the interrupt +// mask set and clear, raw interrupt, masked interrupt, and interrupt clear +// registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif + +#endif // __HW_SSI_H__ diff --git a/cpu/stellaris_common/include/hw_sysctl.h b/cpu/stellaris_common/include/hw_sysctl.h new file mode 100644 index 0000000000..70ab4d49bf --- /dev/null +++ b/cpu/stellaris_common/include/hw_sysctl.h @@ -0,0 +1,3676 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following are defines for the System Control register addresses. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400FE000 // Device Identification 0 +#define SYSCTL_DID1 0x400FE004 // Device Identification 1 +#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0 +#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1 +#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2 +#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3 +#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4 +#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5 +#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6 +#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7 +#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 ADC + // Channels +#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control +#define SYSCTL_LDOPCTL 0x400FE034 // LDO Power Control +#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0 +#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1 +#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2 +#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status +#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control +#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and + // Clear +#define SYSCTL_RESC 0x400FE05C // Reset Cause +#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration +#define SYSCTL_PLLCFG 0x400FE064 // XTAL to PLL Translation +#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus + // Control +#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2 +#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control +#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control + // Register 0 +#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control + // Register 1 +#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control + // Register 2 +#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control + // Register 0 +#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control + // Register 1 +#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control + // Register 2 +#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating + // Control Register 0 +#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating + // Control Register 1 +#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating + // Control Register 2 +#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration +#define SYSCTL_SYSPROP 0x400FE14C // System Properties +#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator + // Calibration +#define SYSCTL_CLKVCLR 0x400FE150 // Clock Verification Clear +#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator + // Statistics +#define SYSCTL_LDOARST 0x400FE160 // Allow Unregulated LDO to Reset + // the Part +#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 +#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1 +#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status +#define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration +#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 ADC + // Digital Comparators +#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information +#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral + // Present +#define SYSCTL_PPTIMER 0x400FE304 // Timer Peripheral Present +#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output + // Peripheral Present +#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access + // Peripheral Present +#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present +#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Present +#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface + // Peripheral Present +#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit + // Peripheral Present +#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral + // Present +#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network + // Peripheral Present +#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter + // Peripheral Present +#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral + // Present +#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral + // Present +#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface + // Peripheral Present +#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface + // Peripheral Present +#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control + // Interface Peripheral Present +#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present +#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present +#define SYSCTL_PPWTIMER 0x400FE35C // Wide Timer Peripheral Present +#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset +#define SYSCTL_SRTIMER 0x400FE504 // Timer Software Reset +#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output + // Software Reset +#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access + // Software Reset +#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset +#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous + // Receiver/Transmitter Software + // Reset +#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface + // Software Reset +#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit + // Software Reset +#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software + // Reset +#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software + // Reset +#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter + // Software Reset +#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset +#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software + // Reset +#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface + // Software Reset +#define SYSCTL_SRLPC 0x400FE548 // Low Pin Count Interface Software + // Reset +#define SYSCTL_SRPECI 0x400FE550 // Platform Environment Control + // Interface Software Reset +#define SYSCTL_SRFAN 0x400FE554 // Fan Software Reset +#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset +#define SYSCTL_SRWTIMER 0x400FE55C // Wide Timer Software Reset +#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock + // Gating Control +#define SYSCTL_RCGCTIMER 0x400FE604 // Timer Run Mode Clock Gating + // Control +#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run + // Mode Clock Gating Control +#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run + // Mode Clock Gating Control +#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous + // Receiver/Transmitter Run Mode + // Clock Gating Control +#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run + // Mode Clock Gating Control +#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode + // Clock Gating Control +#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode + // Clock Gating Control +#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run + // Mode Clock Gating Control +#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode + // Clock Gating Control +#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCLPC 0x400FE648 // Low Pin Count Interface Run Mode + // Clock Gating Control +#define SYSCTL_RCGCPECI 0x400FE650 // Platform Environment Control + // Interface Run Mode Clock Gating + // Control +#define SYSCTL_RCGCFAN 0x400FE654 // Fan Run Mode Clock Gating + // Control +#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER 0x400FE65C // Wide Timer Run Mode Clock Gating + // Control +#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCTIMER 0x400FE704 // Timer Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous + // Receiver/Transmitter Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCLPC 0x400FE748 // Low Pin Count Interface Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCPECI 0x400FE750 // Platform Environment Control + // Interface Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCFAN 0x400FE754 // Fan Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER 0x400FE75C // Wide Timer Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCTIMER 0x400FE804 // Timer Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous + // Receiver/Transmitter Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCLPC 0x400FE848 // Low Pin Count Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCPECI 0x400FE850 // Platform Environment Control + // Interface Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCFAN 0x400FE854 // Fan Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER 0x400FE85C // Wide Timer Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control +#define SYSCTL_PCTIMER 0x400FE904 // Timer Power Control +#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output + // Power Control +#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power + // Control +#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control +#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous + // Receiver/Transmitter Power + // Control +#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface + // Power Control +#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power + // Control +#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power + // Control +#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power + // Control +#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter + // Power Control +#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control +#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power + // Control +#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface + // Power Control +#define SYSCTL_PCLPC 0x400FE948 // Low Pin Count Interface Power + // Control +#define SYSCTL_PCPECI 0x400FE950 // Platform Environment Control + // Interface Power Control +#define SYSCTL_PCFAN 0x400FE954 // Fan Power Control +#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control +#define SYSCTL_PCWTIMER 0x400FE95C // Wide Timer Power Control +#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready +#define SYSCTL_PRTIMER 0x400FEA04 // Timer Peripheral Ready +#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output + // Peripheral Ready +#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access + // Peripheral Ready +#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready +#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Ready +#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface + // Peripheral Ready +#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit + // Peripheral Ready +#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral + // Ready +#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network + // Peripheral Ready +#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter + // Peripheral Ready +#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral + // Ready +#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral + // Ready +#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface + // Peripheral Ready +#define SYSCTL_PRLPC 0x400FEA48 // Low Pin Count Interface + // Peripheral Ready +#define SYSCTL_PRPECI 0x400FEA50 // Platform Environment Control + // Interface Peripheral Ready +#define SYSCTL_PRFAN 0x400FEA54 // Fan Peripheral Ready +#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready +#define SYSCTL_PRWTIMER 0x400FEA5C // Wide Timer Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version +#define SYSCTL_DID0_VER_0 0x00000000 // Initial DID0 register format + // definition for Stellaris(R) + // Sandstorm-class devices +#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 + // register format +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_SANDSTORM \ + 0x00000000 // Sandstorm-class Device +#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(R) Fury-class devices +#define SYSCTL_DID0_CLASS_DUSTDEVIL \ + 0x00030000 // Stellaris(R) DustDevil-class + // devices +#define SYSCTL_DID0_CLASS_TEMPEST \ + 0x00040000 // Stellaris(R) Tempest-class + // microcontrollers +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Stellaris(R) Blizzard-class + // microcontrollers +#define SYSCTL_DID0_CLASS_FIRESTORM \ + 0x00060000 // Stellaris(R) Firestorm-class + // microcontrollers +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision +#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major + // revision update +#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change +#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change +#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 +#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 +#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version +#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format + // definition, indicating a + // Stellaris LM3Snnn device +#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1 + // register format +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family +#define SYSCTL_DID1_FAM_STELLARIS \ + 0x00000000 // Stellaris family of + // microcontollers, that is, all + // devices with external part + // numbers starting with LM3S +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 +#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 +#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110 +#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133 +#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138 +#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150 +#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162 +#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165 +#define SYSCTL_DID1_PRTNO_1166 0x00EC0000 // LM3S1166 +#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332 +#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435 +#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439 +#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512 +#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538 +#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601 +#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607 +#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608 +#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620 +#define SYSCTL_DID1_PRTNO_1621 0x00CD0000 // LM3S1621 +#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625 +#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626 +#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627 +#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635 +#define SYSCTL_DID1_PRTNO_1636 0x00EB0000 // LM3S1636 +#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637 +#define SYSCTL_DID1_PRTNO_1651 0x00B10000 // LM3S1651 +#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751 +#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776 +#define SYSCTL_DID1_PRTNO_1811 0x00160000 // LM3S1811 +#define SYSCTL_DID1_PRTNO_1816 0x003D0000 // LM3S1816 +#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850 +#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911 +#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918 +#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937 +#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958 +#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960 +#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968 +#define SYSCTL_DID1_PRTNO_1969 0x00EA0000 // LM3S1969 +#define SYSCTL_DID1_PRTNO_1B21 0x00CE0000 // LM3S1B21 +#define SYSCTL_DID1_PRTNO_1C21 0x00CA0000 // LM3S1C21 +#define SYSCTL_DID1_PRTNO_1C26 0x00CB0000 // LM3S1C26 +#define SYSCTL_DID1_PRTNO_1C58 0x00980000 // LM3S1C58 +#define SYSCTL_DID1_PRTNO_1D21 0x00B00000 // LM3S1D21 +#define SYSCTL_DID1_PRTNO_1D26 0x00CC0000 // LM3S1D26 +#define SYSCTL_DID1_PRTNO_1F11 0x001D0000 // LM3S1F11 +#define SYSCTL_DID1_PRTNO_1F16 0x001B0000 // LM3S1F16 +#define SYSCTL_DID1_PRTNO_1G21 0x00AF0000 // LM3S1G21 +#define SYSCTL_DID1_PRTNO_1G58 0x00950000 // LM3S1G58 +#define SYSCTL_DID1_PRTNO_1H11 0x001E0000 // LM3S1H11 +#define SYSCTL_DID1_PRTNO_1H16 0x001C0000 // LM3S1H16 +#define SYSCTL_DID1_PRTNO_1J11 0x000F0000 // LM3S1J11 +#define SYSCTL_DID1_PRTNO_1J16 0x003C0000 // LM3S1J16 +#define SYSCTL_DID1_PRTNO_1N11 0x000E0000 // LM3S1N11 +#define SYSCTL_DID1_PRTNO_1N16 0x003B0000 // LM3S1N16 +#define SYSCTL_DID1_PRTNO_1P51 0x00B20000 // LM3S1P51 +#define SYSCTL_DID1_PRTNO_1R21 0x009E0000 // LM3S1R21 +#define SYSCTL_DID1_PRTNO_1R26 0x00C90000 // LM3S1R26 +#define SYSCTL_DID1_PRTNO_1W16 0x00300000 // LM3S1W16 +#define SYSCTL_DID1_PRTNO_1Z16 0x002F0000 // LM3S1Z16 +#define SYSCTL_DID1_PRTNO_2016 0x00D40000 // LM3S2016 +#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 +#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 +#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276 +#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 +#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 +#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 +#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 +#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601 +#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608 +#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616 +#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 +#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 +#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 +#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671 +#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678 +#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 +#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 +#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776 +#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793 +#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911 +#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918 +#define SYSCTL_DID1_PRTNO_2919 0x00ED0000 // LM3S2919 +#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 +#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 +#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 +#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 +#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93 +#define SYSCTL_DID1_PRTNO_2D93 0x00940000 // LM3S2D93 +#define SYSCTL_DID1_PRTNO_2U93 0x00930000 // LM3S2U93 +#define SYSCTL_DID1_PRTNO_3634 0x00080000 // LM3S3634 +#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651 +#define SYSCTL_DID1_PRTNO_3654 0x00C80000 // LM3S3654 +#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739 +#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748 +#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749 +#define SYSCTL_DID1_PRTNO_3826 0x00420000 // LM3S3826 +#define SYSCTL_DID1_PRTNO_3J26 0x00410000 // LM3S3J26 +#define SYSCTL_DID1_PRTNO_3N26 0x00400000 // LM3S3N26 +#define SYSCTL_DID1_PRTNO_3W26 0x003F0000 // LM3S3W26 +#define SYSCTL_DID1_PRTNO_3Z26 0x003E0000 // LM3S3Z26 +#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632 +#define SYSCTL_DID1_PRTNO_5651 0x000C0000 // LM3S5651 +#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652 +#define SYSCTL_DID1_PRTNO_5656 0x004D0000 // LM3S5656 +#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662 +#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732 +#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737 +#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739 +#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747 +#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749 +#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752 +#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762 +#define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791 +#define SYSCTL_DID1_PRTNO_5951 0x000B0000 // LM3S5951 +#define SYSCTL_DID1_PRTNO_5956 0x004E0000 // LM3S5956 +#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91 +#define SYSCTL_DID1_PRTNO_5C31 0x002E0000 // LM3S5C31 +#define SYSCTL_DID1_PRTNO_5C36 0x002C0000 // LM3S5C36 +#define SYSCTL_DID1_PRTNO_5C51 0x005E0000 // LM3S5C51 +#define SYSCTL_DID1_PRTNO_5C56 0x005B0000 // LM3S5C56 +#define SYSCTL_DID1_PRTNO_5D51 0x005F0000 // LM3S5D51 +#define SYSCTL_DID1_PRTNO_5D56 0x005C0000 // LM3S5D56 +#define SYSCTL_DID1_PRTNO_5D91 0x00870000 // LM3S5D91 +#define SYSCTL_DID1_PRTNO_5G31 0x002D0000 // LM3S5G31 +#define SYSCTL_DID1_PRTNO_5G36 0x001F0000 // LM3S5G36 +#define SYSCTL_DID1_PRTNO_5G51 0x005D0000 // LM3S5G51 +#define SYSCTL_DID1_PRTNO_5G56 0x004F0000 // LM3S5G56 +#define SYSCTL_DID1_PRTNO_5K31 0x00090000 // LM3S5K31 +#define SYSCTL_DID1_PRTNO_5K36 0x004A0000 // LM3S5K36 +#define SYSCTL_DID1_PRTNO_5P31 0x000A0000 // LM3S5P31 +#define SYSCTL_DID1_PRTNO_5P36 0x00480000 // LM3S5P36 +#define SYSCTL_DID1_PRTNO_5P3B 0x00B60000 // LM3S5P3B +#define SYSCTL_DID1_PRTNO_5P51 0x000D0000 // LM3S5P51 +#define SYSCTL_DID1_PRTNO_5P56 0x004C0000 // LM3S5P56 +#define SYSCTL_DID1_PRTNO_5R31 0x00070000 // LM3S5R31 +#define SYSCTL_DID1_PRTNO_5R36 0x004B0000 // LM3S5R36 +#define SYSCTL_DID1_PRTNO_5T36 0x00470000 // LM3S5T36 +#define SYSCTL_DID1_PRTNO_5U91 0x007F0000 // LM3S5U91 +#define SYSCTL_DID1_PRTNO_5Y36 0x00460000 // LM3S5Y36 +#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 +#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 +#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 +#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 +#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 +#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537 +#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 +#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611 +#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618 +#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 +#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 +#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 +#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753 +#define SYSCTL_DID1_PRTNO_6816 0x00D10000 // LM3S6816 +#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911 +#define SYSCTL_DID1_PRTNO_6916 0x00D30000 // LM3S6916 +#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918 +#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 +#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950 +#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 +#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 +#define SYSCTL_DID1_PRTNO_6C11 0x00AA0000 // LM3S6C11 +#define SYSCTL_DID1_PRTNO_6C65 0x00AC0000 // LM3S6C65 +#define SYSCTL_DID1_PRTNO_6G11 0x009F0000 // LM3S6G11 +#define SYSCTL_DID1_PRTNO_6G65 0x00AB0000 // LM3S6G65 +#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530 +#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538 +#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630 +#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730 +#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733 +#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738 +#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930 +#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933 +#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938 +#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 +#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970 +#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971 +#define SYSCTL_DID1_PRTNO_8C62 0x00AE0000 // LM3S8C62 +#define SYSCTL_DID1_PRTNO_8G62 0x00AD0000 // LM3S8G62 +#define SYSCTL_DID1_PRTNO_9781 0x00CF0000 // LM3S9781 +#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790 +#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792 +#define SYSCTL_DID1_PRTNO_9971 0x002D0000 // LM3S9971 +#define SYSCTL_DID1_PRTNO_9997 0x00200000 // LM3S9997 +#define SYSCTL_DID1_PRTNO_9B81 0x00D00000 // LM3S9B81 +#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90 +#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92 +#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95 +#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96 +#define SYSCTL_DID1_PRTNO_9BN2 0x001D0000 // LM3S9BN2 +#define SYSCTL_DID1_PRTNO_9BN5 0x001E0000 // LM3S9BN5 +#define SYSCTL_DID1_PRTNO_9BN6 0x001F0000 // LM3S9BN6 +#define SYSCTL_DID1_PRTNO_9C97 0x00700000 // LM3S9C97 +#define SYSCTL_DID1_PRTNO_9CN5 0x007A0000 // LM3S9CN5 +#define SYSCTL_DID1_PRTNO_9D81 0x00A90000 // LM3S9D81 +#define SYSCTL_DID1_PRTNO_9D90 0x007E0000 // LM3S9D90 +#define SYSCTL_DID1_PRTNO_9D92 0x00920000 // LM3S9D92 +#define SYSCTL_DID1_PRTNO_9D95 0x00C80000 // LM3S9D95 +#define SYSCTL_DID1_PRTNO_9D96 0x009D0000 // LM3S9D96 +#define SYSCTL_DID1_PRTNO_9DN5 0x007B0000 // LM3S9DN5 +#define SYSCTL_DID1_PRTNO_9DN6 0x007C0000 // LM3S9DN6 +#define SYSCTL_DID1_PRTNO_9G97 0x00600000 // LM3S9G97 +#define SYSCTL_DID1_PRTNO_9GN5 0x00790000 // LM3S9GN5 +#define SYSCTL_DID1_PRTNO_9L71 0x001B0000 // LM3S9L71 +#define SYSCTL_DID1_PRTNO_9L97 0x00180000 // LM3S9L97 +#define SYSCTL_DID1_PRTNO_9U81 0x00A80000 // LM3S9U81 +#define SYSCTL_DID1_PRTNO_9U90 0x007D0000 // LM3S9U90 +#define SYSCTL_DID1_PRTNO_9U92 0x00900000 // LM3S9U92 +#define SYSCTL_DID1_PRTNO_9U95 0x00B70000 // LM3S9U95 +#define SYSCTL_DID1_PRTNO_9U96 0x009B0000 // LM3S9U96 +#define SYSCTL_DID1_PRTNO_LM4F110B2QR \ + 0x00180000 // LM4F110B2QR +#define SYSCTL_DID1_PRTNO_LM4F110C4QR \ + 0x00190000 // LM4F110C4QR +#define SYSCTL_DID1_PRTNO_LM4F110E5QR \ + 0x00100000 // LM4F110E5QR +#define SYSCTL_DID1_PRTNO_LM4F110H5QR \ + 0x00110000 // LM4F110H5QR +#define SYSCTL_DID1_PRTNO_LM4F111B2QR \ + 0x00220000 // LM4F111B2QR +#define SYSCTL_DID1_PRTNO_LM4F111C4QR \ + 0x00230000 // LM4F111C4QR +#define SYSCTL_DID1_PRTNO_LM4F111E5QR \ + 0x00200000 // LM4F111E5QR +#define SYSCTL_DID1_PRTNO_LM4F111H5QR \ + 0x00210000 // LM4F111H5QR +#define SYSCTL_DID1_PRTNO_LM4F112C4QC \ + 0x00360000 // LM4F112C4QC +#define SYSCTL_DID1_PRTNO_LM4F112E5QC \ + 0x00300000 // LM4F112E5QC +#define SYSCTL_DID1_PRTNO_LM4F112H5QC \ + 0x00310000 // LM4F112H5QC +#define SYSCTL_DID1_PRTNO_LM4F112H5QD \ + 0x00350000 // LM4F112H5QD +#define SYSCTL_DID1_PRTNO_LM4F120B2QR \ + 0x00010000 // LM4F120B2QR +#define SYSCTL_DID1_PRTNO_LM4F120C4QR \ + 0x00020000 // LM4F120C4QR +#define SYSCTL_DID1_PRTNO_LM4F120E5QR \ + 0x00030000 // LM4F120E5QR +#define SYSCTL_DID1_PRTNO_LM4F120H5QR \ + 0x00040000 // LM4F120H5QR +#define SYSCTL_DID1_PRTNO_LM4F121B2QR \ + 0x00080000 // LM4F121B2QR +#define SYSCTL_DID1_PRTNO_LM4F121C4QR \ + 0x00090000 // LM4F121C4QR +#define SYSCTL_DID1_PRTNO_LM4F121E5QR \ + 0x000A0000 // LM4F121E5QR +#define SYSCTL_DID1_PRTNO_LM4F121H5QR \ + 0x000B0000 // LM4F121H5QR +#define SYSCTL_DID1_PRTNO_LM4F122C4QC \ + 0x00D00000 // LM4F122C4QC +#define SYSCTL_DID1_PRTNO_LM4F122E5QC \ + 0x00D10000 // LM4F122E5QC +#define SYSCTL_DID1_PRTNO_LM4F122H5QC \ + 0x00D20000 // LM4F122H5QC +#define SYSCTL_DID1_PRTNO_LM4F122H5QD \ + 0x00D60000 // LM4F122H5QD +#define SYSCTL_DID1_PRTNO_LM4F130C4QR \ + 0x00480000 // LM4F130C4QR +#define SYSCTL_DID1_PRTNO_LM4F130E5QR \ + 0x00400000 // LM4F130E5QR +#define SYSCTL_DID1_PRTNO_LM4F130H5QR \ + 0x00410000 // LM4F130H5QR +#define SYSCTL_DID1_PRTNO_LM4F131C4QR \ + 0x00520000 // LM4F131C4QR +#define SYSCTL_DID1_PRTNO_LM4F131E5QR \ + 0x00500000 // LM4F131E5QR +#define SYSCTL_DID1_PRTNO_LM4F131H5QR \ + 0x00510000 // LM4F131H5QR +#define SYSCTL_DID1_PRTNO_LM4F132C4QC \ + 0x00660000 // LM4F132C4QC +#define SYSCTL_DID1_PRTNO_LM4F132E5QC \ + 0x00600000 // LM4F132E5QC +#define SYSCTL_DID1_PRTNO_LM4F132H5QC \ + 0x00610000 // LM4F132H5QC +#define SYSCTL_DID1_PRTNO_LM4F132H5QD \ + 0x00650000 // LM4F132H5QD +#define SYSCTL_DID1_PRTNO_LM4F210E5QR \ + 0x00700000 // LM4F210E5QR +#define SYSCTL_DID1_PRTNO_LM4F210H5QR \ + 0x00730000 // LM4F210H5QR +#define SYSCTL_DID1_PRTNO_LM4F211E5QR \ + 0x00800000 // LM4F211E5QR +#define SYSCTL_DID1_PRTNO_LM4F211H5QR \ + 0x00830000 // LM4F211H5QR +#define SYSCTL_DID1_PRTNO_LM4F212H5BB \ + 0x00E90000 // LM4F212H5BB +#define SYSCTL_DID1_PRTNO_LM4F212H5QC \ + 0x00C40000 // LM4F212H5QC +#define SYSCTL_DID1_PRTNO_LM4F212H5QD \ + 0x00C60000 // LM4F212H5QD +#define SYSCTL_DID1_PRTNO_LM4F230E5QR \ + 0x00A00000 // LM4F230E5QR +#define SYSCTL_DID1_PRTNO_LM4F230H5QR \ + 0x00A10000 // LM4F230H5QR +#define SYSCTL_DID1_PRTNO_LM4F231E5QR \ + 0x00B00000 // LM4F231E5QR +#define SYSCTL_DID1_PRTNO_LM4F231H5QR \ + 0x00B10000 // LM4F231H5QR +#define SYSCTL_DID1_PRTNO_LM4F232E5QC \ + 0x00C00000 // LM4F232E5QC +#define SYSCTL_DID1_PRTNO_LM4F232H5BB \ + 0x00E30000 // LM4F232H5BB +#define SYSCTL_DID1_PRTNO_LM4F232H5QC \ + 0x00C10000 // LM4F232H5QC +#define SYSCTL_DID1_PRTNO_LM4F232H5QD \ + 0x00C50000 // LM4F232H5QD +#define SYSCTL_DID1_PRTNO_LM4FS1AH5BB \ + 0x00E50000 // LM4FS1AH5BB +#define SYSCTL_DID1_PRTNO_LM4FS1GH5BB \ + 0x00EA0000 // LM4FS1GH5BB +#define SYSCTL_DID1_PRTNO_LM4FS99H5BB \ + 0x00E40000 // LM4FS99H5BB +#define SYSCTL_DID1_PRTNO_LM4FSXAH5BB \ + 0x00E00000 // LM4FSXAH5BB +#define SYSCTL_DID1_PRTNO_LM4FSXLH5BB \ + 0x00E10000 // LM4FSXLH5BB +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count +#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package +#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C + // to 70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range + // (-40C to 85C) +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C + // to 105C) +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type +#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package +#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_PKG_QFN 0x00000018 // QFN package +#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified +#define SYSCTL_DID1_PRTNO_S 16 // Part number shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_48KB 0x00BF0000 // 48 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash +#define SYSCTL_DC0_FLASHSZ_384K 0x000000BF // 384 KB of Flash +#define SYSCTL_DC0_FLASHSZ_512K 0x000000FF // 512 KB of Flash +#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift +#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present +#define SYSCTL_DC1_CAN2 0x04000000 // CAN Module 2 Present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider +#define SYSCTL_DC1_MINSYSDIV_100 \ + 0x00001000 // Divide VCO (400MHZ) by 5 minimum +#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 = + // 6 minimum +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8 +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10 +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // MPU Present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present +#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present +#define SYSCTL_DC1_PLL 0x00000010 // PLL Present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present +#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present +#define SYSCTL_DC1_SWD 0x00000002 // SWD Present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present +#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present +#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed +#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed +#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present +#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present +#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present +#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present +#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present +#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present +#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable +#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate +#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present +#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present +#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present +#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_SW 0x40000000 // Software transfer on uDMA Ch30 +#define SYSCTL_DC7_DMACH30 0x40000000 // SW +#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX +#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX +#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3 +#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2 +#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1 +#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25 +#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24 +#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0 +#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23 +#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX +#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX +#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22 +#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO +#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO +#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B +#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A +#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3 +#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2 +#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B +#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A +#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX +#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX +#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11 +#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX +#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10 +#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX +#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9 +#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX +#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX +#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8 +#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B +#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A +#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B +#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5 +#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4 +#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A +#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3 +#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B +#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2 +#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A +#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1 +#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX +#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX +#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR Wait and Check for Noise +#define SYSCTL_PBORCTL_BORTIM_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50 +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45 +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40 +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35 +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30 +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25 +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75 +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70 +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65 +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60 +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control +#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control +#define SYSCTL_SRCR1_I2S0 0x10000000 // I2S0 Reset Control +#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control +#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control +#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control +#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control +#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control +#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status +#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt + // Status +#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw + // Interrupt Status +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw + // Interrupt Status +#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw + // Interrupt Status +#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt + // Status +#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask +#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask +#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault + // Interrupt Mask +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt + // Mask +#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt + // Mask +#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask +#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status +#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt + // Status +#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked + // Interrupt Status +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked + // Interrupt Status +#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked + // Interrupt Status +#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset +#define SYSCTL_RESC_LDO 0x00000020 // LDO Reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset +#define SYSCTL_RESC_SW 0x00000010 // Software Reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset +#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset +#define SYSCTL_RESC_EXT 0x00000001 // External Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down +#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value +#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1 MHz +#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432 MHz +#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2 MHz +#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576 MHz +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz +#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL Verification +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz +#define SYSCTL_RCC_IOSCVER 0x00000008 // Internal Oscillator Verification + // Timer +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main Oscillator Verification + // Timer +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable +#define SYSCTL_RCC_SYSDIV_S 23 +#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_M 0x0000C000 // PLL OD Value +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Divide by 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Divide by 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Divide by 4 +#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value +#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value +#define SYSCTL_PLLCFG_F_S 5 +#define SYSCTL_PLLCFG_R_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance + // Bus + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 + // MHz +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 +#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 +#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 +#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 +#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 +#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 +#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 +#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 +#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 +#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 +#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 +#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 +#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 +#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 +#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 +#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 +#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 +#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 +#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 +#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 +#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 +#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 +#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 +#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 +#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 +#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 +#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 +#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 +#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 +#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 +#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 +#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 +#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 +#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 +#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 +#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 +#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 +#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 +#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 +#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 +#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 +#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 +#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 +#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 +#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 +#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 +#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 +#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 +#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 +#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 +#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 +#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 +#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 +#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 +#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 +#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 +#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 +#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 +#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 +#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 +#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 +#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 +#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 +#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 +#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL +#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz +#define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // 4.194304 MHz +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz +#define SYSCTL_RCC2_SYSDIV2_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed +#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_RCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_RCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_RCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating +#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating +#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control +#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed +#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_SCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_SCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_SCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_SCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_SCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_SCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating +#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S0 Clock Gating +#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control +#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating +#define SYSCTL_DCGC1_I2S0 0x10000000 // I2S0 Clock Gating +#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control +#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override +#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1 +#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 +#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 +#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 +#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 +#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 +#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 +#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 +#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 +#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 +#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 +#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 +#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 +#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 +#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 +#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 +#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 +#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 +#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 +#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 +#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 +#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 +#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 +#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 +#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 +#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 +#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 +#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 +#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 +#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 +#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 +#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 +#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 +#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 +#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 +#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 +#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 +#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 +#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 +#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 +#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 +#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 +#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 +#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 +#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 +#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 +#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 +#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 +#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 +#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 +#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 +#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 +#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 +#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 +#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 +#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 +#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 +#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 +#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 +#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 +#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 +#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 +#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 +#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz +#define SYSCTL_DSLPCLKCFG_PIOSCPD \ + 0x00000002 // PIOSC Power Down Request +#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable +#define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000 // RX Clock Integer Input +#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input +#define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable +#define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0 // TX Clock Integer Input +#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input +#define SYSCTL_I2SMCLKCFG_RXI_S 20 +#define SYSCTL_I2SMCLKCFG_RXF_S 16 +#define SYSCTL_I2SMCLKCFG_TXI_S 4 +#define SYSCTL_I2SMCLKCFG_TXF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer + // Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPLPC register. +// +//***************************************************************************** +#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPECI register. +// +//***************************************************************************** +#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPFAN register. +// +//***************************************************************************** +#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset +#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset +#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset +#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset +#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset +#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset +#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset +#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset +#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset +#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset +#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset +#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRLPC register. +// +//***************************************************************************** +#define SYSCTL_SRLPC_R0 0x00000001 // LPC Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPECI register. +// +//***************************************************************************** +#define SYSCTL_SRPECI_R0 0x00000001 // PECI Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRFAN register. +// +//***************************************************************************** +#define SYSCTL_SRFAN_R0 0x00000001 // FAN Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCLPC register. +// +//***************************************************************************** +#define SYSCTL_RCGCLPC_R0 0x00000001 // LPC Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPECI +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCPECI_R0 0x00000001 // PECI Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCFAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCFAN_R0 0x00000001 // FAN Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCLPC register. +// +//***************************************************************************** +#define SYSCTL_SCGCLPC_S0 0x00000001 // LPC Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPECI +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCPECI_S0 0x00000001 // PECI Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCFAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCFAN_S0 0x00000001 // FAN Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCLPC register. +// +//***************************************************************************** +#define SYSCTL_DCGCLPC_D0 0x00000001 // LPC Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPECI +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCPECI_D0 0x00000001 // PECI Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCFAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCFAN_D0 0x00000001 // FAN Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWD register. +// +//***************************************************************************** +#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control +#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCTIMER register. +// +//***************************************************************************** +#define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control +#define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control +#define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control +#define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control +#define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control +#define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCGPIO register. +// +//***************************************************************************** +#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control +#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control +#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control +#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control +#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control +#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control +#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control +#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control +#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control +#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control +#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control +#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control +#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control +#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control +#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCDMA register. +// +//***************************************************************************** +#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCHIB register. +// +//***************************************************************************** +#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUART register. +// +//***************************************************************************** +#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control +#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control +#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control +#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control +#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control +#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control +#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control +#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCSSI register. +// +//***************************************************************************** +#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control +#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control +#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control +#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCI2C register. +// +//***************************************************************************** +#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control +#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control +#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control +#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control +#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control +#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUSB register. +// +//***************************************************************************** +#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCCAN register. +// +//***************************************************************************** +#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control +#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCADC register. +// +//***************************************************************************** +#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control +#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCACMP register. +// +//***************************************************************************** +#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCPWM register. +// +//***************************************************************************** +#define SYSCTL_PCPWM_P1 0x00000002 // PWM Module 1 Power Control +#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCQEI register. +// +//***************************************************************************** +#define SYSCTL_PCQEI_P1 0x00000002 // QEI Module 1 Power Control +#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCLPC register. +// +//***************************************************************************** +#define SYSCTL_PCLPC_P0 0x00000001 // LPC Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCPECI register. +// +//***************************************************************************** +#define SYSCTL_PCPECI_P0 0x00000001 // PECI Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCFAN register. +// +//***************************************************************************** +#define SYSCTL_PCFAN_P0 0x00000001 // FAN Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control +#define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control +#define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control +#define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control +#define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control +#define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready +#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready +#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready +#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready +#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready +#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready +#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready +#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready +#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready +#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready +#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready +#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRLPC register. +// +//***************************************************************************** +#define SYSCTL_PRLPC_R0 0x00000001 // LPC Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPECI register. +// +//***************************************************************************** +#define SYSCTL_PRPECI_R0 0x00000001 // PECI Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRFAN register. +// +//***************************************************************************** +#define SYSCTL_PRFAN_R0 0x00000001 // FAN Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the System Control register +// addresses. +// +//***************************************************************************** +#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High-Speed Control +#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0 +#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID0 +// register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID1 +// register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // QFP package +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC0 +// register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC1 +// register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present +#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC2 +// register. +// +//***************************************************************************** +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC3 +// register. +// +//***************************************************************************** +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 Pin Present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 Pin Present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 Pin Present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 Pin Present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present +#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0 +// register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RESC +// register. +// +//***************************************************************************** +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCC +// register. +// +//***************************************************************************** +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG +// register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_GPIOHSCTL register. +// +//***************************************************************************** +#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed +#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed +#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed +#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed +#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed +#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed +#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed +#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCC2 +// register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USEFRACT 0x40000000 // Use fractional divider +#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider +#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide +#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0 +// register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0 +// register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0 +// register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_DSLPCLKCFG register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override +#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0, +// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module +#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module +#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1, +// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 +#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 +#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 +#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2, +// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_ETH 0x50000000 // ETH module +#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module +#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module +#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RIS, +// SYSCTL_IMC, and SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +#endif + +#endif // __HW_SYSCTL_H__ diff --git a/cpu/stellaris_common/include/hw_sysexc.h b/cpu/stellaris_common/include/hw_sysexc.h new file mode 100644 index 0000000000..6b8283490e --- /dev/null +++ b/cpu/stellaris_common/include/hw_sysexc.h @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// hw_sysexc.h - Macros used when accessing the system exception module. +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSEXC_H__ +#define __HW_SYSEXC_H__ + +//***************************************************************************** +// +// The following are defines for the System Exception Module register +// addresses. +// +//***************************************************************************** +#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt + // Status +#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask +#define SYSEXC_MIS 0x400F9008 // System Exception Masked + // Interrupt Status +#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception + // Raw Interrupt Status +#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation + // Raw Interrupt Status +#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal + // Exception Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception + // Interrupt Mask +#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation + // Interrupt Mask +#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Mask +#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception + // Masked Interrupt Status +#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation + // Masked Interrupt Status +#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception + // Interrupt Clear +#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation + // Interrupt Clear +#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Clear +#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Clear + +#endif // __HW_SYSEXC_H__ diff --git a/cpu/stellaris_common/include/hw_timer.h b/cpu/stellaris_common/include/hw_timer.h new file mode 100644 index 0000000000..44353cefb0 --- /dev/null +++ b/cpu/stellaris_common/include/hw_timer.h @@ -0,0 +1,759 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the Timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // GPTM Configuration +#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode +#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode +#define TIMER_O_CTL 0x0000000C // GPTM Control +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize +#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask +#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status +#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status +#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear +#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load +#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load +#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match +#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match +#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale +#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale +#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match +#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match +#define TIMER_O_TAR 0x00000048 // GPTM Timer A +#define TIMER_O_TBR 0x0000004C // GPTM Timer B +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) + // counter configuration +#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The + // function is controlled by bits + // 1:0 of GPTMTAMR and GPTMTBMR + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer + // 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer + // 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer + // 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer + // 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer + // 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer + // 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM 16/32-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM 16/32-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM 16/32-Bit + // Timer 0 is triggered + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error + // Interrupt Mask +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt + // Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt + // Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw + // Interrupt +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked + // Interrupt +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Clear +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt + // Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt + // Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load + // Register High +#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load + // Register Low +#define TIMER_TAILR_TAILRH_S 16 +#define TIMER_TAILR_TAILRL_S 0 +#define TIMER_TAILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_TBILRL_S 0 +#define TIMER_TBILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High +#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low +#define TIMER_TAMATCHR_TAMRH_S 16 +#define TIMER_TAMATCHR_TAMRL_S 0 +#define TIMER_TAMATCHR_TAMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low +#define TIMER_TBMATCHR_TBMR_S 0 +#define TIMER_TBMATCHR_TBMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High +#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAR_TARH_S 16 +#define TIMER_TAR_TARL_S 0 +#define TIMER_TAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B +#define TIMER_TBR_TBRL_S 0 +#define TIMER_TBR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High +#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAV_TAVH_S 16 +#define TIMER_TAV_TAVL_S 0 +#define TIMER_TAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register +#define TIMER_TBV_TBVL_S 0 +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CFG +// register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CTL +// register. +// +//***************************************************************************** +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_RIS +// register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAILR +// register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBILR +// register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAR +// register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBR +// register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the timer +// registers. +// +//***************************************************************************** +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnMR +// register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPR +// register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPMR +// register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +#endif + +#endif // __HW_TIMER_H__ diff --git a/cpu/stellaris_common/include/hw_types.h b/cpu/stellaris_common/include/hw_types.h new file mode 100644 index 0000000000..6fcb5abdba --- /dev/null +++ b/cpu/stellaris_common/include/hw_types.h @@ -0,0 +1,218 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Stellaris silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(CLASS_IS_SANDSTORM) +// { +// do some Sandstorm-class specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Stellaris family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Stellaris silicon. Many compilers will +// then detect the "hard-coded" conditionals, and appropriately optimize the +// code blocks, eliminating any "unreachable" code. This would result in +// a smaller Driverlib, thus producing a smaller final application size, but +// at the cost of limiting the Driverlib binary to a specific Stellaris +// silicon revision. +// +//***************************************************************************** +#ifndef CLASS_IS_SANDSTORM +#define CLASS_IS_SANDSTORM \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM))) +#endif + +#ifndef CLASS_IS_FURY +#define CLASS_IS_FURY \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY)) +#endif + +#ifndef CLASS_IS_DUSTDEVIL +#define CLASS_IS_DUSTDEVIL \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL)) +#endif + +#ifndef CLASS_IS_TEMPEST +#define CLASS_IS_TEMPEST \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST)) +#endif + +#ifndef CLASS_IS_FIRESTORM +#define CLASS_IS_FIRESTORM \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM)) +#endif + +#ifndef CLASS_IS_BLIZZARD +#define CLASS_IS_BLIZZARD \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD)) +#endif + +#ifndef REVISION_IS_A0 +#define REVISION_IS_A0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A1 +#define REVISION_IS_A1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A2 +#define REVISION_IS_A2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_B0 +#define REVISION_IS_B0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_B1 +#define REVISION_IS_B1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C0 +#define REVISION_IS_C0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_C1 +#define REVISION_IS_C1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C2 +#define REVISION_IS_C2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_C3 +#define REVISION_IS_C3 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3)) +#endif + +#ifndef REVISION_IS_C5 +#define REVISION_IS_C5 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5)) +#endif + +//***************************************************************************** +// +// Deprecated silicon class and revision detection macros. +// +//***************************************************************************** +#ifndef DEPRECATED +#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM +#define DEVICE_IS_FURY CLASS_IS_FURY +#define DEVICE_IS_REVA2 REVISION_IS_A2 +#define DEVICE_IS_REVC1 REVISION_IS_C1 +#define DEVICE_IS_REVC2 REVISION_IS_C2 +#endif + +#endif // __HW_TYPES_H__ diff --git a/cpu/stellaris_common/include/hw_uart.h b/cpu/stellaris_common/include/hw_uart.h new file mode 100644 index 0000000000..27c8f6faf8 --- /dev/null +++ b/cpu/stellaris_common/include/hw_uart.h @@ -0,0 +1,522 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // UART Data +#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear +#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear +#define UART_O_FR 0x00000018 // UART Flag +#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register +#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate + // Divisor +#define UART_O_LCRH 0x0000002C // UART Line Control +#define UART_O_CTL 0x00000030 // UART Control +#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select +#define UART_O_IM 0x00000038 // UART Interrupt Mask +#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status +#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status +#define UART_O_ICR 0x00000044 // UART Interrupt Clear +#define UART_O_DMACTL 0x00000048 // UART DMA Control +#define UART_O_LCTL 0x00000090 // UART LIN Control +#define UART_O_LSS 0x00000094 // UART LIN Snap Shot +#define UART_O_LTIM 0x00000098 // UART LIN Timer +#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address +#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask +#define UART_O_PP 0x00000FC0 // UART Peripheral Properties +#define UART_O_CC 0x00000FC8 // UART Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_LIN 0x00000040 // LIN Mode Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full +#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full +#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) +#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full +#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full +#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full +#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) +#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full +#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask +#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask +#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt + // Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt + // Status +#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt + // Status +#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw + // Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt + // Status +#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt + // Status +#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked + // Interrupt Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCTL register. +// +//***************************************************************************** +#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length +#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits + // (default) +#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits +#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits +#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits +#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LSS register. +// +//***************************************************************************** +#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot +#define UART_LSS_TSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LTIM register. +// +//***************************************************************************** +#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value +#define UART_LTIM_TIMER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default) +#define UART_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_PeriphID4 0x00000FD0 +#define UART_O_PeriphID5 0x00000FD4 +#define UART_O_PeriphID6 0x00000FD8 +#define UART_O_PeriphID7 0x00000FDC +#define UART_O_PeriphID0 0x00000FE0 +#define UART_O_PeriphID1 0x00000FE4 +#define UART_O_PeriphID2 0x00000FE8 +#define UART_O_PeriphID3 0x00000FEC +#define UART_O_PCellID0 0x00000FF0 +#define UART_O_PCellID1 0x00000FF4 +#define UART_O_PCellID2 0x00000FF8 +#define UART_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UART_O_DR +// register. +// +//***************************************************************************** +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UART_O_IBRD +// register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UART_O_FBRD +// register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UART_O_LCR_H +// register. +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UART_O_IFLS +// register. +// +//***************************************************************************** +#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask +#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the UART_O_ICR +// register. +// +//***************************************************************************** +#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear +#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// The following are deprecated defines for the Reset Values for UART +// Registers. +// +//***************************************************************************** +#define UART_RV_CTL 0x00000300 +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID3 0x000000B1 +#define UART_RV_FR 0x00000090 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_IM 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_IBRD 0x00000000 + +#endif + +#endif // __HW_UART_H__ diff --git a/cpu/stellaris_common/include/hw_watchdog.h b/cpu/stellaris_common/include/hw_watchdog.h new file mode 100644 index 0000000000..7491371419 --- /dev/null +++ b/cpu/stellaris_common/include/hw_watchdog.h @@ -0,0 +1,191 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following are defines for the Watchdog Timer register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Watchdog Load +#define WDT_O_VALUE 0x00000004 // Watchdog Value +#define WDT_O_CTL 0x00000008 // Watchdog Control +#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear +#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status +#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status +#define WDT_O_TEST 0x00000418 // Watchdog Test +#define WDT_O_LOCK 0x00000C00 // Watchdog Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the Watchdog Timer register +// offsets. +// +//***************************************************************************** +#define WDT_O_PeriphID4 0x00000FD0 +#define WDT_O_PeriphID5 0x00000FD4 +#define WDT_O_PeriphID6 0x00000FD8 +#define WDT_O_PeriphID7 0x00000FDC +#define WDT_O_PeriphID0 0x00000FE0 +#define WDT_O_PeriphID1 0x00000FE4 +#define WDT_O_PeriphID2 0x00000FE8 +#define WDT_O_PeriphID3 0x00000FEC +#define WDT_O_PCellID0 0x00000FF0 +#define WDT_O_PCellID1 0x00000FF4 +#define WDT_O_PCellID2 0x00000FF8 +#define WDT_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the WDT_O_TEST +// register. +// +//***************************************************************************** +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable + +//***************************************************************************** +// +// The following are deprecated defines for the reset values for the WDT +// registers. +// +//***************************************************************************** +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_PCellID1 0x000000F0 +#define WDT_RV_PCellID3 0x000000B1 +#define WDT_RV_PeriphID1 0x00000018 +#define WDT_RV_PeriphID2 0x00000018 +#define WDT_RV_PCellID0 0x0000000D +#define WDT_RV_PCellID2 0x00000005 +#define WDT_RV_PeriphID0 0x00000005 +#define WDT_RV_PeriphID3 0x00000001 +#define WDT_RV_PeriphID5 0x00000000 +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_PeriphID4 0x00000000 +#define WDT_RV_PeriphID6 0x00000000 +#define WDT_RV_PeriphID7 0x00000000 +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register + +#endif + +#endif // __HW_WATCHDOG_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/adc.h b/cpu/stellaris_common/include/stellaris_periph/adc.h new file mode 100644 index 0000000000..1949d0e35d --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/adc.h @@ -0,0 +1,311 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 +#define ADC_CTL_CH8 0x00000008 // Input channel 8 +#define ADC_CTL_CH9 0x00000009 // Input channel 9 +#define ADC_CTL_CH10 0x0000000A // Input channel 10 +#define ADC_CTL_CH11 0x0000000B // Input channel 11 +#define ADC_CTL_CH12 0x0000000C // Input channel 12 +#define ADC_CTL_CH13 0x0000000D // Input channel 13 +#define ADC_CTL_CH14 0x0000000E // Input channel 14 +#define ADC_CTL_CH15 0x0000000F // Input channel 15 +#define ADC_CTL_CH16 0x00000100 // Input channel 16 +#define ADC_CTL_CH17 0x00000101 // Input channel 17 +#define ADC_CTL_CH18 0x00000102 // Input channel 18 +#define ADC_CTL_CH19 0x00000103 // Input channel 19 +#define ADC_CTL_CH20 0x00000104 // Input channel 20 +#define ADC_CTL_CH21 0x00000105 // Input channel 21 +#define ADC_CTL_CH22 0x00000106 // Input channel 22 +#define ADC_CTL_CH23 0x00000107 // Input channel 23 +#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 +#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 +#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 +#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3 +#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4 +#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5 +#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6 +#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7 + +//***************************************************************************** +// +// Values that can be passed to ADCComparatorConfigure as part of the +// ulConfig parameter. +// +//***************************************************************************** +#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled +#define ADC_COMP_TRIG_LOW_ALWAYS \ + 0x00001000 // Trigger Low Always +#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once +#define ADC_COMP_TRIG_LOW_HALWAYS \ + 0x00001200 // Trigger Low Always (Hysteresis) +#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis) +#define ADC_COMP_TRIG_MID_ALWAYS \ + 0x00001400 // Trigger Mid Always +#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once +#define ADC_COMP_TRIG_HIGH_ALWAYS \ + 0x00001C00 // Trigger High Always +#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once +#define ADC_COMP_TRIG_HIGH_HALWAYS \ + 0x00001E00 // Trigger High Always (Hysteresis) +#define ADC_COMP_TRIG_HIGH_HONCE \ + 0x00001F00 // Trigger High Once (Hysteresis) + +#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled +#define ADC_COMP_INT_LOW_ALWAYS \ + 0x00000010 // Interrupt Low Always +#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once +#define ADC_COMP_INT_LOW_HALWAYS \ + 0x00000012 // Interrupt Low Always + // (Hysteresis) +#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis) +#define ADC_COMP_INT_MID_ALWAYS \ + 0x00000014 // Interrupt Mid Always +#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once +#define ADC_COMP_INT_HIGH_ALWAYS \ + 0x0000001C // Interrupt High Always +#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once +#define ADC_COMP_INT_HIGH_HALWAYS \ + 0x0000001E // Interrupt High Always + // (Hysteresis) +#define ADC_COMP_INT_HIGH_HONCE \ + 0x0000001F // Interrupt High Once (Hysteresis) + +//***************************************************************************** +// +// Values that can be used to modify the sequence number passed to +// ADCProcessorTrigger in order to get cross-module synchronous processor +// triggers. +// +//***************************************************************************** +#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger +#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger + +//***************************************************************************** +// +// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and +// returned from ADCPhaseDelayGet. +// +//***************************************************************************** +#define ADC_PHASE_0 0x00000000 // 0 degrees +#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees +#define ADC_PHASE_45 0x00000002 // 45 degrees +#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees +#define ADC_PHASE_90 0x00000004 // 90 degrees +#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees +#define ADC_PHASE_135 0x00000006 // 135 degrees +#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees +#define ADC_PHASE_180 0x00000008 // 180 degrees +#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees +#define ADC_PHASE_225 0x0000000A // 225 degrees +#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees +#define ADC_PHASE_270 0x0000000C // 270 degrees +#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees +#define ADC_PHASE_315 0x0000000E // 315 degrees +#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees + +//***************************************************************************** +// +// Values that can be passed to ADCReferenceSet as the ulRef parameter. +// +//***************************************************************************** +#define ADC_REF_INT 0x00000000 // Internal reference +#define ADC_REF_EXT_3V 0x00000001 // External 3V reference +#define ADC_REF_EXT_1V 0x00000003 // External 1V reference + +//***************************************************************************** +// +// Values that can be passed to ADCResolutionSet as the ulResolution parameter. +// +//***************************************************************************** +#define ADC_RES_10BIT_S 0x00000000 // 10-bit resolution +#define ADC_RES_12BIT_S 0x00000010 // 12-bit resolution + +//***************************************************************************** +// +// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), +// ADCIntClearEx() and ADCIntStatusEx(). +// +//***************************************************************************** +#define ADC_INT_SS0 0x00000001 +#define ADC_INT_SS1 0x00000002 +#define ADC_INT_SS2 0x00000004 +#define ADC_INT_SS3 0x00000008 +#define ADC_INT_DMA_SS0 0x00000100 +#define ADC_INT_DMA_SS1 0x00000200 +#define ADC_INT_DMA_SS2 0x00000400 +#define ADC_INT_DMA_SS3 0x00000800 +#define ADC_INT_DCON_SS0 0x00010000 +#define ADC_INT_DCON_SS1 0x00020000 +#define ADC_INT_DCON_SS2 0x00040000 +#define ADC_INT_DCON_SS3 0x00080000 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceOverflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceUnderflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); +extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp, + unsigned long ulLowRef, + unsigned long ulHighRef); +extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp, + tBoolean bTrigger, tBoolean bInterrupt); +extern void ADCComparatorIntDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCComparatorIntEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern unsigned long ADCComparatorIntStatus(unsigned long ulBase); +extern void ADCComparatorIntClear(unsigned long ulBase, + unsigned long ulStatus); +extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef); +extern unsigned long ADCReferenceGet(unsigned long ulBase); +extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution); +extern unsigned long ADCResolutionGet(unsigned long ulBase); +extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase); +extern unsigned long ADCPhaseDelayGet(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/comp.h b/cpu/stellaris_common/include/stellaris_periph/comp.h new file mode 100644 index 0000000000..3705f90516 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/comp.h @@ -0,0 +1,145 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and combined together with values from the other +// groups via a logical OR. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#ifndef DEPRECATED +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#endif +#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/cpu.h b/cpu/stellaris_common/include/stellaris_periph/cpu.h new file mode 100644 index 0000000000..5e4ad5455b --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/cpu.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern unsigned long CPUcpsid(void); +extern unsigned long CPUcpsie(void); +extern unsigned long CPUprimask(void); +extern void CPUwfi(void); +extern unsigned long CPUbasepriGet(void); +extern void CPUbasepriSet(unsigned long ulNewBasepri); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/debug.h b/cpu/stellaris_common/include/stellaris_periph/debug.h new file mode 100644 index 0000000000..fb8f0c6a7c --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/debug.h @@ -0,0 +1,68 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/fpu.h b/cpu/stellaris_common/include/stellaris_periph/fpu.h new file mode 100644 index 0000000000..e374b55c25 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/fpu.h @@ -0,0 +1,112 @@ +//***************************************************************************** +// +// fpu.h - Prototypes for the floatint point manipulation routines. +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FPU_H__ +#define __FPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_HALF_IEEE 0x00000000 +#define FPU_HALF_ALTERNATE 0x04000000 + +//***************************************************************************** +// +// Values that can be passed to FPUNaNModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_NAN_PROPAGATE 0x00000000 +#define FPU_NAN_DEFAULT 0x02000000 + +//***************************************************************************** +// +// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_FLUSH_TO_ZERO_DIS 0x00000000 +#define FPU_FLUSH_TO_ZERO_EN 0x01000000 + +//***************************************************************************** +// +// Values that can be passed to FPURoundingModeSet as the ulMode parameter. +// +//***************************************************************************** +#define FPU_ROUND_NEAREST 0x00000000 +#define FPU_ROUND_POS_INF 0x00400000 +#define FPU_ROUND_NEG_INF 0x00800000 +#define FPU_ROUND_ZERO 0x00c00000 + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void FPUEnable(void); +extern void FPUDisable(void); +extern void FPUStackingEnable(void); +extern void FPULazyStackingEnable(void); +extern void FPUStackingDisable(void); +extern void FPUHalfPrecisionModeSet(unsigned long ulMode); +extern void FPUNaNModeSet(unsigned long ulMode); +extern void FPUFlushToZeroModeSet(unsigned long ulMode); +extern void FPURoundingModeSet(unsigned long ulMode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FPU_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/gpio.h b/cpu/stellaris_common/include/stellaris_periph/gpio.h new file mode 100644 index 0000000000..7747d51505 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/gpio.h @@ -0,0 +1,199 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level +#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfnIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinConfigure(unsigned long ulPinConfig); +extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort, + unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins); +extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins); + +//**************************************************************************** +// +// The definitions for GPIOPinConfigure previously resided in this file but +// have been moved to pin_map.h and made part-specific (in other words, only +// those definitions that are valid based on the selected part, as defined by +// PART_, will be made available). For backwards compatibility, +// pin_map.h is included here so that the expected definitions will still be +// available (though part-specific now, so some that were previously available +// but inappropriate for the given part will not be available). +// +//***************************************************************************** +#ifndef DEPRECATED +#include "pin_map.h" +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/hibernate.h b/cpu/stellaris_common/include/stellaris_periph/hibernate.h new file mode 100644 index 0000000000..bf3d181b9e --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/hibernate.h @@ -0,0 +1,167 @@ +//***************************************************************************** +// +// hibernate.h - API definition for the Hibernation module. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HIBERNATE_H__ +#define __HIBERNATE_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros needed for selecting the clock source for HibernateClockSelect() +// +//***************************************************************************** +#define HIBERNATE_CLOCK_SEL_RAW 0x00000004 +#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000 + +//***************************************************************************** +// +// Macros need to configure wake events for HibernateWakeSet() +// +//***************************************************************************** +#define HIBERNATE_WAKE_PIN 0x00000010 +#define HIBERNATE_WAKE_RTC 0x00000008 +#define HIBERNATE_WAKE_LOW_BAT 0x00000200 + +//***************************************************************************** +// +// Macros needed to configure low battery detect for HibernateLowBatSet() +// +//***************************************************************************** +#define HIBERNATE_LOW_BAT_DETECT 0x00000020 +#define HIBERNATE_LOW_BAT_ABORT 0x000000A0 +#define HIBERNATE_LOW_BAT_1_9V 0x00000000 +#define HIBERNATE_LOW_BAT_2_1V 0x00002000 +#define HIBERNATE_LOW_BAT_2_3V 0x00004000 +#define HIBERNATE_LOW_BAT_2_5V 0x00006000 + +//***************************************************************************** +// +// Macros defining interrupt source bits for the interrupt functions. +// +//***************************************************************************** +#define HIBERNATE_INT_WR_COMPLETE 0x00000010 +#define HIBERNATE_INT_PIN_WAKE 0x00000008 +#define HIBERNATE_INT_LOW_BAT 0x00000004 +#define HIBERNATE_INT_RTC_MATCH_0 0x00000001 +#define HIBERNATE_INT_RTC_MATCH_1 0x00000002 + +//***************************************************************************** +// +// Macros defining oscillator configuration options for the +// HibernateClockConfig() function. +// +//***************************************************************************** +#define HIBERNATE_OSC_LOWDRIVE 0x00040000 +#define HIBERNATE_OSC_HIGHDRIVE 0x00060000 +#define HIBERNATE_OSC_DISABLE 0x00010000 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HibernateGPIORetentionEnable(void); +extern void HibernateGPIORetentionDisable(void); +extern tBoolean HibernateGPIORetentionGet(void); +extern void HibernateEnableExpClk(unsigned long ulHibClk); +extern void HibernateDisable(void); +extern void HibernateClockSelect(unsigned long ulClockInput); +extern void HibernateRTCEnable(void); +extern void HibernateRTCDisable(void); +extern void HibernateWakeSet(unsigned long ulWakeFlags); +extern unsigned long HibernateWakeGet(void); +extern void HibernateLowBatSet(unsigned long ulLowBatFlags); +extern unsigned long HibernateLowBatGet(void); +extern void HibernateRTCSet(unsigned long ulRTCValue); +extern unsigned long HibernateRTCGet(void); +extern void HibernateRTCMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch0Get(void); +extern void HibernateRTCMatch1Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch1Get(void); +extern void HibernateRTCTrimSet(unsigned long ulTrim); +extern unsigned long HibernateRTCTrimGet(void); +extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateRequest(void); +extern void HibernateIntEnable(unsigned long ulIntFlags); +extern void HibernateIntDisable(unsigned long ulIntFlags); +extern void HibernateIntRegister(void (*pfnHandler)(void)); +extern void HibernateIntUnregister(void); +extern unsigned long HibernateIntStatus(tBoolean bMasked); +extern void HibernateIntClear(unsigned long ulIntFlags); +extern unsigned long HibernateIsActive(void); +extern void HibernateRTCSSMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCSSMatch0Get(void); +extern unsigned long HibernateRTCSSGet(void); +extern void HibernateClockConfig(unsigned long ulConfig); +extern void HibernateBatCheckStart(void); +extern unsigned long HibernateBatCheckDone(void); + +//***************************************************************************** +// +// Several Hibernate module APIs have been renamed, with the original function +// name being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define HibernateEnable(a) \ + HibernateEnableExpClk(a, SysCtlClockGet()) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HIBERNATE_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/i2c.h b/cpu/stellaris_common/include/stellaris_periph/i2c.h new file mode 100644 index 0000000000..f9f7326115 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/i2c.h @@ -0,0 +1,224 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 +#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ + 0x00000011 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 +#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt. +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterIntEnableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CMasterIntDisableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase, + tBoolean bMasked); +extern void I2CMasterIntClearEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue); +extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable); +extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK); +extern unsigned long I2CMasterLineStateGet(unsigned long ulBase); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum, + unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags); +extern void I2CSlaveIntDisableEx(unsigned long ulBase, + unsigned long ulIntFlags); +extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase, + tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +//***************************************************************************** +// +// Several I2C APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "driverlib/sysctl.h" +#define I2CMasterInit(a, b) \ + I2CMasterInitExpClk(a, SysCtlClockGet(), b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/interrupt.h b/cpu/stellaris_common/include/stellaris_periph/interrupt.h new file mode 100644 index 0000000000..04a217c046 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/interrupt.h @@ -0,0 +1,93 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** +#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean IntMasterEnable(void); +extern tBoolean IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); +extern unsigned long IntIsEnabled(unsigned long ulInterrupt); +extern void IntPendSet(unsigned long ulInterrupt); +extern void IntPendClear(unsigned long ulInterrupt); +extern void IntPriorityMaskSet(unsigned long ulPriorityMask); +extern unsigned long IntPriorityMaskGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/pin_map.h b/cpu/stellaris_common/include/stellaris_periph/pin_map.h new file mode 100644 index 0000000000..a657bb3e54 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/pin_map.h @@ -0,0 +1,449 @@ +//***************************************************************************** +// +// pin_map.h - Mapping of peripherals to pins for all parts. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PIN_MAP_H__ +#define __PIN_MAP_H__ + +//***************************************************************************** +// +// LM4F120H5QR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_LM4F120H5QR + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_CAN0RX 0x00011008 +#define GPIO_PB4_T1CCP0 0x00011007 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_CAN0TX 0x00011408 +#define GPIO_PB5_T1CCP1 0x00011407 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_LM4F120H5QR + +//***************************************************************************** +// +// Pin Mapping Functions +// +// This section describes the code that is responsible for handling the +// mapping of peripheral functions to their physical location on the pins of +// a device. +// +//***************************************************************************** + +//***************************************************************************** +// +// Definitions to support mapping GPIO Ports and Pins to their function. +// +//***************************************************************************** + +//***************************************************************************** +// +// Configures the specified ADC pin to function as an ADC pin. +// +// \param ulName is one of the valid names for the ADC pins. +// +// This function takes on of the valid names for an ADC pin and configures +// the pin for its ADC functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b ADC0, \b ADC1, \b ADC2, +// \b ADC3, \b ADC4, \b ADC5, \b ADC6, or \b ADC7. +// +// \sa GPIOPinTypeADC() in order to configure multiple ADC pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeADC(ulName) GPIOPinTypeADC(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified CAN pin to function as a CAN pin. +// +// \param ulName is one of the valid names for the CAN pins. +// +// This function takes one of the valid names for a CAN pin and configures +// the pin for its CAN functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b CAN0RX, \b CAN0TX, +// \b CAN1RX, \b CAN1TX, \b CAN2RX, or \b CAN2TX. +// +// \sa GPIOPinTypeCAN() in order to configure multiple CAN pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeCAN(ulName) GPIOPinTypeCAN(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified comparator pin to function as a comparator pin. +// +// \param ulName is one of the valid names for the Comparator pins. +// +// This function takes one of the valid names for a comparator pin and +// configures the pin for its comparator functionality depending on the part +// that is defined. +// +// The valid names for the pins are as follows: \b C0_MINUS, \b C0_PLUS, +// \b C1_MINUS, \b C1_PLUS, \b C2_MINUS, or \b C2_PLUS. +// +// \sa GPIOPinTypeComparator() in order to configure multiple comparator pins +// at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeComparator(ulName) \ + GPIOPinTypeComparator(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified I2C pin to function as an I2C pin. +// +// \param ulName is one of the valid names for the I2C pins. +// +// This function takes one of the valid names for an I2C pin and configures +// the pin for its I2C functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b I2C0SCL, \b I2C0SDA, +// \b I2C1SCL, or \b I2C1SDA. +// +// \sa GPIOPinTypeI2C() in order to configure multiple I2C pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeI2C(ulName) GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified Ethernet LED to function as an Ethernet LED pin. +// +// \param ulName is one of the valid names for the Ethernet LED pins. +// +// This function takes one of the valid names for an Ethernet LED pin and +// configures the pin for its Ethernet LED functionality depending on the part +// that is defined. +// +// The valid names for the pins are as follows: \b LED0 or \b LED1. +// +// sa GPIOPinTypeEthernetLED() in order to configure multiple Ethernet LED +// pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeEthernetLED(ulName) \ + GPIOPinTypeEthernetLED(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified PWM pin to function as a PWM pin. +// +// \param ulName is one of the valid names for the PWM pins. +// +// This function takes one of the valid names for a PWM pin and configures +// the pin for its PWM functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b PWM0, \b PWM1, \b PWM2, +// \b PWM3, \b PWM4, \b PWM5, or \b FAULT. +// +// \sa GPIOPinTypePWM() in order to configure multiple PWM pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypePWM(ulName) GPIOPinTypePWM(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified QEI pin to function as a QEI pin. +// +// \param ulName is one of the valid names for the QEI pins. +// +// This function takes one of the valid names for a QEI pin and configures +// the pin for its QEI functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b PHA0, \b PHB0, \b IDX0, +// \b PHA1, \b PHB1, or \b IDX1. +// +// \sa GPIOPinTypeQEI() in order to configure multiple QEI pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeQEI(ulName) GPIOPinTypeQEI(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified SSI pin to function as an SSI pin. +// +// \param ulName is one of the valid names for the SSI pins. +// +// This function takes one of the valid names for an SSI pin and configures +// the pin for its SSI functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b SSI0CLK, \b SSI0FSS, +// \b SSI0RX, \b SSI0TX, \b SSI1CLK, \b SSI1FSS, \b SSI1RX, or \b SSI1TX. +// +// \sa GPIOPinTypeSSI() in order to configure multiple SSI pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeSSI(ulName) GPIOPinTypeSSI(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified Timer pin to function as a Timer pin. +// +// \param ulName is one of the valid names for the Timer pins. +// +// This function takes one of the valid names for a Timer pin and configures +// the pin for its Timer functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b CCP0, \b CCP1, \b CCP2, +// \b CCP3, \b CCP4, \b CCP5, \b CCP6, or \b CCP7. +// +// \sa GPIOPinTypeTimer() in order to configure multiple CCP pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeTimer(ulName) GPIOPinTypeTimer(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +// Configures the specified UART pin to function as a UART pin. +// +// \param ulName is one of the valid names for the UART pins. +// +// This function takes one of the valid names for a UART pin and configures +// the pin for its UART functionality depending on the part that is defined. +// +// The valid names for the pins are as follows: \b U0RX, \b U0TX, \b U1RX, +// \b U1TX, \b U2RX, or \b U2TX. +// +// \sa GPIOPinTypeUART() in order to configure multiple UART pins at once. +// +// \return None. +// +//***************************************************************************** +#define PinTypeUART(ulName) GPIOPinTypeUART(ulName##_PORT, ulName##_PIN) + +//***************************************************************************** +// +//! Configures the specified USB digital pin to function as a USB pin. +//! +//! \param ulName is one of the valid names for a USB digital pin. +//! +//! This function takes one of the valid names for a USB digital pin and +//! configures the pin for its USB functionality depending on the part that is +//! defined. +//! +//! The valid names for the pins are as follows: \b EPEN or \b PFAULT. +//! +//! \sa GPIOPinTypeUSBDigital() in order to configure multiple USB pins at +//! once. +//! +//! \return None. +// +//***************************************************************************** +#define PinTypeUSBDigital(ulName) \ + GPIOPinTypeUSBDigital(ulName##_PORT, \ + ulName##_PIN) + +//***************************************************************************** +// +//! Enables the peripheral port used by the given pin. +//! +//! \param ulName is one of the valid names for a pin. +//! +//! This function takes one of the valid names for a pin function and +//! enables the peripheral port for that pin depending on the part that is +//! defined. +//! +//! Any valid pin name can be used. +//! +//! \sa SysCtlPeripheralEnable() in order to enable a single port when +//! multiple pins are on the same port. +//! +//! \return None. +// +//***************************************************************************** +#define PeripheralEnable(ulName) \ + SysCtlPeripheralEnable(ulName##_PERIPH) + +#endif // __PIN_MAP_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/pwm.h b/cpu/stellaris_common/include/stellaris_periph/pwm.h new file mode 100644 index 0000000000..d7843cc480 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/pwm.h @@ -0,0 +1,298 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode +#define PWM_GEN_MODE_FAULT_LATCHED \ + 0x00040000 // Fault is latched +#define PWM_GEN_MODE_FAULT_UNLATCHED \ + 0x00000000 // Fault is not latched +#define PWM_GEN_MODE_FAULT_MINPER \ + 0x00020000 // Enable min fault period +#define PWM_GEN_MODE_FAULT_NO_MINPER \ + 0x00000000 // Disable min fault period +#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support +#define PWM_GEN_MODE_FAULT_LEGACY \ + 0x00000000 // Disable extended fault support +#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur + // immediately +#define PWM_GEN_MODE_DB_SYNC_LOCAL \ + 0x0000A800 // Deadband updates locally + // synchronized +#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ + 0x0000FC00 // Deadband updates globally + // synchronized +#define PWM_GEN_MODE_GEN_NO_SYNC \ + 0x00000000 // Generator mode updates occur + // immediately +#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ + 0x00000280 // Generator mode updates locally + // synchronized +#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ + 0x000003C0 // Generator mode updates globally + // synchronized + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt +#ifndef DEPRECATED +#define PWM_INT_FAULT 0x00010000 // Fault interrupt +#endif +#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt +#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt +#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt +#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt +#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 +#define PWM_GEN_3 0x00000100 // Offset address of Gen3 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 +#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 + +#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range +#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range +#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range +#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 +#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 +#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 +#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 +#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_0 0 + +#define PWM_FAULT_FAULT0 0x00000001 +#define PWM_FAULT_FAULT1 0x00000002 +#define PWM_FAULT_FAULT2 0x00000004 +#define PWM_FAULT_FAULT3 0x00000008 +#define PWM_FAULT_ACMP0 0x00010000 +#define PWM_FAULT_ACMP1 0x00020000 +#define PWM_FAULT_ACMP2 0x00040000 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_1. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_1 1 + +#define PWM_FAULT_DCMP0 0x00000001 +#define PWM_FAULT_DCMP1 0x00000002 +#define PWM_FAULT_DCMP2 0x00000004 +#define PWM_FAULT_DCMP3 0x00000008 +#define PWM_FAULT_DCMP4 0x00000010 +#define PWM_FAULT_DCMP5 0x00000020 +#define PWM_FAULT_DCMP6 0x00000040 +#define PWM_FAULT_DCMP7 0x00000080 + +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +#define PWM_FAULT0_SENSE_HIGH 0x00000000 +#define PWM_FAULT0_SENSE_LOW 0x00000001 +#define PWM_FAULT1_SENSE_HIGH 0x00000000 +#define PWM_FAULT1_SENSE_LOW 0x00000002 +#define PWM_FAULT2_SENSE_HIGH 0x00000000 +#define PWM_FAULT2_SENSE_LOW 0x00000004 +#define PWM_FAULT3_SENSE_HIGH 0x00000000 +#define PWM_FAULT3_SENSE_LOW 0x00000008 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFaultLevel(unsigned long ulBase, + unsigned long ulPWMOutBits, + tBoolean bDriveHigh); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultSuppress); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void PWMFaultIntClearExt(unsigned long ulBase, + unsigned long ulFaultInts); +extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulMinFaultPeriod, + unsigned long ulFaultSenses); +extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); +extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern unsigned long PWMGenFaultStatus(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/readme.txt b/cpu/stellaris_common/include/stellaris_periph/readme.txt new file mode 100644 index 0000000000..6e466a9890 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/readme.txt @@ -0,0 +1,36 @@ +This project will build the Stellaris Peripheral Driver Library. + +------------------------------------------------------------------------------- + +Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. +Software License Agreement + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +This is part of revision 9453 of the Stellaris Peripheral Driver Library. diff --git a/cpu/stellaris_common/include/stellaris_periph/rom.h b/cpu/stellaris_common/include/stellaris_periph/rom.h new file mode 100644 index 0000000000..b16bc64fe9 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/rom.h @@ -0,0 +1,6744 @@ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((unsigned long *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14])) +#define ROM_ETHERNETTABLE ((unsigned long *)(ROM_APITABLE[15])) +#define ROM_USBTABLE ((unsigned long *)(ROM_APITABLE[16])) +#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[17])) +#define ROM_CANTABLE ((unsigned long *)(ROM_APITABLE[18])) +#define ROM_HIBERNATETABLE ((unsigned long *)(ROM_APITABLE[19])) +#define ROM_MPUTABLE ((unsigned long *)(ROM_APITABLE[20])) +#define ROM_SOFTWARETABLE ((unsigned long *)(ROM_APITABLE[21])) +#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[22])) +#define ROM_EPITABLE ((unsigned long *)(ROM_APITABLE[23])) +#define ROM_EEPROMTABLE ((unsigned long *)(ROM_APITABLE[24])) +#define ROM_FANTABLE ((unsigned long *)(ROM_APITABLE[25])) +#define ROM_FPUTABLE ((unsigned long *)(ROM_APITABLE[26])) +#define ROM_LPCTABLE ((unsigned long *)(ROM_APITABLE[27])) +#define ROM_PECITABLE ((unsigned long *)(ROM_APITABLE[28])) +#define ROM_SMBUSTABLE ((unsigned long *)(ROM_APITABLE[29])) +#define ROM_SYSEXCTABLE ((unsigned long *)(ROM_APITABLE[30])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceDataGet \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long *pulBuffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + tBoolean bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulTrigger, \ + unsigned long ulPriority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulStep, \ + unsigned long ulConfig))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceOverflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceUnderflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCProcessorTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFactor))ROM_ADCTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulConfig))ROM_ADCTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorRegionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulLowRef, \ + unsigned long ulHighRef))ROM_ADCTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorReset \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + tBoolean bTrigger, \ + tBoolean bInterrupt))ROM_ADCTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCComparatorIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulStatus))ROM_ADCTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCReferenceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRef))ROM_ADCTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCReferenceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCPhaseDelaySet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPhase))ROM_ADCTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCPhaseDelayGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[25]) +#endif +#if defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCResolutionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulResolution))ROM_ADCTABLE[26]) +#endif +#if defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ADCResolutionGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[27]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAN API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntClr))ROM_CANTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANInit \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANEnable \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANDisable \ + ((void (*)(unsigned long ulBase))ROM_CANTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANBitTimingSet \ + ((void (*)(unsigned long ulBase, \ + tCANBitClkParms *pClkParms))ROM_CANTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANBitTimingGet \ + ((void (*)(unsigned long ulBase, \ + tCANBitClkParms *pClkParms))ROM_CANTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANMessageSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID, \ + tCANMsgObject *pMsgObject, \ + tMsgObjType eMsgType))ROM_CANTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANMessageGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID, \ + tCANMsgObject *pMsgObject, \ + tBoolean bClrPendingInt))ROM_CANTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + tCANStsReg eStatusReg))ROM_CANTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANMessageClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulObjID))ROM_CANTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CANTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_CANTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANRetryGet \ + ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANRetrySet \ + ((void (*)(unsigned long ulBase, \ + tBoolean bAutoRetry))ROM_CANTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANErrCntrGet \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long *pulRxCount, \ + unsigned long *pulTxCount))ROM_CANTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_CANBitRateSet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulSourceClock, \ + unsigned long ulBitRate))ROM_CANTABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Comparator API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulConfig))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorRefSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRef))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorValueGet \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_ComparatorIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + tBoolean bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EEPROM API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMRead \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_EEPROMTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockCountGet \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockHide \ + ((void (*)(unsigned long ulBlock))ROM_EEPROMTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockLock \ + ((unsigned long (*)(unsigned long ulBlock))ROM_EEPROMTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockPasswordSet \ + ((unsigned long (*)(unsigned long ulBlock, \ + unsigned long *pulPassword, \ + unsigned long ulCount))ROM_EEPROMTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockProtectGet \ + ((unsigned long (*)(unsigned long ulBlock))ROM_EEPROMTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockProtectSet \ + ((unsigned long (*)(unsigned long ulBlock, \ + unsigned long ulProtect))ROM_EEPROMTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMBlockUnlock \ + ((unsigned long (*)(unsigned long ulBlock, \ + unsigned long *pulPassword, \ + unsigned long ulCount))ROM_EEPROMTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_EEPROMTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_EEPROMTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_EEPROMTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_EEPROMTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMMassErase \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMProgram \ + ((unsigned long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_EEPROMTABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMProgramNonBlocking \ + ((unsigned long (*)(unsigned long ulData, \ + unsigned long ulAddress))ROM_EEPROMTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMSizeGet \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMStatusGet \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_EEPROMInit \ + ((unsigned long (*)(void))ROM_EEPROMTABLE[17]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EPI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_EPITABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_EPITABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIDividerSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDivider))ROM_EPITABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigSDRAMSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulRefresh))ROM_EPITABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigGPModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulFrameCount, \ + unsigned long ulMaxWait))ROM_EPITABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigHB8Set \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxWait))ROM_EPITABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIConfigHB16Set \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxWait))ROM_EPITABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIAddressMapSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMap))ROM_EPITABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulDataSize, \ + unsigned long ulAddress))ROM_EPITABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadStart \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulCount))ROM_EPITABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadStop \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_EPITABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadCount \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_EPITABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadAvail \ + ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadGet32 \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulCount, \ + unsigned long *pulBuf))ROM_EPITABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadGet16 \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulCount, \ + unsigned short *pusBuf))ROM_EPITABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPINonBlockingReadGet8 \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulCount, \ + unsigned char *pucBuf))ROM_EPITABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIFIFOConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_EPITABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIWriteFIFOCountGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_EPITABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_EPITABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntErrorStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EPIIntErrorClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulErrFlags))ROM_EPITABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Ethernet API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetInitExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEthClk))ROM_ETHERNETTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_ETHERNETTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetMACAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetMACAddrGet \ + ((void (*)(unsigned long ulBase, \ + unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetEnable \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetDisable \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketGet \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPacketPut \ + ((long (*)(unsigned long ulBase, \ + unsigned char *pucBuf, \ + long lBufLen))ROM_ETHERNETTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_ETHERNETTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_ETHERNETTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucRegAddr, \ + unsigned long ulData))ROM_ETHERNETTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYRead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned char ucRegAddr))ROM_ETHERNETTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_UpdateEthernet \ + ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr))ROM_ETHERNETTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYPowerOff \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_EthernetPHYPowerOn \ + ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[22]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Fan API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelConfigAuto \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig))ROM_FANTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelConfigManual \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig))ROM_FANTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelDutyGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelDutySet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulDuty))ROM_FANTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelRPMGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelRPMSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulRPM))ROM_FANTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_FANTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanChannelsGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_FANTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_FANTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FanIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_FANTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Flash API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProgram \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUsecGet \ + ((unsigned long (*)(void))ROM_FLASHTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUsecSet \ + ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashErase \ + ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProtectSet \ + ((long (*)(unsigned long ulAddress, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashProtectSave \ + ((long (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUserGet \ + ((long (*)(unsigned long *pulUser0, \ + unsigned long *pulUser1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUserSet \ + ((long (*)(unsigned long ulUser0, \ + unsigned long ulUser1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashUserSave \ + ((long (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FlashIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the FPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUEnable \ + ((void (*)(void))ROM_FPUTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUDisable \ + ((void (*)(void))ROM_FPUTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUFlushToZeroModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUHalfPrecisionModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPULazyStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUNaNModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPURoundingModeSet \ + ((void (*)(unsigned long ulMode))ROM_FPUTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUStackingDisable \ + ((void (*)(void))ROM_FPUTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_FPUStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[8]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinWrite \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned char ucVal))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODirModeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulPinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODirModeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOIntTypeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulIntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOIntTypeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPadConfigSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulStrength, \ + unsigned long ulPadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPadConfigGet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPin, \ + unsigned long *pulStrength, \ + unsigned long *pulPadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntStatus \ + ((long (*)(unsigned long ulPort, \ + tBoolean bMasked))ROM_GPIOTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinIntClear \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinRead \ + ((long (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypePWM \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeUART \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeADC \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeUSBDigital \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeI2S \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinConfigure \ + ((void (*)(unsigned long ulPinConfig))ROM_GPIOTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEthernetLED \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeUSBAnalog \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[28]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEPI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_GPIOPinTypeEthernetMII \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOADCTriggerEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOADCTriggerDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeFan \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeLPC \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypePECIRx \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypePECITx \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[38]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_GPIOPinTypeI2CSCL \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[39]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Hibernate API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateEnableExpClk \ + ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateClockSelect \ + ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateWakeSet \ + ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateWakeGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateLowBatSet \ + ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateLowBatGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSet \ + ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCMatch0Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCMatch0Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_HibernateRTCMatch1Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_HibernateRTCMatch1Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCTrimSet \ + ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCTrimGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateDataSet \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulCount))ROM_HIBERNATETABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateDataGet \ + ((void (*)(unsigned long *pulData, \ + unsigned long ulCount))ROM_HIBERNATETABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRequest \ + ((void (*)(void))ROM_HIBERNATETABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateIsActive \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSSMatch0Set \ + ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSSMatch0Get \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateRTCSSGet \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateClockConfig \ + ((void (*)(unsigned long ulConfig))ROM_HIBERNATETABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateBatCheckStart \ + ((void (*)(void))ROM_HIBERNATETABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_HibernateBatCheckDone \ + ((unsigned long (*)(void))ROM_HIBERNATETABLE[30]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulI2CClk, \ + tBoolean bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveInit \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr, \ + tBoolean bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterBusBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterErr \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntStatusEx \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntStatusEx \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2CTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulValue))ROM_I2CTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(unsigned long ulBase, \ + tBoolean bEnable))ROM_I2CTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(unsigned long ulBase, \ + tBoolean bACK))ROM_I2CTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddrNum, \ + unsigned char ucSlaveAddr))ROM_I2CTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_I2CMasterLineStateGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[38]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2S API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2STABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxEnable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_I2STABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_I2STABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_I2STABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxFIFOLimitSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLevel))ROM_I2STABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxFIFOLimitGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxFIFOLevelGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxEnable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_I2STABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_I2STABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_I2STABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxFIFOLimitSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLevel))ROM_I2STABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxFIFOLimitGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SRxFIFOLevelGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxRxEnable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxRxDisable \ + ((void (*)(unsigned long ulBase))ROM_I2STABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2STxRxConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_I2STABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SMasterClockSelect \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMClock))ROM_I2STABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_I2SIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_I2STABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntEnable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntMasterEnable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntMasterDisable \ + ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntDisable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityGroupingGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPrioritySet \ + ((void (*)(unsigned long ulInterrupt, \ + unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityGet \ + ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPendSet \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPendClear \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityMaskSet \ + ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_IntPriorityMaskGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the LPC API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCByteRead \ + ((unsigned char (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCByteWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned char ucData))ROM_LPCTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigCOMxSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset, \ + unsigned long ulCOMxMode))ROM_LPCTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long *pulAddress, \ + unsigned long *pulOffset, \ + unsigned long *pulCOMxMode))ROM_LPCTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigEPSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset))ROM_LPCTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelConfigMBSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulConfig, \ + unsigned long ulAddress, \ + unsigned long ulOffset))ROM_LPCTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelDMAConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelDMAConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMask))ROM_LPCTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulStatus))ROM_LPCTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelStatusSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulChannel, \ + unsigned long ulStatus))ROM_LPCTABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCCOMxIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_LPCTABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCConfigGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_LPCTABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCHalfWordRead \ + ((unsigned short (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[20]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCHalfWordWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned short usData))ROM_LPCTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIRQ))ROM_LPCTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQConfig \ + ((void (*)(unsigned long ulBase, \ + tBoolean bIRQPulse, \ + tBoolean bIRQOnChange))ROM_LPCTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_LPCTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQSend \ + ((void (*)(unsigned long ulBase))ROM_LPCTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIRQSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIRQ))ROM_LPCTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_LPCTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_LPCTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCSCIAssert \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCount))ROM_LPCTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long *pulCount, \ + unsigned long *pulPoolSize))ROM_LPCTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCWordRead \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulOffset))ROM_LPCTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCWordWrite \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulOffset, \ + unsigned long ulData))ROM_LPCTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCChannelPoolAddressGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulChannel))ROM_LPCTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCStatusBlockAddressGet \ + ((unsigned (*)(unsigned long ulBase))ROM_LPCTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_LPCStatusBlockAddressSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulAddress, \ + tBoolean bEnabled))ROM_LPCTABLE[36]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the MPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPUEnable \ + ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPUDisable \ + ((void (*)(void))ROM_MPUTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionCountGet \ + ((unsigned long (*)(void))ROM_MPUTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionEnable \ + ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionDisable \ + ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionSet \ + ((void (*)(unsigned long ulRegion, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_MPUTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_MPURegionGet \ + ((void (*)(unsigned long ulRegion, \ + unsigned long *pulAddr, \ + unsigned long *pulFlags))ROM_MPUTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PECI API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_PECITABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIAdvCmdSend \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucCmd, \ + unsigned char ucHidRe, \ + unsigned char ucDomain, \ + unsigned char ucProcAdd, \ + unsigned long ulArg, \ + unsigned char ucSize, \ + unsigned long ulData0, \ + unsigned long ulData1))ROM_PECITABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIAdvCmdSendNonBlocking \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned char ucCmd, \ + unsigned char ucHidRe, \ + unsigned char ucDomain, \ + unsigned char ucProcAdd, \ + unsigned long ulArg, \ + unsigned char ucSize, \ + unsigned long ulData0, \ + unsigned long ulData1))ROM_PECITABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIAdvCmdStatusGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long *pulData0, \ + unsigned long *pulData1))ROM_PECITABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPECIClk, \ + unsigned long *pulBaud, \ + unsigned long *pulPoll, \ + unsigned long *pulOffset, \ + unsigned long *pulRetry))ROM_PECITABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPECIClk, \ + unsigned long ulBaud, \ + unsigned long ulPoll, \ + unsigned long ulOffset, \ + unsigned long ulRetry))ROM_PECITABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainMaxReadClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainValueClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain, \ + unsigned long *pulHigh, \ + unsigned long *pulLow))ROM_PECITABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain, \ + unsigned long ulHigh, \ + unsigned long ulLow))ROM_PECITABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainMaxReadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIDomainValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulDomain))ROM_PECITABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_PECITABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags, \ + unsigned long ulIntMode))ROM_PECITABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_PECITABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIBypassEnable \ + ((void (*)(unsigned long ulBase))ROM_PECITABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PECIBypassDisable \ + ((void (*)(unsigned long ulBase))ROM_PECITABLE[18]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PWM API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMPulseWidthSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOut, \ + unsigned long ulWidth))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulConfig))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenPeriodSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulPeriod))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenPeriodGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMPulseWidthGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulPWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMDeadBandEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned short usRise, \ + unsigned short usFall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMDeadBandDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMSyncUpdate \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMSyncTimeBase \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputState \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputInvert \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputFault \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + tBoolean bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulInts))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMFaultIntClear \ + ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_PWMTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMOutputFaultLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bDriveHigh))ROM_PWMTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMFaultIntClearExt \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFaultInts))ROM_PWMTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulMinFaultPeriod, \ + unsigned long ulFaultSenses))ROM_PWMTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultTriggerSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup, \ + unsigned long ulFaultTriggers))ROM_PWMTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultTriggerGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup))ROM_PWMTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup))ROM_PWMTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_PWMGenFaultClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulGroup, \ + unsigned long ulFaultTriggers))ROM_PWMTABLE[28]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the QEI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIPositionGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIPositionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPosition))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIDirectionGet \ + ((long (*)(unsigned long ulBase))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIErrorGet \ + ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPreDiv, \ + unsigned long ulPeriod))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIVelocityGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_QEIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SMBus API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterIntProcess \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPUDIDPacketDecode \ + ((void (*)(tSMBusUDID *pUDID, \ + unsigned char *pucAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusARPUDIDPacketEncode \ + ((void (*)(tSMBusUDID *pUDID, \ + unsigned char ucAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[4]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPAssignAddress \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPGetUDIDDir \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[6]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPGetUDIDGen \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[7]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPNotifyMaster \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char *pucData))ROM_SMBUSTABLE[8]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPPrepareToARP \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[9]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPResetDeviceDir \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress))ROM_SMBUSTABLE[10]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterARPResetDeviceGen \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[11]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterBlockProcessCall \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucTxData, \ + unsigned char ucTxSize, \ + unsigned char *pucRxData))ROM_SMBUSTABLE[12]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterBlockRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData))ROM_SMBUSTABLE[13]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterBlockWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteReceive \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteSend \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucData))ROM_SMBUSTABLE[16]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteWordRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[17]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterByteWordWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterHostNotify \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucOwnSlaveAddress, \ + unsigned char *pucData))ROM_SMBUSTABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterI2CRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[20]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterI2CWrite \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterI2CWriteRead \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char *pucTxData, \ + unsigned char ucTxSize, \ + unsigned char *pucRxData, \ + unsigned char ucRxSize))ROM_SMBUSTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterInit \ + ((void (*)(tSMBus *pSMBus, \ + unsigned long ulI2CBase, \ + unsigned long ulSMBusClock))ROM_SMBUSTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterIntEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterProcessCall \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + unsigned char ucCommand, \ + unsigned char *pucTxData, \ + unsigned char *pucRxData))ROM_SMBUSTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusMasterQuickCommand \ + ((tSMBusStatus (*)(tSMBus *pSMBus, \ + unsigned char ucTargetAddress, \ + tBoolean bData))ROM_SMBUSTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusPECDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[27]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusPECEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[28]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusRxPacketSizeGet \ + ((unsigned char (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[29]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveACKSend \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bACK))ROM_SMBUSTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveAddressSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char ucAddressNum, \ + unsigned char ucSlaveAddress))ROM_SMBUSTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagARGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagARSet \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bValue))ROM_SMBUSTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagAVGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveARPFlagAVSet \ + ((void (*)(tSMBus *pSMBus, \ + tBoolean bValue))ROM_SMBUSTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveBlockTransferDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveBlockTransferEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveCommandGet \ + ((unsigned char (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[38]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveI2CDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[39]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveI2CEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[40]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveInit \ + ((void (*)(tSMBus *pSMBus, \ + unsigned long ulI2CBase))ROM_SMBUSTABLE[41]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveIntAddressGet \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[42]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveIntEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[43]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveIntProcess \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[44]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveManualACKDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[45]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveManualACKEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[46]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveManualACKStatusGet \ + ((tBoolean (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[47]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveProcessCallDisable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[48]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveProcessCallEnable \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[49]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveRxBufferSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[50]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveTransferInit \ + ((void (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[51]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveTxBufferSet \ + ((void (*)(tSMBus *pSMBus, \ + unsigned char *pucData, \ + unsigned char ucSize))ROM_SMBUSTABLE[52]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveUDIDSet \ + ((void (*)(tSMBus *pSMBus, \ + tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusStatusGet \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[54]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SMBusSlaveDataSend \ + ((tSMBusStatus (*)(tSMBus *pSMBus))ROM_SMBUSTABLE[55]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SSI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSSIClk, \ + unsigned long ulProtocol, \ + unsigned long ulMode, \ + unsigned long ulBitRate, \ + unsigned long ulDataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIEnable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDisable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_SSITABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_SSITABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_SSITABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIClockSourceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_SSITABLE[15]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SSIClockSourceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSource))ROM_SSITABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysCtl API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlSRAMSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlFlashSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPinPresent \ + ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralPresent \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntEnable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntDisable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntClear \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_SysCtlLDOSet \ + ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_SysCtlLDOGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlResetCauseGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPWMClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlADCSpeedSet \ + ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlADCSpeedGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[28]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlGPIOAHBEnable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlGPIOAHBDisable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlUSBPLLEnable \ + ((void (*)(void))ROM_SYSCTLTABLE[31]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlUSBPLLDisable \ + ((void (*)(void))ROM_SYSCTLTABLE[32]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) +#define ROM_SysCtlI2SMClkSet \ + ((unsigned long (*)(unsigned long ulInputClock, \ + unsigned long ulMClk))ROM_SYSCTLTABLE[33]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlDelay \ + ((void (*)(unsigned long ulCount))ROM_SYSCTLTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralReady \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralPowerOn \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[36]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPeripheralPowerOff \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[37]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlMOSCConfigSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[44]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlPIOSCCalibrate \ + ((unsigned long (*)(unsigned long ulType))ROM_SYSCTLTABLE[45]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysCtlDeepSleepClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[46]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysExc API. +// +//***************************************************************************** +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_SYSEXCTABLE[0]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[1]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysExcIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_SYSEXCTABLE[3]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysTick API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickValueGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickPeriodSet \ + ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_SysTickPeriodGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlEvent \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulEvent))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerRTCEnable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerRTCDisable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerPrescaleMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_TIMERTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerControlWaitOnTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bWait))ROM_TIMERTABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadSet64 \ + ((void (*)(unsigned long ulBase, \ + unsigned long long ullValue))ROM_TIMERTABLE[23]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerLoadGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[24]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerValueGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[25]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchSet64 \ + ((void (*)(unsigned long ulBase, \ + unsigned long long ullValue))ROM_TIMERTABLE[26]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_TimerMatchGet64 \ + ((unsigned long long (*)(unsigned long ulBase))ROM_TIMERTABLE[27]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTParityModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulParity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTParityModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long ulBaud, \ + unsigned long ulConfig))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long *pulBaud, \ + unsigned long *pulConfig))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTEnableSIR \ + ((void (*)(unsigned long ulBase, \ + tBoolean bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDisableSIR \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharsAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharGetNonBlocking \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharGet \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTCharPutNonBlocking \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTBreakCtl \ + ((void (*)(unsigned long ulBase, \ + tBoolean bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulDMAFlags))ROM_UARTTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFOEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTFIFODisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTTxIntModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulMode))ROM_UARTTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTTxIntModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[28]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTRxErrorGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTRxErrorClear \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[30]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTClockSourceSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSource))ROM_UARTTABLE[31]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UARTClockSourceGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[32]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[33]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[34]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr, \ + unsigned char ucMask))ROM_UARTTABLE[35]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UART9BitAddrSend \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucAddr))ROM_UARTTABLE[36]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulMode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + unsigned long ulTransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAErrorStatusGet \ + ((unsigned long (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelEnable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelDisable \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelIsEnabled \ + ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelRequest \ + ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned long ulAttr))ROM_UDMATABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAttributeGet \ + ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelControlSet \ + ((void (*)(unsigned long ulChannelStructIndex, \ + unsigned long ulControl))ROM_UDMATABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelSizeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelModeGet \ + ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelSelectSecondary \ + ((void (*)(unsigned long ulSecPeriphs))ROM_UDMATABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelSelectDefault \ + ((void (*)(unsigned long ulDefPeriphs))ROM_UDMATABLE[18]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAIntStatus \ + ((unsigned long (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAIntClear \ + ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[21]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(unsigned long ulChannelNum, \ + unsigned ulTaskCount, \ + void *pvTaskList, \ + unsigned long ulIsPeriphSG))ROM_UDMATABLE[22]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_uDMAChannelAssign \ + ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the USB API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevAddrGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulAddress))ROM_USBTABLE[2]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevConnect \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[3]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevDisconnect \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulMaxPacketSize, \ + unsigned long ulFlags))ROM_USBTABLE[5]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointDataAck \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + tBoolean bIsLastPacket))ROM_USBTABLE[6]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[7]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointStallClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[8]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[9]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataGet \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned char *pucData, \ + unsigned long *pulSize))ROM_USBTABLE[10]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataPut \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned char *pucData, \ + unsigned long ulSize))ROM_USBTABLE[11]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataSend \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulTransType))ROM_USBTABLE[12]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataToggleClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[13]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[14]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[15]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long *pulFIFOAddress, \ + unsigned long *pulFIFOSize, \ + unsigned long ulFlags))ROM_USBTABLE[16]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOConfigSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFIFOAddress, \ + unsigned long ulFIFOSize, \ + unsigned long ulFlags))ROM_USBTABLE[17]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFIFOFlush \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[18]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBFrameNumberGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[20]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_USBTABLE[21]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulMaxPacketSize, \ + unsigned long ulNAKPollInterval, \ + unsigned long ulTargetEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[22]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointDataAck \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[23]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointDataToggle \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + tBoolean bDataToggle, \ + unsigned long ulFlags))ROM_USBTABLE[24]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostEndpointStatusClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[25]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostHubAddrGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[26]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostHubAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulAddr, \ + unsigned long ulFlags))ROM_USBTABLE[27]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrDisable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[28]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrEnable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[29]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrConfig \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFlags))ROM_USBTABLE[30]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrFaultDisable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[31]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostPwrFaultEnable \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[32]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostRequestIN \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[33]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostRequestStatus \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[34]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostReset \ + ((void (*)(unsigned long ulBase, \ + tBoolean bStart))ROM_USBTABLE[35]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostResume \ + ((void (*)(unsigned long ulBase, \ + tBoolean bStart))ROM_USBTABLE[36]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostSpeedGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostSuspend \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[38]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[39]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[40]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevEndpointConfigGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long *pulMaxPacketSize, \ + unsigned long *pulFlags))ROM_USBTABLE[41]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDMAEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[42]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDMADisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulFlags))ROM_USBTABLE[43]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDataAvail \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulEndpoint))ROM_USBTABLE[44]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBOTGHostRequest \ + ((void (*)(unsigned long ulBase, \ + tBoolean bHNP))ROM_USBTABLE[45]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[46]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBEndpointDMAChannel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulEndpoint, \ + unsigned long ulChannel))ROM_USBTABLE[47]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntDisableControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[48]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntEnableControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[49]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntStatusControl \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[50]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntDisableEndpoint \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[51]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntEnableEndpoint \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_USBTABLE[52]) +#endif +#if defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBIntStatusEndpoint \ + ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[53]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBHostMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[54]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBDevMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[55]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBPHYPowerOff \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[56]) +#endif +#if defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBPHYPowerOn \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[57]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_UpdateUSB \ + ((void (*)(unsigned char *pucDescriptorInfo))ROM_USBTABLE[58]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_USBOTGMode \ + ((void (*)(unsigned long ulBase))ROM_USBTABLE[59]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntClear \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogRunning \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogResetEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogResetDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogLock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogUnlock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogLockState \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogReloadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogReloadGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogStallEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) || \ + defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogStallDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_WatchdogIntTypeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulType))ROM_WATCHDOGTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Software API. +// +//***************************************************************************** +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc16Array \ + ((unsigned short (*)(unsigned long ulWordLen, \ + const unsigned long *pulData))ROM_SOFTWARETABLE[1]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc16Array3 \ + ((void (*)(unsigned long ulWordLen, \ + const unsigned long *pulData, \ + unsigned short *pusCrc3))ROM_SOFTWARETABLE[2]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc16 \ + ((unsigned short (*)(unsigned short usCrc, \ + const unsigned char *pucData, \ + unsigned long ulCount))ROM_SOFTWARETABLE[3]) +#endif +#if defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_Crc8CCITT \ + ((unsigned char (*)(unsigned char ucCrc, \ + const unsigned char *pucData, \ + unsigned long ulCount))ROM_SOFTWARETABLE[4]) +#endif +#if defined(TARGET_IS_TEMPEST_RB1) || \ + defined(TARGET_IS_TEMPEST_RC1) || \ + defined(TARGET_IS_TEMPEST_RC3) || \ + defined(TARGET_IS_TEMPEST_RC5) || \ + defined(TARGET_IS_FIRESTORM_RA2) || \ + defined(TARGET_IS_BLIZZARD_RA1) || \ + defined(TARGET_IS_BLIZZARD_RA2) +#define ROM_pvAESTable \ + ((void *)&(ROM_SOFTWARETABLE[7])) +#endif + +//***************************************************************************** +// +// Deprecated ROM functions. +// +//***************************************************************************** +#ifndef DEPRECATED +#ifdef ROM_FlashIntStatus +#define ROM_FlashIntGetStatus \ + ROM_FlashIntStatus +#endif +#ifdef ROM_USBDevEndpointConfigSet +#define ROM_USBDevEndpointConfig \ + ROM_USBDevEndpointConfigSet +#endif +#ifdef ROM_USBHostPwrConfig +#define ROM_USBHostPwrFaultConfig \ + ROM_USBHostPwrConfig +#endif +#endif + +#endif // __ROM_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/rom_map.h b/cpu/stellaris_common/include/stellaris_periph/rom_map.h new file mode 100644 index 0000000000..53e8e20dbd --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/rom_map.h @@ -0,0 +1,5075 @@ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available and in flash otherwise. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_MAP_H__ +#define __ROM_MAP_H__ + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCSequenceDataGet +#define MAP_ADCSequenceDataGet \ + ROM_ADCSequenceDataGet +#else +#define MAP_ADCSequenceDataGet \ + ADCSequenceDataGet +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCSequenceEnable +#define MAP_ADCSequenceEnable \ + ROM_ADCSequenceEnable +#else +#define MAP_ADCSequenceEnable \ + ADCSequenceEnable +#endif +#ifdef ROM_ADCSequenceDisable +#define MAP_ADCSequenceDisable \ + ROM_ADCSequenceDisable +#else +#define MAP_ADCSequenceDisable \ + ADCSequenceDisable +#endif +#ifdef ROM_ADCSequenceConfigure +#define MAP_ADCSequenceConfigure \ + ROM_ADCSequenceConfigure +#else +#define MAP_ADCSequenceConfigure \ + ADCSequenceConfigure +#endif +#ifdef ROM_ADCSequenceStepConfigure +#define MAP_ADCSequenceStepConfigure \ + ROM_ADCSequenceStepConfigure +#else +#define MAP_ADCSequenceStepConfigure \ + ADCSequenceStepConfigure +#endif +#ifdef ROM_ADCSequenceOverflow +#define MAP_ADCSequenceOverflow \ + ROM_ADCSequenceOverflow +#else +#define MAP_ADCSequenceOverflow \ + ADCSequenceOverflow +#endif +#ifdef ROM_ADCSequenceOverflowClear +#define MAP_ADCSequenceOverflowClear \ + ROM_ADCSequenceOverflowClear +#else +#define MAP_ADCSequenceOverflowClear \ + ADCSequenceOverflowClear +#endif +#ifdef ROM_ADCSequenceUnderflow +#define MAP_ADCSequenceUnderflow \ + ROM_ADCSequenceUnderflow +#else +#define MAP_ADCSequenceUnderflow \ + ADCSequenceUnderflow +#endif +#ifdef ROM_ADCSequenceUnderflowClear +#define MAP_ADCSequenceUnderflowClear \ + ROM_ADCSequenceUnderflowClear +#else +#define MAP_ADCSequenceUnderflowClear \ + ADCSequenceUnderflowClear +#endif +#ifdef ROM_ADCProcessorTrigger +#define MAP_ADCProcessorTrigger \ + ROM_ADCProcessorTrigger +#else +#define MAP_ADCProcessorTrigger \ + ADCProcessorTrigger +#endif +#ifdef ROM_ADCHardwareOversampleConfigure +#define MAP_ADCHardwareOversampleConfigure \ + ROM_ADCHardwareOversampleConfigure +#else +#define MAP_ADCHardwareOversampleConfigure \ + ADCHardwareOversampleConfigure +#endif +#ifdef ROM_ADCComparatorConfigure +#define MAP_ADCComparatorConfigure \ + ROM_ADCComparatorConfigure +#else +#define MAP_ADCComparatorConfigure \ + ADCComparatorConfigure +#endif +#ifdef ROM_ADCComparatorRegionSet +#define MAP_ADCComparatorRegionSet \ + ROM_ADCComparatorRegionSet +#else +#define MAP_ADCComparatorRegionSet \ + ADCComparatorRegionSet +#endif +#ifdef ROM_ADCComparatorReset +#define MAP_ADCComparatorReset \ + ROM_ADCComparatorReset +#else +#define MAP_ADCComparatorReset \ + ADCComparatorReset +#endif +#ifdef ROM_ADCComparatorIntDisable +#define MAP_ADCComparatorIntDisable \ + ROM_ADCComparatorIntDisable +#else +#define MAP_ADCComparatorIntDisable \ + ADCComparatorIntDisable +#endif +#ifdef ROM_ADCComparatorIntEnable +#define MAP_ADCComparatorIntEnable \ + ROM_ADCComparatorIntEnable +#else +#define MAP_ADCComparatorIntEnable \ + ADCComparatorIntEnable +#endif +#ifdef ROM_ADCComparatorIntStatus +#define MAP_ADCComparatorIntStatus \ + ROM_ADCComparatorIntStatus +#else +#define MAP_ADCComparatorIntStatus \ + ADCComparatorIntStatus +#endif +#ifdef ROM_ADCComparatorIntClear +#define MAP_ADCComparatorIntClear \ + ROM_ADCComparatorIntClear +#else +#define MAP_ADCComparatorIntClear \ + ADCComparatorIntClear +#endif +#ifdef ROM_ADCReferenceSet +#define MAP_ADCReferenceSet \ + ROM_ADCReferenceSet +#else +#define MAP_ADCReferenceSet \ + ADCReferenceSet +#endif +#ifdef ROM_ADCReferenceGet +#define MAP_ADCReferenceGet \ + ROM_ADCReferenceGet +#else +#define MAP_ADCReferenceGet \ + ADCReferenceGet +#endif +#ifdef ROM_ADCPhaseDelaySet +#define MAP_ADCPhaseDelaySet \ + ROM_ADCPhaseDelaySet +#else +#define MAP_ADCPhaseDelaySet \ + ADCPhaseDelaySet +#endif +#ifdef ROM_ADCPhaseDelayGet +#define MAP_ADCPhaseDelayGet \ + ROM_ADCPhaseDelayGet +#else +#define MAP_ADCPhaseDelayGet \ + ADCPhaseDelayGet +#endif +#ifdef ROM_ADCResolutionSet +#define MAP_ADCResolutionSet \ + ROM_ADCResolutionSet +#else +#define MAP_ADCResolutionSet \ + ADCResolutionSet +#endif +#ifdef ROM_ADCResolutionGet +#define MAP_ADCResolutionGet \ + ROM_ADCResolutionGet +#else +#define MAP_ADCResolutionGet \ + ADCResolutionGet +#endif + +//***************************************************************************** +// +// Macros for the CAN API. +// +//***************************************************************************** +#ifdef ROM_CANIntClear +#define MAP_CANIntClear \ + ROM_CANIntClear +#else +#define MAP_CANIntClear \ + CANIntClear +#endif +#ifdef ROM_CANInit +#define MAP_CANInit \ + ROM_CANInit +#else +#define MAP_CANInit \ + CANInit +#endif +#ifdef ROM_CANEnable +#define MAP_CANEnable \ + ROM_CANEnable +#else +#define MAP_CANEnable \ + CANEnable +#endif +#ifdef ROM_CANDisable +#define MAP_CANDisable \ + ROM_CANDisable +#else +#define MAP_CANDisable \ + CANDisable +#endif +#ifdef ROM_CANBitTimingSet +#define MAP_CANBitTimingSet \ + ROM_CANBitTimingSet +#else +#define MAP_CANBitTimingSet \ + CANBitTimingSet +#endif +#ifdef ROM_CANBitTimingGet +#define MAP_CANBitTimingGet \ + ROM_CANBitTimingGet +#else +#define MAP_CANBitTimingGet \ + CANBitTimingGet +#endif +#ifdef ROM_CANMessageSet +#define MAP_CANMessageSet \ + ROM_CANMessageSet +#else +#define MAP_CANMessageSet \ + CANMessageSet +#endif +#ifdef ROM_CANMessageGet +#define MAP_CANMessageGet \ + ROM_CANMessageGet +#else +#define MAP_CANMessageGet \ + CANMessageGet +#endif +#ifdef ROM_CANStatusGet +#define MAP_CANStatusGet \ + ROM_CANStatusGet +#else +#define MAP_CANStatusGet \ + CANStatusGet +#endif +#ifdef ROM_CANMessageClear +#define MAP_CANMessageClear \ + ROM_CANMessageClear +#else +#define MAP_CANMessageClear \ + CANMessageClear +#endif +#ifdef ROM_CANIntEnable +#define MAP_CANIntEnable \ + ROM_CANIntEnable +#else +#define MAP_CANIntEnable \ + CANIntEnable +#endif +#ifdef ROM_CANIntDisable +#define MAP_CANIntDisable \ + ROM_CANIntDisable +#else +#define MAP_CANIntDisable \ + CANIntDisable +#endif +#ifdef ROM_CANIntStatus +#define MAP_CANIntStatus \ + ROM_CANIntStatus +#else +#define MAP_CANIntStatus \ + CANIntStatus +#endif +#ifdef ROM_CANRetryGet +#define MAP_CANRetryGet \ + ROM_CANRetryGet +#else +#define MAP_CANRetryGet \ + CANRetryGet +#endif +#ifdef ROM_CANRetrySet +#define MAP_CANRetrySet \ + ROM_CANRetrySet +#else +#define MAP_CANRetrySet \ + CANRetrySet +#endif +#ifdef ROM_CANErrCntrGet +#define MAP_CANErrCntrGet \ + ROM_CANErrCntrGet +#else +#define MAP_CANErrCntrGet \ + CANErrCntrGet +#endif +#ifdef ROM_CANBitRateSet +#define MAP_CANBitRateSet \ + ROM_CANBitRateSet +#else +#define MAP_CANBitRateSet \ + CANBitRateSet +#endif + +//***************************************************************************** +// +// Macros for the Comparator API. +// +//***************************************************************************** +#ifdef ROM_ComparatorIntClear +#define MAP_ComparatorIntClear \ + ROM_ComparatorIntClear +#else +#define MAP_ComparatorIntClear \ + ComparatorIntClear +#endif +#ifdef ROM_ComparatorConfigure +#define MAP_ComparatorConfigure \ + ROM_ComparatorConfigure +#else +#define MAP_ComparatorConfigure \ + ComparatorConfigure +#endif +#ifdef ROM_ComparatorRefSet +#define MAP_ComparatorRefSet \ + ROM_ComparatorRefSet +#else +#define MAP_ComparatorRefSet \ + ComparatorRefSet +#endif +#ifdef ROM_ComparatorValueGet +#define MAP_ComparatorValueGet \ + ROM_ComparatorValueGet +#else +#define MAP_ComparatorValueGet \ + ComparatorValueGet +#endif +#ifdef ROM_ComparatorIntEnable +#define MAP_ComparatorIntEnable \ + ROM_ComparatorIntEnable +#else +#define MAP_ComparatorIntEnable \ + ComparatorIntEnable +#endif +#ifdef ROM_ComparatorIntDisable +#define MAP_ComparatorIntDisable \ + ROM_ComparatorIntDisable +#else +#define MAP_ComparatorIntDisable \ + ComparatorIntDisable +#endif +#ifdef ROM_ComparatorIntStatus +#define MAP_ComparatorIntStatus \ + ROM_ComparatorIntStatus +#else +#define MAP_ComparatorIntStatus \ + ComparatorIntStatus +#endif + +//***************************************************************************** +// +// Macros for the EEPROM API. +// +//***************************************************************************** +#ifdef ROM_EEPROMRead +#define MAP_EEPROMRead \ + ROM_EEPROMRead +#else +#define MAP_EEPROMRead \ + EEPROMRead +#endif +#ifdef ROM_EEPROMBlockCountGet +#define MAP_EEPROMBlockCountGet \ + ROM_EEPROMBlockCountGet +#else +#define MAP_EEPROMBlockCountGet \ + EEPROMBlockCountGet +#endif +#ifdef ROM_EEPROMBlockHide +#define MAP_EEPROMBlockHide \ + ROM_EEPROMBlockHide +#else +#define MAP_EEPROMBlockHide \ + EEPROMBlockHide +#endif +#ifdef ROM_EEPROMBlockLock +#define MAP_EEPROMBlockLock \ + ROM_EEPROMBlockLock +#else +#define MAP_EEPROMBlockLock \ + EEPROMBlockLock +#endif +#ifdef ROM_EEPROMBlockPasswordSet +#define MAP_EEPROMBlockPasswordSet \ + ROM_EEPROMBlockPasswordSet +#else +#define MAP_EEPROMBlockPasswordSet \ + EEPROMBlockPasswordSet +#endif +#ifdef ROM_EEPROMBlockProtectGet +#define MAP_EEPROMBlockProtectGet \ + ROM_EEPROMBlockProtectGet +#else +#define MAP_EEPROMBlockProtectGet \ + EEPROMBlockProtectGet +#endif +#ifdef ROM_EEPROMBlockProtectSet +#define MAP_EEPROMBlockProtectSet \ + ROM_EEPROMBlockProtectSet +#else +#define MAP_EEPROMBlockProtectSet \ + EEPROMBlockProtectSet +#endif +#ifdef ROM_EEPROMBlockUnlock +#define MAP_EEPROMBlockUnlock \ + ROM_EEPROMBlockUnlock +#else +#define MAP_EEPROMBlockUnlock \ + EEPROMBlockUnlock +#endif +#ifdef ROM_EEPROMIntClear +#define MAP_EEPROMIntClear \ + ROM_EEPROMIntClear +#else +#define MAP_EEPROMIntClear \ + EEPROMIntClear +#endif +#ifdef ROM_EEPROMIntDisable +#define MAP_EEPROMIntDisable \ + ROM_EEPROMIntDisable +#else +#define MAP_EEPROMIntDisable \ + EEPROMIntDisable +#endif +#ifdef ROM_EEPROMIntEnable +#define MAP_EEPROMIntEnable \ + ROM_EEPROMIntEnable +#else +#define MAP_EEPROMIntEnable \ + EEPROMIntEnable +#endif +#ifdef ROM_EEPROMIntStatus +#define MAP_EEPROMIntStatus \ + ROM_EEPROMIntStatus +#else +#define MAP_EEPROMIntStatus \ + EEPROMIntStatus +#endif +#ifdef ROM_EEPROMMassErase +#define MAP_EEPROMMassErase \ + ROM_EEPROMMassErase +#else +#define MAP_EEPROMMassErase \ + EEPROMMassErase +#endif +#ifdef ROM_EEPROMProgram +#define MAP_EEPROMProgram \ + ROM_EEPROMProgram +#else +#define MAP_EEPROMProgram \ + EEPROMProgram +#endif +#ifdef ROM_EEPROMProgramNonBlocking +#define MAP_EEPROMProgramNonBlocking \ + ROM_EEPROMProgramNonBlocking +#else +#define MAP_EEPROMProgramNonBlocking \ + EEPROMProgramNonBlocking +#endif +#ifdef ROM_EEPROMSizeGet +#define MAP_EEPROMSizeGet \ + ROM_EEPROMSizeGet +#else +#define MAP_EEPROMSizeGet \ + EEPROMSizeGet +#endif +#ifdef ROM_EEPROMStatusGet +#define MAP_EEPROMStatusGet \ + ROM_EEPROMStatusGet +#else +#define MAP_EEPROMStatusGet \ + EEPROMStatusGet +#endif +#ifdef ROM_EEPROMInit +#define MAP_EEPROMInit \ + ROM_EEPROMInit +#else +#define MAP_EEPROMInit \ + EEPROMInit +#endif + +//***************************************************************************** +// +// Macros for the EPI API. +// +//***************************************************************************** +#ifdef ROM_EPIIntStatus +#define MAP_EPIIntStatus \ + ROM_EPIIntStatus +#else +#define MAP_EPIIntStatus \ + EPIIntStatus +#endif +#ifdef ROM_EPIModeSet +#define MAP_EPIModeSet \ + ROM_EPIModeSet +#else +#define MAP_EPIModeSet \ + EPIModeSet +#endif +#ifdef ROM_EPIDividerSet +#define MAP_EPIDividerSet \ + ROM_EPIDividerSet +#else +#define MAP_EPIDividerSet \ + EPIDividerSet +#endif +#ifdef ROM_EPIConfigSDRAMSet +#define MAP_EPIConfigSDRAMSet \ + ROM_EPIConfigSDRAMSet +#else +#define MAP_EPIConfigSDRAMSet \ + EPIConfigSDRAMSet +#endif +#ifdef ROM_EPIConfigGPModeSet +#define MAP_EPIConfigGPModeSet \ + ROM_EPIConfigGPModeSet +#else +#define MAP_EPIConfigGPModeSet \ + EPIConfigGPModeSet +#endif +#ifdef ROM_EPIConfigHB8Set +#define MAP_EPIConfigHB8Set \ + ROM_EPIConfigHB8Set +#else +#define MAP_EPIConfigHB8Set \ + EPIConfigHB8Set +#endif +#ifdef ROM_EPIConfigHB16Set +#define MAP_EPIConfigHB16Set \ + ROM_EPIConfigHB16Set +#else +#define MAP_EPIConfigHB16Set \ + EPIConfigHB16Set +#endif +#ifdef ROM_EPIAddressMapSet +#define MAP_EPIAddressMapSet \ + ROM_EPIAddressMapSet +#else +#define MAP_EPIAddressMapSet \ + EPIAddressMapSet +#endif +#ifdef ROM_EPINonBlockingReadConfigure +#define MAP_EPINonBlockingReadConfigure \ + ROM_EPINonBlockingReadConfigure +#else +#define MAP_EPINonBlockingReadConfigure \ + EPINonBlockingReadConfigure +#endif +#ifdef ROM_EPINonBlockingReadStart +#define MAP_EPINonBlockingReadStart \ + ROM_EPINonBlockingReadStart +#else +#define MAP_EPINonBlockingReadStart \ + EPINonBlockingReadStart +#endif +#ifdef ROM_EPINonBlockingReadStop +#define MAP_EPINonBlockingReadStop \ + ROM_EPINonBlockingReadStop +#else +#define MAP_EPINonBlockingReadStop \ + EPINonBlockingReadStop +#endif +#ifdef ROM_EPINonBlockingReadCount +#define MAP_EPINonBlockingReadCount \ + ROM_EPINonBlockingReadCount +#else +#define MAP_EPINonBlockingReadCount \ + EPINonBlockingReadCount +#endif +#ifdef ROM_EPINonBlockingReadAvail +#define MAP_EPINonBlockingReadAvail \ + ROM_EPINonBlockingReadAvail +#else +#define MAP_EPINonBlockingReadAvail \ + EPINonBlockingReadAvail +#endif +#ifdef ROM_EPINonBlockingReadGet32 +#define MAP_EPINonBlockingReadGet32 \ + ROM_EPINonBlockingReadGet32 +#else +#define MAP_EPINonBlockingReadGet32 \ + EPINonBlockingReadGet32 +#endif +#ifdef ROM_EPINonBlockingReadGet16 +#define MAP_EPINonBlockingReadGet16 \ + ROM_EPINonBlockingReadGet16 +#else +#define MAP_EPINonBlockingReadGet16 \ + EPINonBlockingReadGet16 +#endif +#ifdef ROM_EPINonBlockingReadGet8 +#define MAP_EPINonBlockingReadGet8 \ + ROM_EPINonBlockingReadGet8 +#else +#define MAP_EPINonBlockingReadGet8 \ + EPINonBlockingReadGet8 +#endif +#ifdef ROM_EPIFIFOConfig +#define MAP_EPIFIFOConfig \ + ROM_EPIFIFOConfig +#else +#define MAP_EPIFIFOConfig \ + EPIFIFOConfig +#endif +#ifdef ROM_EPIWriteFIFOCountGet +#define MAP_EPIWriteFIFOCountGet \ + ROM_EPIWriteFIFOCountGet +#else +#define MAP_EPIWriteFIFOCountGet \ + EPIWriteFIFOCountGet +#endif +#ifdef ROM_EPIIntEnable +#define MAP_EPIIntEnable \ + ROM_EPIIntEnable +#else +#define MAP_EPIIntEnable \ + EPIIntEnable +#endif +#ifdef ROM_EPIIntDisable +#define MAP_EPIIntDisable \ + ROM_EPIIntDisable +#else +#define MAP_EPIIntDisable \ + EPIIntDisable +#endif +#ifdef ROM_EPIIntErrorStatus +#define MAP_EPIIntErrorStatus \ + ROM_EPIIntErrorStatus +#else +#define MAP_EPIIntErrorStatus \ + EPIIntErrorStatus +#endif +#ifdef ROM_EPIIntErrorClear +#define MAP_EPIIntErrorClear \ + ROM_EPIIntErrorClear +#else +#define MAP_EPIIntErrorClear \ + EPIIntErrorClear +#endif + +//***************************************************************************** +// +// Macros for the Ethernet API. +// +//***************************************************************************** +#ifdef ROM_EthernetIntClear +#define MAP_EthernetIntClear \ + ROM_EthernetIntClear +#else +#define MAP_EthernetIntClear \ + EthernetIntClear +#endif +#ifdef ROM_EthernetInitExpClk +#define MAP_EthernetInitExpClk \ + ROM_EthernetInitExpClk +#else +#define MAP_EthernetInitExpClk \ + EthernetInitExpClk +#endif +#ifdef ROM_EthernetConfigSet +#define MAP_EthernetConfigSet \ + ROM_EthernetConfigSet +#else +#define MAP_EthernetConfigSet \ + EthernetConfigSet +#endif +#ifdef ROM_EthernetConfigGet +#define MAP_EthernetConfigGet \ + ROM_EthernetConfigGet +#else +#define MAP_EthernetConfigGet \ + EthernetConfigGet +#endif +#ifdef ROM_EthernetMACAddrSet +#define MAP_EthernetMACAddrSet \ + ROM_EthernetMACAddrSet +#else +#define MAP_EthernetMACAddrSet \ + EthernetMACAddrSet +#endif +#ifdef ROM_EthernetMACAddrGet +#define MAP_EthernetMACAddrGet \ + ROM_EthernetMACAddrGet +#else +#define MAP_EthernetMACAddrGet \ + EthernetMACAddrGet +#endif +#ifdef ROM_EthernetEnable +#define MAP_EthernetEnable \ + ROM_EthernetEnable +#else +#define MAP_EthernetEnable \ + EthernetEnable +#endif +#ifdef ROM_EthernetDisable +#define MAP_EthernetDisable \ + ROM_EthernetDisable +#else +#define MAP_EthernetDisable \ + EthernetDisable +#endif +#ifdef ROM_EthernetPacketAvail +#define MAP_EthernetPacketAvail \ + ROM_EthernetPacketAvail +#else +#define MAP_EthernetPacketAvail \ + EthernetPacketAvail +#endif +#ifdef ROM_EthernetSpaceAvail +#define MAP_EthernetSpaceAvail \ + ROM_EthernetSpaceAvail +#else +#define MAP_EthernetSpaceAvail \ + EthernetSpaceAvail +#endif +#ifdef ROM_EthernetPacketGetNonBlocking +#define MAP_EthernetPacketGetNonBlocking \ + ROM_EthernetPacketGetNonBlocking +#else +#define MAP_EthernetPacketGetNonBlocking \ + EthernetPacketGetNonBlocking +#endif +#ifdef ROM_EthernetPacketGet +#define MAP_EthernetPacketGet \ + ROM_EthernetPacketGet +#else +#define MAP_EthernetPacketGet \ + EthernetPacketGet +#endif +#ifdef ROM_EthernetPacketPutNonBlocking +#define MAP_EthernetPacketPutNonBlocking \ + ROM_EthernetPacketPutNonBlocking +#else +#define MAP_EthernetPacketPutNonBlocking \ + EthernetPacketPutNonBlocking +#endif +#ifdef ROM_EthernetPacketPut +#define MAP_EthernetPacketPut \ + ROM_EthernetPacketPut +#else +#define MAP_EthernetPacketPut \ + EthernetPacketPut +#endif +#ifdef ROM_EthernetIntEnable +#define MAP_EthernetIntEnable \ + ROM_EthernetIntEnable +#else +#define MAP_EthernetIntEnable \ + EthernetIntEnable +#endif +#ifdef ROM_EthernetIntDisable +#define MAP_EthernetIntDisable \ + ROM_EthernetIntDisable +#else +#define MAP_EthernetIntDisable \ + EthernetIntDisable +#endif +#ifdef ROM_EthernetIntStatus +#define MAP_EthernetIntStatus \ + ROM_EthernetIntStatus +#else +#define MAP_EthernetIntStatus \ + EthernetIntStatus +#endif +#ifdef ROM_EthernetPHYWrite +#define MAP_EthernetPHYWrite \ + ROM_EthernetPHYWrite +#else +#define MAP_EthernetPHYWrite \ + EthernetPHYWrite +#endif +#ifdef ROM_EthernetPHYRead +#define MAP_EthernetPHYRead \ + ROM_EthernetPHYRead +#else +#define MAP_EthernetPHYRead \ + EthernetPHYRead +#endif +#ifdef ROM_EthernetPHYAddrSet +#define MAP_EthernetPHYAddrSet \ + ROM_EthernetPHYAddrSet +#else +#define MAP_EthernetPHYAddrSet \ + EthernetPHYAddrSet +#endif +#ifdef ROM_EthernetPHYPowerOff +#define MAP_EthernetPHYPowerOff \ + ROM_EthernetPHYPowerOff +#else +#define MAP_EthernetPHYPowerOff \ + EthernetPHYPowerOff +#endif +#ifdef ROM_EthernetPHYPowerOn +#define MAP_EthernetPHYPowerOn \ + ROM_EthernetPHYPowerOn +#else +#define MAP_EthernetPHYPowerOn \ + EthernetPHYPowerOn +#endif + +//***************************************************************************** +// +// Macros for the Fan API. +// +//***************************************************************************** +#ifdef ROM_FanIntClear +#define MAP_FanIntClear \ + ROM_FanIntClear +#else +#define MAP_FanIntClear \ + FanIntClear +#endif +#ifdef ROM_FanChannelConfigAuto +#define MAP_FanChannelConfigAuto \ + ROM_FanChannelConfigAuto +#else +#define MAP_FanChannelConfigAuto \ + FanChannelConfigAuto +#endif +#ifdef ROM_FanChannelConfigManual +#define MAP_FanChannelConfigManual \ + ROM_FanChannelConfigManual +#else +#define MAP_FanChannelConfigManual \ + FanChannelConfigManual +#endif +#ifdef ROM_FanChannelDisable +#define MAP_FanChannelDisable \ + ROM_FanChannelDisable +#else +#define MAP_FanChannelDisable \ + FanChannelDisable +#endif +#ifdef ROM_FanChannelDutyGet +#define MAP_FanChannelDutyGet \ + ROM_FanChannelDutyGet +#else +#define MAP_FanChannelDutyGet \ + FanChannelDutyGet +#endif +#ifdef ROM_FanChannelDutySet +#define MAP_FanChannelDutySet \ + ROM_FanChannelDutySet +#else +#define MAP_FanChannelDutySet \ + FanChannelDutySet +#endif +#ifdef ROM_FanChannelEnable +#define MAP_FanChannelEnable \ + ROM_FanChannelEnable +#else +#define MAP_FanChannelEnable \ + FanChannelEnable +#endif +#ifdef ROM_FanChannelRPMGet +#define MAP_FanChannelRPMGet \ + ROM_FanChannelRPMGet +#else +#define MAP_FanChannelRPMGet \ + FanChannelRPMGet +#endif +#ifdef ROM_FanChannelRPMSet +#define MAP_FanChannelRPMSet \ + ROM_FanChannelRPMSet +#else +#define MAP_FanChannelRPMSet \ + FanChannelRPMSet +#endif +#ifdef ROM_FanChannelStatus +#define MAP_FanChannelStatus \ + ROM_FanChannelStatus +#else +#define MAP_FanChannelStatus \ + FanChannelStatus +#endif +#ifdef ROM_FanChannelsGet +#define MAP_FanChannelsGet \ + ROM_FanChannelsGet +#else +#define MAP_FanChannelsGet \ + FanChannelsGet +#endif +#ifdef ROM_FanIntDisable +#define MAP_FanIntDisable \ + ROM_FanIntDisable +#else +#define MAP_FanIntDisable \ + FanIntDisable +#endif +#ifdef ROM_FanIntEnable +#define MAP_FanIntEnable \ + ROM_FanIntEnable +#else +#define MAP_FanIntEnable \ + FanIntEnable +#endif +#ifdef ROM_FanIntStatus +#define MAP_FanIntStatus \ + ROM_FanIntStatus +#else +#define MAP_FanIntStatus \ + FanIntStatus +#endif + +//***************************************************************************** +// +// Macros for the Flash API. +// +//***************************************************************************** +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashUsecGet +#define MAP_FlashUsecGet \ + ROM_FlashUsecGet +#else +#define MAP_FlashUsecGet \ + FlashUsecGet +#endif +#ifdef ROM_FlashUsecSet +#define MAP_FlashUsecSet \ + ROM_FlashUsecSet +#else +#define MAP_FlashUsecSet \ + FlashUsecSet +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif +#ifdef ROM_FlashProtectSet +#define MAP_FlashProtectSet \ + ROM_FlashProtectSet +#else +#define MAP_FlashProtectSet \ + FlashProtectSet +#endif +#ifdef ROM_FlashProtectSave +#define MAP_FlashProtectSave \ + ROM_FlashProtectSave +#else +#define MAP_FlashProtectSave \ + FlashProtectSave +#endif +#ifdef ROM_FlashUserGet +#define MAP_FlashUserGet \ + ROM_FlashUserGet +#else +#define MAP_FlashUserGet \ + FlashUserGet +#endif +#ifdef ROM_FlashUserSet +#define MAP_FlashUserSet \ + ROM_FlashUserSet +#else +#define MAP_FlashUserSet \ + FlashUserSet +#endif +#ifdef ROM_FlashUserSave +#define MAP_FlashUserSave \ + ROM_FlashUserSave +#else +#define MAP_FlashUserSave \ + FlashUserSave +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntStatus +#define MAP_FlashIntStatus \ + ROM_FlashIntStatus +#else +#define MAP_FlashIntStatus \ + FlashIntStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif + +//***************************************************************************** +// +// Macros for the FPU API. +// +//***************************************************************************** +#ifdef ROM_FPUEnable +#define MAP_FPUEnable \ + ROM_FPUEnable +#else +#define MAP_FPUEnable \ + FPUEnable +#endif +#ifdef ROM_FPUDisable +#define MAP_FPUDisable \ + ROM_FPUDisable +#else +#define MAP_FPUDisable \ + FPUDisable +#endif +#ifdef ROM_FPUFlushToZeroModeSet +#define MAP_FPUFlushToZeroModeSet \ + ROM_FPUFlushToZeroModeSet +#else +#define MAP_FPUFlushToZeroModeSet \ + FPUFlushToZeroModeSet +#endif +#ifdef ROM_FPUHalfPrecisionModeSet +#define MAP_FPUHalfPrecisionModeSet \ + ROM_FPUHalfPrecisionModeSet +#else +#define MAP_FPUHalfPrecisionModeSet \ + FPUHalfPrecisionModeSet +#endif +#ifdef ROM_FPULazyStackingEnable +#define MAP_FPULazyStackingEnable \ + ROM_FPULazyStackingEnable +#else +#define MAP_FPULazyStackingEnable \ + FPULazyStackingEnable +#endif +#ifdef ROM_FPUNaNModeSet +#define MAP_FPUNaNModeSet \ + ROM_FPUNaNModeSet +#else +#define MAP_FPUNaNModeSet \ + FPUNaNModeSet +#endif +#ifdef ROM_FPURoundingModeSet +#define MAP_FPURoundingModeSet \ + ROM_FPURoundingModeSet +#else +#define MAP_FPURoundingModeSet \ + FPURoundingModeSet +#endif +#ifdef ROM_FPUStackingDisable +#define MAP_FPUStackingDisable \ + ROM_FPUStackingDisable +#else +#define MAP_FPUStackingDisable \ + FPUStackingDisable +#endif +#ifdef ROM_FPUStackingEnable +#define MAP_FPUStackingEnable \ + ROM_FPUStackingEnable +#else +#define MAP_FPUStackingEnable \ + FPUStackingEnable +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOPadConfigSet +#define MAP_GPIOPadConfigSet \ + ROM_GPIOPadConfigSet +#else +#define MAP_GPIOPadConfigSet \ + GPIOPadConfigSet +#endif +#ifdef ROM_GPIOPadConfigGet +#define MAP_GPIOPadConfigGet \ + ROM_GPIOPadConfigGet +#else +#define MAP_GPIOPadConfigGet \ + GPIOPadConfigGet +#endif +#ifdef ROM_GPIOPinIntEnable +#define MAP_GPIOPinIntEnable \ + ROM_GPIOPinIntEnable +#else +#define MAP_GPIOPinIntEnable \ + GPIOPinIntEnable +#endif +#ifdef ROM_GPIOPinIntDisable +#define MAP_GPIOPinIntDisable \ + ROM_GPIOPinIntDisable +#else +#define MAP_GPIOPinIntDisable \ + GPIOPinIntDisable +#endif +#ifdef ROM_GPIOPinIntStatus +#define MAP_GPIOPinIntStatus \ + ROM_GPIOPinIntStatus +#else +#define MAP_GPIOPinIntStatus \ + GPIOPinIntStatus +#endif +#ifdef ROM_GPIOPinIntClear +#define MAP_GPIOPinIntClear \ + ROM_GPIOPinIntClear +#else +#define MAP_GPIOPinIntClear \ + GPIOPinIntClear +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinTypeCAN +#define MAP_GPIOPinTypeCAN \ + ROM_GPIOPinTypeCAN +#else +#define MAP_GPIOPinTypeCAN \ + GPIOPinTypeCAN +#endif +#ifdef ROM_GPIOPinTypeComparator +#define MAP_GPIOPinTypeComparator \ + ROM_GPIOPinTypeComparator +#else +#define MAP_GPIOPinTypeComparator \ + GPIOPinTypeComparator +#endif +#ifdef ROM_GPIOPinTypeGPIOInput +#define MAP_GPIOPinTypeGPIOInput \ + ROM_GPIOPinTypeGPIOInput +#else +#define MAP_GPIOPinTypeGPIOInput \ + GPIOPinTypeGPIOInput +#endif +#ifdef ROM_GPIOPinTypeGPIOOutput +#define MAP_GPIOPinTypeGPIOOutput \ + ROM_GPIOPinTypeGPIOOutput +#else +#define MAP_GPIOPinTypeGPIOOutput \ + GPIOPinTypeGPIOOutput +#endif +#ifdef ROM_GPIOPinTypeI2C +#define MAP_GPIOPinTypeI2C \ + ROM_GPIOPinTypeI2C +#else +#define MAP_GPIOPinTypeI2C \ + GPIOPinTypeI2C +#endif +#ifdef ROM_GPIOPinTypePWM +#define MAP_GPIOPinTypePWM \ + ROM_GPIOPinTypePWM +#else +#define MAP_GPIOPinTypePWM \ + GPIOPinTypePWM +#endif +#ifdef ROM_GPIOPinTypeQEI +#define MAP_GPIOPinTypeQEI \ + ROM_GPIOPinTypeQEI +#else +#define MAP_GPIOPinTypeQEI \ + GPIOPinTypeQEI +#endif +#ifdef ROM_GPIOPinTypeSSI +#define MAP_GPIOPinTypeSSI \ + ROM_GPIOPinTypeSSI +#else +#define MAP_GPIOPinTypeSSI \ + GPIOPinTypeSSI +#endif +#ifdef ROM_GPIOPinTypeTimer +#define MAP_GPIOPinTypeTimer \ + ROM_GPIOPinTypeTimer +#else +#define MAP_GPIOPinTypeTimer \ + GPIOPinTypeTimer +#endif +#ifdef ROM_GPIOPinTypeUART +#define MAP_GPIOPinTypeUART \ + ROM_GPIOPinTypeUART +#else +#define MAP_GPIOPinTypeUART \ + GPIOPinTypeUART +#endif +#ifdef ROM_GPIOPinTypeGPIOOutputOD +#define MAP_GPIOPinTypeGPIOOutputOD \ + ROM_GPIOPinTypeGPIOOutputOD +#else +#define MAP_GPIOPinTypeGPIOOutputOD \ + GPIOPinTypeGPIOOutputOD +#endif +#ifdef ROM_GPIOPinTypeADC +#define MAP_GPIOPinTypeADC \ + ROM_GPIOPinTypeADC +#else +#define MAP_GPIOPinTypeADC \ + GPIOPinTypeADC +#endif +#ifdef ROM_GPIOPinTypeUSBDigital +#define MAP_GPIOPinTypeUSBDigital \ + ROM_GPIOPinTypeUSBDigital +#else +#define MAP_GPIOPinTypeUSBDigital \ + GPIOPinTypeUSBDigital +#endif +#ifdef ROM_GPIOPinTypeI2S +#define MAP_GPIOPinTypeI2S \ + ROM_GPIOPinTypeI2S +#else +#define MAP_GPIOPinTypeI2S \ + GPIOPinTypeI2S +#endif +#ifdef ROM_GPIOPinConfigure +#define MAP_GPIOPinConfigure \ + ROM_GPIOPinConfigure +#else +#define MAP_GPIOPinConfigure \ + GPIOPinConfigure +#endif +#ifdef ROM_GPIOPinTypeEthernetLED +#define MAP_GPIOPinTypeEthernetLED \ + ROM_GPIOPinTypeEthernetLED +#else +#define MAP_GPIOPinTypeEthernetLED \ + GPIOPinTypeEthernetLED +#endif +#ifdef ROM_GPIOPinTypeUSBAnalog +#define MAP_GPIOPinTypeUSBAnalog \ + ROM_GPIOPinTypeUSBAnalog +#else +#define MAP_GPIOPinTypeUSBAnalog \ + GPIOPinTypeUSBAnalog +#endif +#ifdef ROM_GPIOPinTypeEPI +#define MAP_GPIOPinTypeEPI \ + ROM_GPIOPinTypeEPI +#else +#define MAP_GPIOPinTypeEPI \ + GPIOPinTypeEPI +#endif +#ifdef ROM_GPIOPinTypeEthernetMII +#define MAP_GPIOPinTypeEthernetMII \ + ROM_GPIOPinTypeEthernetMII +#else +#define MAP_GPIOPinTypeEthernetMII \ + GPIOPinTypeEthernetMII +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOADCTriggerEnable +#define MAP_GPIOADCTriggerEnable \ + ROM_GPIOADCTriggerEnable +#else +#define MAP_GPIOADCTriggerEnable \ + GPIOADCTriggerEnable +#endif +#ifdef ROM_GPIOADCTriggerDisable +#define MAP_GPIOADCTriggerDisable \ + ROM_GPIOADCTriggerDisable +#else +#define MAP_GPIOADCTriggerDisable \ + GPIOADCTriggerDisable +#endif +#ifdef ROM_GPIOPinTypeFan +#define MAP_GPIOPinTypeFan \ + ROM_GPIOPinTypeFan +#else +#define MAP_GPIOPinTypeFan \ + GPIOPinTypeFan +#endif +#ifdef ROM_GPIOPinTypeLPC +#define MAP_GPIOPinTypeLPC \ + ROM_GPIOPinTypeLPC +#else +#define MAP_GPIOPinTypeLPC \ + GPIOPinTypeLPC +#endif +#ifdef ROM_GPIOPinTypePECIRx +#define MAP_GPIOPinTypePECIRx \ + ROM_GPIOPinTypePECIRx +#else +#define MAP_GPIOPinTypePECIRx \ + GPIOPinTypePECIRx +#endif +#ifdef ROM_GPIOPinTypePECITx +#define MAP_GPIOPinTypePECITx \ + ROM_GPIOPinTypePECITx +#else +#define MAP_GPIOPinTypePECITx \ + GPIOPinTypePECITx +#endif +#ifdef ROM_GPIOPinTypeI2CSCL +#define MAP_GPIOPinTypeI2CSCL \ + ROM_GPIOPinTypeI2CSCL +#else +#define MAP_GPIOPinTypeI2CSCL \ + GPIOPinTypeI2CSCL +#endif + +//***************************************************************************** +// +// Macros for the Hibernate API. +// +//***************************************************************************** +#ifdef ROM_HibernateIntClear +#define MAP_HibernateIntClear \ + ROM_HibernateIntClear +#else +#define MAP_HibernateIntClear \ + HibernateIntClear +#endif +#ifdef ROM_HibernateEnableExpClk +#define MAP_HibernateEnableExpClk \ + ROM_HibernateEnableExpClk +#else +#define MAP_HibernateEnableExpClk \ + HibernateEnableExpClk +#endif +#ifdef ROM_HibernateDisable +#define MAP_HibernateDisable \ + ROM_HibernateDisable +#else +#define MAP_HibernateDisable \ + HibernateDisable +#endif +#ifdef ROM_HibernateClockSelect +#define MAP_HibernateClockSelect \ + ROM_HibernateClockSelect +#else +#define MAP_HibernateClockSelect \ + HibernateClockSelect +#endif +#ifdef ROM_HibernateRTCEnable +#define MAP_HibernateRTCEnable \ + ROM_HibernateRTCEnable +#else +#define MAP_HibernateRTCEnable \ + HibernateRTCEnable +#endif +#ifdef ROM_HibernateRTCDisable +#define MAP_HibernateRTCDisable \ + ROM_HibernateRTCDisable +#else +#define MAP_HibernateRTCDisable \ + HibernateRTCDisable +#endif +#ifdef ROM_HibernateWakeSet +#define MAP_HibernateWakeSet \ + ROM_HibernateWakeSet +#else +#define MAP_HibernateWakeSet \ + HibernateWakeSet +#endif +#ifdef ROM_HibernateWakeGet +#define MAP_HibernateWakeGet \ + ROM_HibernateWakeGet +#else +#define MAP_HibernateWakeGet \ + HibernateWakeGet +#endif +#ifdef ROM_HibernateLowBatSet +#define MAP_HibernateLowBatSet \ + ROM_HibernateLowBatSet +#else +#define MAP_HibernateLowBatSet \ + HibernateLowBatSet +#endif +#ifdef ROM_HibernateLowBatGet +#define MAP_HibernateLowBatGet \ + ROM_HibernateLowBatGet +#else +#define MAP_HibernateLowBatGet \ + HibernateLowBatGet +#endif +#ifdef ROM_HibernateRTCSet +#define MAP_HibernateRTCSet \ + ROM_HibernateRTCSet +#else +#define MAP_HibernateRTCSet \ + HibernateRTCSet +#endif +#ifdef ROM_HibernateRTCGet +#define MAP_HibernateRTCGet \ + ROM_HibernateRTCGet +#else +#define MAP_HibernateRTCGet \ + HibernateRTCGet +#endif +#ifdef ROM_HibernateRTCMatch0Set +#define MAP_HibernateRTCMatch0Set \ + ROM_HibernateRTCMatch0Set +#else +#define MAP_HibernateRTCMatch0Set \ + HibernateRTCMatch0Set +#endif +#ifdef ROM_HibernateRTCMatch0Get +#define MAP_HibernateRTCMatch0Get \ + ROM_HibernateRTCMatch0Get +#else +#define MAP_HibernateRTCMatch0Get \ + HibernateRTCMatch0Get +#endif +#ifdef ROM_HibernateRTCMatch1Set +#define MAP_HibernateRTCMatch1Set \ + ROM_HibernateRTCMatch1Set +#else +#define MAP_HibernateRTCMatch1Set \ + HibernateRTCMatch1Set +#endif +#ifdef ROM_HibernateRTCMatch1Get +#define MAP_HibernateRTCMatch1Get \ + ROM_HibernateRTCMatch1Get +#else +#define MAP_HibernateRTCMatch1Get \ + HibernateRTCMatch1Get +#endif +#ifdef ROM_HibernateRTCTrimSet +#define MAP_HibernateRTCTrimSet \ + ROM_HibernateRTCTrimSet +#else +#define MAP_HibernateRTCTrimSet \ + HibernateRTCTrimSet +#endif +#ifdef ROM_HibernateRTCTrimGet +#define MAP_HibernateRTCTrimGet \ + ROM_HibernateRTCTrimGet +#else +#define MAP_HibernateRTCTrimGet \ + HibernateRTCTrimGet +#endif +#ifdef ROM_HibernateDataSet +#define MAP_HibernateDataSet \ + ROM_HibernateDataSet +#else +#define MAP_HibernateDataSet \ + HibernateDataSet +#endif +#ifdef ROM_HibernateDataGet +#define MAP_HibernateDataGet \ + ROM_HibernateDataGet +#else +#define MAP_HibernateDataGet \ + HibernateDataGet +#endif +#ifdef ROM_HibernateRequest +#define MAP_HibernateRequest \ + ROM_HibernateRequest +#else +#define MAP_HibernateRequest \ + HibernateRequest +#endif +#ifdef ROM_HibernateIntEnable +#define MAP_HibernateIntEnable \ + ROM_HibernateIntEnable +#else +#define MAP_HibernateIntEnable \ + HibernateIntEnable +#endif +#ifdef ROM_HibernateIntDisable +#define MAP_HibernateIntDisable \ + ROM_HibernateIntDisable +#else +#define MAP_HibernateIntDisable \ + HibernateIntDisable +#endif +#ifdef ROM_HibernateIntStatus +#define MAP_HibernateIntStatus \ + ROM_HibernateIntStatus +#else +#define MAP_HibernateIntStatus \ + HibernateIntStatus +#endif +#ifdef ROM_HibernateIsActive +#define MAP_HibernateIsActive \ + ROM_HibernateIsActive +#else +#define MAP_HibernateIsActive \ + HibernateIsActive +#endif +#ifdef ROM_HibernateRTCSSMatch0Set +#define MAP_HibernateRTCSSMatch0Set \ + ROM_HibernateRTCSSMatch0Set +#else +#define MAP_HibernateRTCSSMatch0Set \ + HibernateRTCSSMatch0Set +#endif +#ifdef ROM_HibernateRTCSSMatch0Get +#define MAP_HibernateRTCSSMatch0Get \ + ROM_HibernateRTCSSMatch0Get +#else +#define MAP_HibernateRTCSSMatch0Get \ + HibernateRTCSSMatch0Get +#endif +#ifdef ROM_HibernateRTCSSGet +#define MAP_HibernateRTCSSGet \ + ROM_HibernateRTCSSGet +#else +#define MAP_HibernateRTCSSGet \ + HibernateRTCSSGet +#endif +#ifdef ROM_HibernateClockConfig +#define MAP_HibernateClockConfig \ + ROM_HibernateClockConfig +#else +#define MAP_HibernateClockConfig \ + HibernateClockConfig +#endif +#ifdef ROM_HibernateBatCheckStart +#define MAP_HibernateBatCheckStart \ + ROM_HibernateBatCheckStart +#else +#define MAP_HibernateBatCheckStart \ + HibernateBatCheckStart +#endif +#ifdef ROM_HibernateBatCheckDone +#define MAP_HibernateBatCheckDone \ + ROM_HibernateBatCheckDone +#else +#define MAP_HibernateBatCheckDone \ + HibernateBatCheckDone +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif +#ifdef ROM_I2CSlaveIntEnableEx +#define MAP_I2CSlaveIntEnableEx \ + ROM_I2CSlaveIntEnableEx +#else +#define MAP_I2CSlaveIntEnableEx \ + I2CSlaveIntEnableEx +#endif +#ifdef ROM_I2CSlaveIntDisableEx +#define MAP_I2CSlaveIntDisableEx \ + ROM_I2CSlaveIntDisableEx +#else +#define MAP_I2CSlaveIntDisableEx \ + I2CSlaveIntDisableEx +#endif +#ifdef ROM_I2CSlaveIntStatusEx +#define MAP_I2CSlaveIntStatusEx \ + ROM_I2CSlaveIntStatusEx +#else +#define MAP_I2CSlaveIntStatusEx \ + I2CSlaveIntStatusEx +#endif +#ifdef ROM_I2CSlaveIntClearEx +#define MAP_I2CSlaveIntClearEx \ + ROM_I2CSlaveIntClearEx +#else +#define MAP_I2CSlaveIntClearEx \ + I2CSlaveIntClearEx +#endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif + +//***************************************************************************** +// +// Macros for the I2S API. +// +//***************************************************************************** +#ifdef ROM_I2SIntStatus +#define MAP_I2SIntStatus \ + ROM_I2SIntStatus +#else +#define MAP_I2SIntStatus \ + I2SIntStatus +#endif +#ifdef ROM_I2STxEnable +#define MAP_I2STxEnable \ + ROM_I2STxEnable +#else +#define MAP_I2STxEnable \ + I2STxEnable +#endif +#ifdef ROM_I2STxDisable +#define MAP_I2STxDisable \ + ROM_I2STxDisable +#else +#define MAP_I2STxDisable \ + I2STxDisable +#endif +#ifdef ROM_I2STxDataPut +#define MAP_I2STxDataPut \ + ROM_I2STxDataPut +#else +#define MAP_I2STxDataPut \ + I2STxDataPut +#endif +#ifdef ROM_I2STxDataPutNonBlocking +#define MAP_I2STxDataPutNonBlocking \ + ROM_I2STxDataPutNonBlocking +#else +#define MAP_I2STxDataPutNonBlocking \ + I2STxDataPutNonBlocking +#endif +#ifdef ROM_I2STxConfigSet +#define MAP_I2STxConfigSet \ + ROM_I2STxConfigSet +#else +#define MAP_I2STxConfigSet \ + I2STxConfigSet +#endif +#ifdef ROM_I2STxFIFOLimitSet +#define MAP_I2STxFIFOLimitSet \ + ROM_I2STxFIFOLimitSet +#else +#define MAP_I2STxFIFOLimitSet \ + I2STxFIFOLimitSet +#endif +#ifdef ROM_I2STxFIFOLimitGet +#define MAP_I2STxFIFOLimitGet \ + ROM_I2STxFIFOLimitGet +#else +#define MAP_I2STxFIFOLimitGet \ + I2STxFIFOLimitGet +#endif +#ifdef ROM_I2STxFIFOLevelGet +#define MAP_I2STxFIFOLevelGet \ + ROM_I2STxFIFOLevelGet +#else +#define MAP_I2STxFIFOLevelGet \ + I2STxFIFOLevelGet +#endif +#ifdef ROM_I2SRxEnable +#define MAP_I2SRxEnable \ + ROM_I2SRxEnable +#else +#define MAP_I2SRxEnable \ + I2SRxEnable +#endif +#ifdef ROM_I2SRxDisable +#define MAP_I2SRxDisable \ + ROM_I2SRxDisable +#else +#define MAP_I2SRxDisable \ + I2SRxDisable +#endif +#ifdef ROM_I2SRxDataGet +#define MAP_I2SRxDataGet \ + ROM_I2SRxDataGet +#else +#define MAP_I2SRxDataGet \ + I2SRxDataGet +#endif +#ifdef ROM_I2SRxDataGetNonBlocking +#define MAP_I2SRxDataGetNonBlocking \ + ROM_I2SRxDataGetNonBlocking +#else +#define MAP_I2SRxDataGetNonBlocking \ + I2SRxDataGetNonBlocking +#endif +#ifdef ROM_I2SRxConfigSet +#define MAP_I2SRxConfigSet \ + ROM_I2SRxConfigSet +#else +#define MAP_I2SRxConfigSet \ + I2SRxConfigSet +#endif +#ifdef ROM_I2SRxFIFOLimitSet +#define MAP_I2SRxFIFOLimitSet \ + ROM_I2SRxFIFOLimitSet +#else +#define MAP_I2SRxFIFOLimitSet \ + I2SRxFIFOLimitSet +#endif +#ifdef ROM_I2SRxFIFOLimitGet +#define MAP_I2SRxFIFOLimitGet \ + ROM_I2SRxFIFOLimitGet +#else +#define MAP_I2SRxFIFOLimitGet \ + I2SRxFIFOLimitGet +#endif +#ifdef ROM_I2SRxFIFOLevelGet +#define MAP_I2SRxFIFOLevelGet \ + ROM_I2SRxFIFOLevelGet +#else +#define MAP_I2SRxFIFOLevelGet \ + I2SRxFIFOLevelGet +#endif +#ifdef ROM_I2STxRxEnable +#define MAP_I2STxRxEnable \ + ROM_I2STxRxEnable +#else +#define MAP_I2STxRxEnable \ + I2STxRxEnable +#endif +#ifdef ROM_I2STxRxDisable +#define MAP_I2STxRxDisable \ + ROM_I2STxRxDisable +#else +#define MAP_I2STxRxDisable \ + I2STxRxDisable +#endif +#ifdef ROM_I2STxRxConfigSet +#define MAP_I2STxRxConfigSet \ + ROM_I2STxRxConfigSet +#else +#define MAP_I2STxRxConfigSet \ + I2STxRxConfigSet +#endif +#ifdef ROM_I2SMasterClockSelect +#define MAP_I2SMasterClockSelect \ + ROM_I2SMasterClockSelect +#else +#define MAP_I2SMasterClockSelect \ + I2SMasterClockSelect +#endif +#ifdef ROM_I2SIntEnable +#define MAP_I2SIntEnable \ + ROM_I2SIntEnable +#else +#define MAP_I2SIntEnable \ + I2SIntEnable +#endif +#ifdef ROM_I2SIntDisable +#define MAP_I2SIntDisable \ + ROM_I2SIntDisable +#else +#define MAP_I2SIntDisable \ + I2SIntDisable +#endif +#ifdef ROM_I2SIntClear +#define MAP_I2SIntClear \ + ROM_I2SIntClear +#else +#define MAP_I2SIntClear \ + I2SIntClear +#endif + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif +#ifdef ROM_IntPendSet +#define MAP_IntPendSet \ + ROM_IntPendSet +#else +#define MAP_IntPendSet \ + IntPendSet +#endif +#ifdef ROM_IntPendClear +#define MAP_IntPendClear \ + ROM_IntPendClear +#else +#define MAP_IntPendClear \ + IntPendClear +#endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif + +//***************************************************************************** +// +// Macros for the LPC API. +// +//***************************************************************************** +#ifdef ROM_LPCIntClear +#define MAP_LPCIntClear \ + ROM_LPCIntClear +#else +#define MAP_LPCIntClear \ + LPCIntClear +#endif +#ifdef ROM_LPCByteRead +#define MAP_LPCByteRead \ + ROM_LPCByteRead +#else +#define MAP_LPCByteRead \ + LPCByteRead +#endif +#ifdef ROM_LPCByteWrite +#define MAP_LPCByteWrite \ + ROM_LPCByteWrite +#else +#define MAP_LPCByteWrite \ + LPCByteWrite +#endif +#ifdef ROM_LPCChannelConfigCOMxSet +#define MAP_LPCChannelConfigCOMxSet \ + ROM_LPCChannelConfigCOMxSet +#else +#define MAP_LPCChannelConfigCOMxSet \ + LPCChannelConfigCOMxSet +#endif +#ifdef ROM_LPCChannelConfigGet +#define MAP_LPCChannelConfigGet \ + ROM_LPCChannelConfigGet +#else +#define MAP_LPCChannelConfigGet \ + LPCChannelConfigGet +#endif +#ifdef ROM_LPCChannelConfigEPSet +#define MAP_LPCChannelConfigEPSet \ + ROM_LPCChannelConfigEPSet +#else +#define MAP_LPCChannelConfigEPSet \ + LPCChannelConfigEPSet +#endif +#ifdef ROM_LPCChannelConfigMBSet +#define MAP_LPCChannelConfigMBSet \ + ROM_LPCChannelConfigMBSet +#else +#define MAP_LPCChannelConfigMBSet \ + LPCChannelConfigMBSet +#endif +#ifdef ROM_LPCChannelDMAConfigGet +#define MAP_LPCChannelDMAConfigGet \ + ROM_LPCChannelDMAConfigGet +#else +#define MAP_LPCChannelDMAConfigGet \ + LPCChannelDMAConfigGet +#endif +#ifdef ROM_LPCChannelDMAConfigSet +#define MAP_LPCChannelDMAConfigSet \ + ROM_LPCChannelDMAConfigSet +#else +#define MAP_LPCChannelDMAConfigSet \ + LPCChannelDMAConfigSet +#endif +#ifdef ROM_LPCChannelDisable +#define MAP_LPCChannelDisable \ + ROM_LPCChannelDisable +#else +#define MAP_LPCChannelDisable \ + LPCChannelDisable +#endif +#ifdef ROM_LPCChannelEnable +#define MAP_LPCChannelEnable \ + ROM_LPCChannelEnable +#else +#define MAP_LPCChannelEnable \ + LPCChannelEnable +#endif +#ifdef ROM_LPCChannelStatusClear +#define MAP_LPCChannelStatusClear \ + ROM_LPCChannelStatusClear +#else +#define MAP_LPCChannelStatusClear \ + LPCChannelStatusClear +#endif +#ifdef ROM_LPCChannelStatusGet +#define MAP_LPCChannelStatusGet \ + ROM_LPCChannelStatusGet +#else +#define MAP_LPCChannelStatusGet \ + LPCChannelStatusGet +#endif +#ifdef ROM_LPCChannelStatusSet +#define MAP_LPCChannelStatusSet \ + ROM_LPCChannelStatusSet +#else +#define MAP_LPCChannelStatusSet \ + LPCChannelStatusSet +#endif +#ifdef ROM_LPCCOMxIntClear +#define MAP_LPCCOMxIntClear \ + ROM_LPCCOMxIntClear +#else +#define MAP_LPCCOMxIntClear \ + LPCCOMxIntClear +#endif +#ifdef ROM_LPCCOMxIntDisable +#define MAP_LPCCOMxIntDisable \ + ROM_LPCCOMxIntDisable +#else +#define MAP_LPCCOMxIntDisable \ + LPCCOMxIntDisable +#endif +#ifdef ROM_LPCCOMxIntEnable +#define MAP_LPCCOMxIntEnable \ + ROM_LPCCOMxIntEnable +#else +#define MAP_LPCCOMxIntEnable \ + LPCCOMxIntEnable +#endif +#ifdef ROM_LPCCOMxIntStatus +#define MAP_LPCCOMxIntStatus \ + ROM_LPCCOMxIntStatus +#else +#define MAP_LPCCOMxIntStatus \ + LPCCOMxIntStatus +#endif +#ifdef ROM_LPCConfigGet +#define MAP_LPCConfigGet \ + ROM_LPCConfigGet +#else +#define MAP_LPCConfigGet \ + LPCConfigGet +#endif +#ifdef ROM_LPCConfigSet +#define MAP_LPCConfigSet \ + ROM_LPCConfigSet +#else +#define MAP_LPCConfigSet \ + LPCConfigSet +#endif +#ifdef ROM_LPCHalfWordRead +#define MAP_LPCHalfWordRead \ + ROM_LPCHalfWordRead +#else +#define MAP_LPCHalfWordRead \ + LPCHalfWordRead +#endif +#ifdef ROM_LPCHalfWordWrite +#define MAP_LPCHalfWordWrite \ + ROM_LPCHalfWordWrite +#else +#define MAP_LPCHalfWordWrite \ + LPCHalfWordWrite +#endif +#ifdef ROM_LPCIRQClear +#define MAP_LPCIRQClear \ + ROM_LPCIRQClear +#else +#define MAP_LPCIRQClear \ + LPCIRQClear +#endif +#ifdef ROM_LPCIRQConfig +#define MAP_LPCIRQConfig \ + ROM_LPCIRQConfig +#else +#define MAP_LPCIRQConfig \ + LPCIRQConfig +#endif +#ifdef ROM_LPCIRQGet +#define MAP_LPCIRQGet \ + ROM_LPCIRQGet +#else +#define MAP_LPCIRQGet \ + LPCIRQGet +#endif +#ifdef ROM_LPCIRQSend +#define MAP_LPCIRQSend \ + ROM_LPCIRQSend +#else +#define MAP_LPCIRQSend \ + LPCIRQSend +#endif +#ifdef ROM_LPCIRQSet +#define MAP_LPCIRQSet \ + ROM_LPCIRQSet +#else +#define MAP_LPCIRQSet \ + LPCIRQSet +#endif +#ifdef ROM_LPCIntDisable +#define MAP_LPCIntDisable \ + ROM_LPCIntDisable +#else +#define MAP_LPCIntDisable \ + LPCIntDisable +#endif +#ifdef ROM_LPCIntEnable +#define MAP_LPCIntEnable \ + ROM_LPCIntEnable +#else +#define MAP_LPCIntEnable \ + LPCIntEnable +#endif +#ifdef ROM_LPCIntStatus +#define MAP_LPCIntStatus \ + ROM_LPCIntStatus +#else +#define MAP_LPCIntStatus \ + LPCIntStatus +#endif +#ifdef ROM_LPCSCIAssert +#define MAP_LPCSCIAssert \ + ROM_LPCSCIAssert +#else +#define MAP_LPCSCIAssert \ + LPCSCIAssert +#endif +#ifdef ROM_LPCStatusGet +#define MAP_LPCStatusGet \ + ROM_LPCStatusGet +#else +#define MAP_LPCStatusGet \ + LPCStatusGet +#endif +#ifdef ROM_LPCWordRead +#define MAP_LPCWordRead \ + ROM_LPCWordRead +#else +#define MAP_LPCWordRead \ + LPCWordRead +#endif +#ifdef ROM_LPCWordWrite +#define MAP_LPCWordWrite \ + ROM_LPCWordWrite +#else +#define MAP_LPCWordWrite \ + LPCWordWrite +#endif +#ifdef ROM_LPCChannelPoolAddressGet +#define MAP_LPCChannelPoolAddressGet \ + ROM_LPCChannelPoolAddressGet +#else +#define MAP_LPCChannelPoolAddressGet \ + LPCChannelPoolAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressGet +#define MAP_LPCStatusBlockAddressGet \ + ROM_LPCStatusBlockAddressGet +#else +#define MAP_LPCStatusBlockAddressGet \ + LPCStatusBlockAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressSet +#define MAP_LPCStatusBlockAddressSet \ + ROM_LPCStatusBlockAddressSet +#else +#define MAP_LPCStatusBlockAddressSet \ + LPCStatusBlockAddressSet +#endif + +//***************************************************************************** +// +// Macros for the MPU API. +// +//***************************************************************************** +#ifdef ROM_MPUEnable +#define MAP_MPUEnable \ + ROM_MPUEnable +#else +#define MAP_MPUEnable \ + MPUEnable +#endif +#ifdef ROM_MPUDisable +#define MAP_MPUDisable \ + ROM_MPUDisable +#else +#define MAP_MPUDisable \ + MPUDisable +#endif +#ifdef ROM_MPURegionCountGet +#define MAP_MPURegionCountGet \ + ROM_MPURegionCountGet +#else +#define MAP_MPURegionCountGet \ + MPURegionCountGet +#endif +#ifdef ROM_MPURegionEnable +#define MAP_MPURegionEnable \ + ROM_MPURegionEnable +#else +#define MAP_MPURegionEnable \ + MPURegionEnable +#endif +#ifdef ROM_MPURegionDisable +#define MAP_MPURegionDisable \ + ROM_MPURegionDisable +#else +#define MAP_MPURegionDisable \ + MPURegionDisable +#endif +#ifdef ROM_MPURegionSet +#define MAP_MPURegionSet \ + ROM_MPURegionSet +#else +#define MAP_MPURegionSet \ + MPURegionSet +#endif +#ifdef ROM_MPURegionGet +#define MAP_MPURegionGet \ + ROM_MPURegionGet +#else +#define MAP_MPURegionGet \ + MPURegionGet +#endif + +//***************************************************************************** +// +// Macros for the PECI API. +// +//***************************************************************************** +#ifdef ROM_PECIIntClear +#define MAP_PECIIntClear \ + ROM_PECIIntClear +#else +#define MAP_PECIIntClear \ + PECIIntClear +#endif +#ifdef ROM_PECIAdvCmdSend +#define MAP_PECIAdvCmdSend \ + ROM_PECIAdvCmdSend +#else +#define MAP_PECIAdvCmdSend \ + PECIAdvCmdSend +#endif +#ifdef ROM_PECIAdvCmdSendNonBlocking +#define MAP_PECIAdvCmdSendNonBlocking \ + ROM_PECIAdvCmdSendNonBlocking +#else +#define MAP_PECIAdvCmdSendNonBlocking \ + PECIAdvCmdSendNonBlocking +#endif +#ifdef ROM_PECIAdvCmdStatusGet +#define MAP_PECIAdvCmdStatusGet \ + ROM_PECIAdvCmdStatusGet +#else +#define MAP_PECIAdvCmdStatusGet \ + PECIAdvCmdStatusGet +#endif +#ifdef ROM_PECIConfigGet +#define MAP_PECIConfigGet \ + ROM_PECIConfigGet +#else +#define MAP_PECIConfigGet \ + PECIConfigGet +#endif +#ifdef ROM_PECIConfigSet +#define MAP_PECIConfigSet \ + ROM_PECIConfigSet +#else +#define MAP_PECIConfigSet \ + PECIConfigSet +#endif +#ifdef ROM_PECIDomainMaxReadClear +#define MAP_PECIDomainMaxReadClear \ + ROM_PECIDomainMaxReadClear +#else +#define MAP_PECIDomainMaxReadClear \ + PECIDomainMaxReadClear +#endif +#ifdef ROM_PECIDomainValueClear +#define MAP_PECIDomainValueClear \ + ROM_PECIDomainValueClear +#else +#define MAP_PECIDomainValueClear \ + PECIDomainValueClear +#endif +#ifdef ROM_PECIDomainConfigGet +#define MAP_PECIDomainConfigGet \ + ROM_PECIDomainConfigGet +#else +#define MAP_PECIDomainConfigGet \ + PECIDomainConfigGet +#endif +#ifdef ROM_PECIDomainConfigSet +#define MAP_PECIDomainConfigSet \ + ROM_PECIDomainConfigSet +#else +#define MAP_PECIDomainConfigSet \ + PECIDomainConfigSet +#endif +#ifdef ROM_PECIDomainDisable +#define MAP_PECIDomainDisable \ + ROM_PECIDomainDisable +#else +#define MAP_PECIDomainDisable \ + PECIDomainDisable +#endif +#ifdef ROM_PECIDomainEnable +#define MAP_PECIDomainEnable \ + ROM_PECIDomainEnable +#else +#define MAP_PECIDomainEnable \ + PECIDomainEnable +#endif +#ifdef ROM_PECIDomainMaxReadGet +#define MAP_PECIDomainMaxReadGet \ + ROM_PECIDomainMaxReadGet +#else +#define MAP_PECIDomainMaxReadGet \ + PECIDomainMaxReadGet +#endif +#ifdef ROM_PECIDomainValueGet +#define MAP_PECIDomainValueGet \ + ROM_PECIDomainValueGet +#else +#define MAP_PECIDomainValueGet \ + PECIDomainValueGet +#endif +#ifdef ROM_PECIIntDisable +#define MAP_PECIIntDisable \ + ROM_PECIIntDisable +#else +#define MAP_PECIIntDisable \ + PECIIntDisable +#endif +#ifdef ROM_PECIIntEnable +#define MAP_PECIIntEnable \ + ROM_PECIIntEnable +#else +#define MAP_PECIIntEnable \ + PECIIntEnable +#endif +#ifdef ROM_PECIIntStatus +#define MAP_PECIIntStatus \ + ROM_PECIIntStatus +#else +#define MAP_PECIIntStatus \ + PECIIntStatus +#endif +#ifdef ROM_PECIBypassEnable +#define MAP_PECIBypassEnable \ + ROM_PECIBypassEnable +#else +#define MAP_PECIBypassEnable \ + PECIBypassEnable +#endif +#ifdef ROM_PECIBypassDisable +#define MAP_PECIBypassDisable \ + ROM_PECIBypassDisable +#else +#define MAP_PECIBypassDisable \ + PECIBypassDisable +#endif + +//***************************************************************************** +// +// Macros for the PWM API. +// +//***************************************************************************** +#ifdef ROM_PWMPulseWidthSet +#define MAP_PWMPulseWidthSet \ + ROM_PWMPulseWidthSet +#else +#define MAP_PWMPulseWidthSet \ + PWMPulseWidthSet +#endif +#ifdef ROM_PWMGenConfigure +#define MAP_PWMGenConfigure \ + ROM_PWMGenConfigure +#else +#define MAP_PWMGenConfigure \ + PWMGenConfigure +#endif +#ifdef ROM_PWMGenPeriodSet +#define MAP_PWMGenPeriodSet \ + ROM_PWMGenPeriodSet +#else +#define MAP_PWMGenPeriodSet \ + PWMGenPeriodSet +#endif +#ifdef ROM_PWMGenPeriodGet +#define MAP_PWMGenPeriodGet \ + ROM_PWMGenPeriodGet +#else +#define MAP_PWMGenPeriodGet \ + PWMGenPeriodGet +#endif +#ifdef ROM_PWMGenEnable +#define MAP_PWMGenEnable \ + ROM_PWMGenEnable +#else +#define MAP_PWMGenEnable \ + PWMGenEnable +#endif +#ifdef ROM_PWMGenDisable +#define MAP_PWMGenDisable \ + ROM_PWMGenDisable +#else +#define MAP_PWMGenDisable \ + PWMGenDisable +#endif +#ifdef ROM_PWMPulseWidthGet +#define MAP_PWMPulseWidthGet \ + ROM_PWMPulseWidthGet +#else +#define MAP_PWMPulseWidthGet \ + PWMPulseWidthGet +#endif +#ifdef ROM_PWMDeadBandEnable +#define MAP_PWMDeadBandEnable \ + ROM_PWMDeadBandEnable +#else +#define MAP_PWMDeadBandEnable \ + PWMDeadBandEnable +#endif +#ifdef ROM_PWMDeadBandDisable +#define MAP_PWMDeadBandDisable \ + ROM_PWMDeadBandDisable +#else +#define MAP_PWMDeadBandDisable \ + PWMDeadBandDisable +#endif +#ifdef ROM_PWMSyncUpdate +#define MAP_PWMSyncUpdate \ + ROM_PWMSyncUpdate +#else +#define MAP_PWMSyncUpdate \ + PWMSyncUpdate +#endif +#ifdef ROM_PWMSyncTimeBase +#define MAP_PWMSyncTimeBase \ + ROM_PWMSyncTimeBase +#else +#define MAP_PWMSyncTimeBase \ + PWMSyncTimeBase +#endif +#ifdef ROM_PWMOutputState +#define MAP_PWMOutputState \ + ROM_PWMOutputState +#else +#define MAP_PWMOutputState \ + PWMOutputState +#endif +#ifdef ROM_PWMOutputInvert +#define MAP_PWMOutputInvert \ + ROM_PWMOutputInvert +#else +#define MAP_PWMOutputInvert \ + PWMOutputInvert +#endif +#ifdef ROM_PWMOutputFault +#define MAP_PWMOutputFault \ + ROM_PWMOutputFault +#else +#define MAP_PWMOutputFault \ + PWMOutputFault +#endif +#ifdef ROM_PWMGenIntTrigEnable +#define MAP_PWMGenIntTrigEnable \ + ROM_PWMGenIntTrigEnable +#else +#define MAP_PWMGenIntTrigEnable \ + PWMGenIntTrigEnable +#endif +#ifdef ROM_PWMGenIntTrigDisable +#define MAP_PWMGenIntTrigDisable \ + ROM_PWMGenIntTrigDisable +#else +#define MAP_PWMGenIntTrigDisable \ + PWMGenIntTrigDisable +#endif +#ifdef ROM_PWMGenIntStatus +#define MAP_PWMGenIntStatus \ + ROM_PWMGenIntStatus +#else +#define MAP_PWMGenIntStatus \ + PWMGenIntStatus +#endif +#ifdef ROM_PWMGenIntClear +#define MAP_PWMGenIntClear \ + ROM_PWMGenIntClear +#else +#define MAP_PWMGenIntClear \ + PWMGenIntClear +#endif +#ifdef ROM_PWMIntEnable +#define MAP_PWMIntEnable \ + ROM_PWMIntEnable +#else +#define MAP_PWMIntEnable \ + PWMIntEnable +#endif +#ifdef ROM_PWMIntDisable +#define MAP_PWMIntDisable \ + ROM_PWMIntDisable +#else +#define MAP_PWMIntDisable \ + PWMIntDisable +#endif +#ifdef ROM_PWMFaultIntClear +#define MAP_PWMFaultIntClear \ + ROM_PWMFaultIntClear +#else +#define MAP_PWMFaultIntClear \ + PWMFaultIntClear +#endif +#ifdef ROM_PWMIntStatus +#define MAP_PWMIntStatus \ + ROM_PWMIntStatus +#else +#define MAP_PWMIntStatus \ + PWMIntStatus +#endif +#ifdef ROM_PWMOutputFaultLevel +#define MAP_PWMOutputFaultLevel \ + ROM_PWMOutputFaultLevel +#else +#define MAP_PWMOutputFaultLevel \ + PWMOutputFaultLevel +#endif +#ifdef ROM_PWMFaultIntClearExt +#define MAP_PWMFaultIntClearExt \ + ROM_PWMFaultIntClearExt +#else +#define MAP_PWMFaultIntClearExt \ + PWMFaultIntClearExt +#endif +#ifdef ROM_PWMGenFaultConfigure +#define MAP_PWMGenFaultConfigure \ + ROM_PWMGenFaultConfigure +#else +#define MAP_PWMGenFaultConfigure \ + PWMGenFaultConfigure +#endif +#ifdef ROM_PWMGenFaultTriggerSet +#define MAP_PWMGenFaultTriggerSet \ + ROM_PWMGenFaultTriggerSet +#else +#define MAP_PWMGenFaultTriggerSet \ + PWMGenFaultTriggerSet +#endif +#ifdef ROM_PWMGenFaultTriggerGet +#define MAP_PWMGenFaultTriggerGet \ + ROM_PWMGenFaultTriggerGet +#else +#define MAP_PWMGenFaultTriggerGet \ + PWMGenFaultTriggerGet +#endif +#ifdef ROM_PWMGenFaultStatus +#define MAP_PWMGenFaultStatus \ + ROM_PWMGenFaultStatus +#else +#define MAP_PWMGenFaultStatus \ + PWMGenFaultStatus +#endif +#ifdef ROM_PWMGenFaultClear +#define MAP_PWMGenFaultClear \ + ROM_PWMGenFaultClear +#else +#define MAP_PWMGenFaultClear \ + PWMGenFaultClear +#endif + +//***************************************************************************** +// +// Macros for the QEI API. +// +//***************************************************************************** +#ifdef ROM_QEIPositionGet +#define MAP_QEIPositionGet \ + ROM_QEIPositionGet +#else +#define MAP_QEIPositionGet \ + QEIPositionGet +#endif +#ifdef ROM_QEIEnable +#define MAP_QEIEnable \ + ROM_QEIEnable +#else +#define MAP_QEIEnable \ + QEIEnable +#endif +#ifdef ROM_QEIDisable +#define MAP_QEIDisable \ + ROM_QEIDisable +#else +#define MAP_QEIDisable \ + QEIDisable +#endif +#ifdef ROM_QEIConfigure +#define MAP_QEIConfigure \ + ROM_QEIConfigure +#else +#define MAP_QEIConfigure \ + QEIConfigure +#endif +#ifdef ROM_QEIPositionSet +#define MAP_QEIPositionSet \ + ROM_QEIPositionSet +#else +#define MAP_QEIPositionSet \ + QEIPositionSet +#endif +#ifdef ROM_QEIDirectionGet +#define MAP_QEIDirectionGet \ + ROM_QEIDirectionGet +#else +#define MAP_QEIDirectionGet \ + QEIDirectionGet +#endif +#ifdef ROM_QEIErrorGet +#define MAP_QEIErrorGet \ + ROM_QEIErrorGet +#else +#define MAP_QEIErrorGet \ + QEIErrorGet +#endif +#ifdef ROM_QEIVelocityEnable +#define MAP_QEIVelocityEnable \ + ROM_QEIVelocityEnable +#else +#define MAP_QEIVelocityEnable \ + QEIVelocityEnable +#endif +#ifdef ROM_QEIVelocityDisable +#define MAP_QEIVelocityDisable \ + ROM_QEIVelocityDisable +#else +#define MAP_QEIVelocityDisable \ + QEIVelocityDisable +#endif +#ifdef ROM_QEIVelocityConfigure +#define MAP_QEIVelocityConfigure \ + ROM_QEIVelocityConfigure +#else +#define MAP_QEIVelocityConfigure \ + QEIVelocityConfigure +#endif +#ifdef ROM_QEIVelocityGet +#define MAP_QEIVelocityGet \ + ROM_QEIVelocityGet +#else +#define MAP_QEIVelocityGet \ + QEIVelocityGet +#endif +#ifdef ROM_QEIIntEnable +#define MAP_QEIIntEnable \ + ROM_QEIIntEnable +#else +#define MAP_QEIIntEnable \ + QEIIntEnable +#endif +#ifdef ROM_QEIIntDisable +#define MAP_QEIIntDisable \ + ROM_QEIIntDisable +#else +#define MAP_QEIIntDisable \ + QEIIntDisable +#endif +#ifdef ROM_QEIIntStatus +#define MAP_QEIIntStatus \ + ROM_QEIIntStatus +#else +#define MAP_QEIIntStatus \ + QEIIntStatus +#endif +#ifdef ROM_QEIIntClear +#define MAP_QEIIntClear \ + ROM_QEIIntClear +#else +#define MAP_QEIIntClear \ + QEIIntClear +#endif + +//***************************************************************************** +// +// Macros for the SMBus API. +// +//***************************************************************************** +#ifdef ROM_SMBusMasterIntProcess +#define MAP_SMBusMasterIntProcess \ + ROM_SMBusMasterIntProcess +#else +#define MAP_SMBusMasterIntProcess \ + SMBusMasterIntProcess +#endif +#ifdef ROM_SMBusARPDisable +#define MAP_SMBusARPDisable \ + ROM_SMBusARPDisable +#else +#define MAP_SMBusARPDisable \ + SMBusARPDisable +#endif +#ifdef ROM_SMBusARPEnable +#define MAP_SMBusARPEnable \ + ROM_SMBusARPEnable +#else +#define MAP_SMBusARPEnable \ + SMBusARPEnable +#endif +#ifdef ROM_SMBusARPUDIDPacketDecode +#define MAP_SMBusARPUDIDPacketDecode \ + ROM_SMBusARPUDIDPacketDecode +#else +#define MAP_SMBusARPUDIDPacketDecode \ + SMBusARPUDIDPacketDecode +#endif +#ifdef ROM_SMBusARPUDIDPacketEncode +#define MAP_SMBusARPUDIDPacketEncode \ + ROM_SMBusARPUDIDPacketEncode +#else +#define MAP_SMBusARPUDIDPacketEncode \ + SMBusARPUDIDPacketEncode +#endif +#ifdef ROM_SMBusMasterARPAssignAddress +#define MAP_SMBusMasterARPAssignAddress \ + ROM_SMBusMasterARPAssignAddress +#else +#define MAP_SMBusMasterARPAssignAddress \ + SMBusMasterARPAssignAddress +#endif +#ifdef ROM_SMBusMasterARPGetUDIDDir +#define MAP_SMBusMasterARPGetUDIDDir \ + ROM_SMBusMasterARPGetUDIDDir +#else +#define MAP_SMBusMasterARPGetUDIDDir \ + SMBusMasterARPGetUDIDDir +#endif +#ifdef ROM_SMBusMasterARPGetUDIDGen +#define MAP_SMBusMasterARPGetUDIDGen \ + ROM_SMBusMasterARPGetUDIDGen +#else +#define MAP_SMBusMasterARPGetUDIDGen \ + SMBusMasterARPGetUDIDGen +#endif +#ifdef ROM_SMBusMasterARPNotifyMaster +#define MAP_SMBusMasterARPNotifyMaster \ + ROM_SMBusMasterARPNotifyMaster +#else +#define MAP_SMBusMasterARPNotifyMaster \ + SMBusMasterARPNotifyMaster +#endif +#ifdef ROM_SMBusMasterARPPrepareToARP +#define MAP_SMBusMasterARPPrepareToARP \ + ROM_SMBusMasterARPPrepareToARP +#else +#define MAP_SMBusMasterARPPrepareToARP \ + SMBusMasterARPPrepareToARP +#endif +#ifdef ROM_SMBusMasterARPResetDeviceDir +#define MAP_SMBusMasterARPResetDeviceDir \ + ROM_SMBusMasterARPResetDeviceDir +#else +#define MAP_SMBusMasterARPResetDeviceDir \ + SMBusMasterARPResetDeviceDir +#endif +#ifdef ROM_SMBusMasterARPResetDeviceGen +#define MAP_SMBusMasterARPResetDeviceGen \ + ROM_SMBusMasterARPResetDeviceGen +#else +#define MAP_SMBusMasterARPResetDeviceGen \ + SMBusMasterARPResetDeviceGen +#endif +#ifdef ROM_SMBusMasterBlockProcessCall +#define MAP_SMBusMasterBlockProcessCall \ + ROM_SMBusMasterBlockProcessCall +#else +#define MAP_SMBusMasterBlockProcessCall \ + SMBusMasterBlockProcessCall +#endif +#ifdef ROM_SMBusMasterBlockRead +#define MAP_SMBusMasterBlockRead \ + ROM_SMBusMasterBlockRead +#else +#define MAP_SMBusMasterBlockRead \ + SMBusMasterBlockRead +#endif +#ifdef ROM_SMBusMasterBlockWrite +#define MAP_SMBusMasterBlockWrite \ + ROM_SMBusMasterBlockWrite +#else +#define MAP_SMBusMasterBlockWrite \ + SMBusMasterBlockWrite +#endif +#ifdef ROM_SMBusMasterByteReceive +#define MAP_SMBusMasterByteReceive \ + ROM_SMBusMasterByteReceive +#else +#define MAP_SMBusMasterByteReceive \ + SMBusMasterByteReceive +#endif +#ifdef ROM_SMBusMasterByteSend +#define MAP_SMBusMasterByteSend \ + ROM_SMBusMasterByteSend +#else +#define MAP_SMBusMasterByteSend \ + SMBusMasterByteSend +#endif +#ifdef ROM_SMBusMasterByteWordRead +#define MAP_SMBusMasterByteWordRead \ + ROM_SMBusMasterByteWordRead +#else +#define MAP_SMBusMasterByteWordRead \ + SMBusMasterByteWordRead +#endif +#ifdef ROM_SMBusMasterByteWordWrite +#define MAP_SMBusMasterByteWordWrite \ + ROM_SMBusMasterByteWordWrite +#else +#define MAP_SMBusMasterByteWordWrite \ + SMBusMasterByteWordWrite +#endif +#ifdef ROM_SMBusMasterHostNotify +#define MAP_SMBusMasterHostNotify \ + ROM_SMBusMasterHostNotify +#else +#define MAP_SMBusMasterHostNotify \ + SMBusMasterHostNotify +#endif +#ifdef ROM_SMBusMasterI2CRead +#define MAP_SMBusMasterI2CRead \ + ROM_SMBusMasterI2CRead +#else +#define MAP_SMBusMasterI2CRead \ + SMBusMasterI2CRead +#endif +#ifdef ROM_SMBusMasterI2CWrite +#define MAP_SMBusMasterI2CWrite \ + ROM_SMBusMasterI2CWrite +#else +#define MAP_SMBusMasterI2CWrite \ + SMBusMasterI2CWrite +#endif +#ifdef ROM_SMBusMasterI2CWriteRead +#define MAP_SMBusMasterI2CWriteRead \ + ROM_SMBusMasterI2CWriteRead +#else +#define MAP_SMBusMasterI2CWriteRead \ + SMBusMasterI2CWriteRead +#endif +#ifdef ROM_SMBusMasterInit +#define MAP_SMBusMasterInit \ + ROM_SMBusMasterInit +#else +#define MAP_SMBusMasterInit \ + SMBusMasterInit +#endif +#ifdef ROM_SMBusMasterIntEnable +#define MAP_SMBusMasterIntEnable \ + ROM_SMBusMasterIntEnable +#else +#define MAP_SMBusMasterIntEnable \ + SMBusMasterIntEnable +#endif +#ifdef ROM_SMBusMasterProcessCall +#define MAP_SMBusMasterProcessCall \ + ROM_SMBusMasterProcessCall +#else +#define MAP_SMBusMasterProcessCall \ + SMBusMasterProcessCall +#endif +#ifdef ROM_SMBusMasterQuickCommand +#define MAP_SMBusMasterQuickCommand \ + ROM_SMBusMasterQuickCommand +#else +#define MAP_SMBusMasterQuickCommand \ + SMBusMasterQuickCommand +#endif +#ifdef ROM_SMBusPECDisable +#define MAP_SMBusPECDisable \ + ROM_SMBusPECDisable +#else +#define MAP_SMBusPECDisable \ + SMBusPECDisable +#endif +#ifdef ROM_SMBusPECEnable +#define MAP_SMBusPECEnable \ + ROM_SMBusPECEnable +#else +#define MAP_SMBusPECEnable \ + SMBusPECEnable +#endif +#ifdef ROM_SMBusRxPacketSizeGet +#define MAP_SMBusRxPacketSizeGet \ + ROM_SMBusRxPacketSizeGet +#else +#define MAP_SMBusRxPacketSizeGet \ + SMBusRxPacketSizeGet +#endif +#ifdef ROM_SMBusSlaveACKSend +#define MAP_SMBusSlaveACKSend \ + ROM_SMBusSlaveACKSend +#else +#define MAP_SMBusSlaveACKSend \ + SMBusSlaveACKSend +#endif +#ifdef ROM_SMBusSlaveAddressSet +#define MAP_SMBusSlaveAddressSet \ + ROM_SMBusSlaveAddressSet +#else +#define MAP_SMBusSlaveAddressSet \ + SMBusSlaveAddressSet +#endif +#ifdef ROM_SMBusSlaveARPFlagARGet +#define MAP_SMBusSlaveARPFlagARGet \ + ROM_SMBusSlaveARPFlagARGet +#else +#define MAP_SMBusSlaveARPFlagARGet \ + SMBusSlaveARPFlagARGet +#endif +#ifdef ROM_SMBusSlaveARPFlagARSet +#define MAP_SMBusSlaveARPFlagARSet \ + ROM_SMBusSlaveARPFlagARSet +#else +#define MAP_SMBusSlaveARPFlagARSet \ + SMBusSlaveARPFlagARSet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVGet +#define MAP_SMBusSlaveARPFlagAVGet \ + ROM_SMBusSlaveARPFlagAVGet +#else +#define MAP_SMBusSlaveARPFlagAVGet \ + SMBusSlaveARPFlagAVGet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVSet +#define MAP_SMBusSlaveARPFlagAVSet \ + ROM_SMBusSlaveARPFlagAVSet +#else +#define MAP_SMBusSlaveARPFlagAVSet \ + SMBusSlaveARPFlagAVSet +#endif +#ifdef ROM_SMBusSlaveBlockTransferDisable +#define MAP_SMBusSlaveBlockTransferDisable \ + ROM_SMBusSlaveBlockTransferDisable +#else +#define MAP_SMBusSlaveBlockTransferDisable \ + SMBusSlaveBlockTransferDisable +#endif +#ifdef ROM_SMBusSlaveBlockTransferEnable +#define MAP_SMBusSlaveBlockTransferEnable \ + ROM_SMBusSlaveBlockTransferEnable +#else +#define MAP_SMBusSlaveBlockTransferEnable \ + SMBusSlaveBlockTransferEnable +#endif +#ifdef ROM_SMBusSlaveCommandGet +#define MAP_SMBusSlaveCommandGet \ + ROM_SMBusSlaveCommandGet +#else +#define MAP_SMBusSlaveCommandGet \ + SMBusSlaveCommandGet +#endif +#ifdef ROM_SMBusSlaveI2CDisable +#define MAP_SMBusSlaveI2CDisable \ + ROM_SMBusSlaveI2CDisable +#else +#define MAP_SMBusSlaveI2CDisable \ + SMBusSlaveI2CDisable +#endif +#ifdef ROM_SMBusSlaveI2CEnable +#define MAP_SMBusSlaveI2CEnable \ + ROM_SMBusSlaveI2CEnable +#else +#define MAP_SMBusSlaveI2CEnable \ + SMBusSlaveI2CEnable +#endif +#ifdef ROM_SMBusSlaveInit +#define MAP_SMBusSlaveInit \ + ROM_SMBusSlaveInit +#else +#define MAP_SMBusSlaveInit \ + SMBusSlaveInit +#endif +#ifdef ROM_SMBusSlaveIntAddressGet +#define MAP_SMBusSlaveIntAddressGet \ + ROM_SMBusSlaveIntAddressGet +#else +#define MAP_SMBusSlaveIntAddressGet \ + SMBusSlaveIntAddressGet +#endif +#ifdef ROM_SMBusSlaveIntEnable +#define MAP_SMBusSlaveIntEnable \ + ROM_SMBusSlaveIntEnable +#else +#define MAP_SMBusSlaveIntEnable \ + SMBusSlaveIntEnable +#endif +#ifdef ROM_SMBusSlaveIntProcess +#define MAP_SMBusSlaveIntProcess \ + ROM_SMBusSlaveIntProcess +#else +#define MAP_SMBusSlaveIntProcess \ + SMBusSlaveIntProcess +#endif +#ifdef ROM_SMBusSlaveManualACKDisable +#define MAP_SMBusSlaveManualACKDisable \ + ROM_SMBusSlaveManualACKDisable +#else +#define MAP_SMBusSlaveManualACKDisable \ + SMBusSlaveManualACKDisable +#endif +#ifdef ROM_SMBusSlaveManualACKEnable +#define MAP_SMBusSlaveManualACKEnable \ + ROM_SMBusSlaveManualACKEnable +#else +#define MAP_SMBusSlaveManualACKEnable \ + SMBusSlaveManualACKEnable +#endif +#ifdef ROM_SMBusSlaveManualACKStatusGet +#define MAP_SMBusSlaveManualACKStatusGet \ + ROM_SMBusSlaveManualACKStatusGet +#else +#define MAP_SMBusSlaveManualACKStatusGet \ + SMBusSlaveManualACKStatusGet +#endif +#ifdef ROM_SMBusSlaveProcessCallDisable +#define MAP_SMBusSlaveProcessCallDisable \ + ROM_SMBusSlaveProcessCallDisable +#else +#define MAP_SMBusSlaveProcessCallDisable \ + SMBusSlaveProcessCallDisable +#endif +#ifdef ROM_SMBusSlaveProcessCallEnable +#define MAP_SMBusSlaveProcessCallEnable \ + ROM_SMBusSlaveProcessCallEnable +#else +#define MAP_SMBusSlaveProcessCallEnable \ + SMBusSlaveProcessCallEnable +#endif +#ifdef ROM_SMBusSlaveRxBufferSet +#define MAP_SMBusSlaveRxBufferSet \ + ROM_SMBusSlaveRxBufferSet +#else +#define MAP_SMBusSlaveRxBufferSet \ + SMBusSlaveRxBufferSet +#endif +#ifdef ROM_SMBusSlaveTransferInit +#define MAP_SMBusSlaveTransferInit \ + ROM_SMBusSlaveTransferInit +#else +#define MAP_SMBusSlaveTransferInit \ + SMBusSlaveTransferInit +#endif +#ifdef ROM_SMBusSlaveTxBufferSet +#define MAP_SMBusSlaveTxBufferSet \ + ROM_SMBusSlaveTxBufferSet +#else +#define MAP_SMBusSlaveTxBufferSet \ + SMBusSlaveTxBufferSet +#endif +#ifdef ROM_SMBusSlaveUDIDSet +#define MAP_SMBusSlaveUDIDSet \ + ROM_SMBusSlaveUDIDSet +#else +#define MAP_SMBusSlaveUDIDSet \ + SMBusSlaveUDIDSet +#endif +#ifdef ROM_SMBusStatusGet +#define MAP_SMBusStatusGet \ + ROM_SMBusStatusGet +#else +#define MAP_SMBusStatusGet \ + SMBusStatusGet +#endif +#ifdef ROM_SMBusSlaveDataSend +#define MAP_SMBusSlaveDataSend \ + ROM_SMBusSlaveDataSend +#else +#define MAP_SMBusSlaveDataSend \ + SMBusSlaveDataSend +#endif + +//***************************************************************************** +// +// Macros for the SSI API. +// +//***************************************************************************** +#ifdef ROM_SSIDataPut +#define MAP_SSIDataPut \ + ROM_SSIDataPut +#else +#define MAP_SSIDataPut \ + SSIDataPut +#endif +#ifdef ROM_SSIConfigSetExpClk +#define MAP_SSIConfigSetExpClk \ + ROM_SSIConfigSetExpClk +#else +#define MAP_SSIConfigSetExpClk \ + SSIConfigSetExpClk +#endif +#ifdef ROM_SSIEnable +#define MAP_SSIEnable \ + ROM_SSIEnable +#else +#define MAP_SSIEnable \ + SSIEnable +#endif +#ifdef ROM_SSIDisable +#define MAP_SSIDisable \ + ROM_SSIDisable +#else +#define MAP_SSIDisable \ + SSIDisable +#endif +#ifdef ROM_SSIIntEnable +#define MAP_SSIIntEnable \ + ROM_SSIIntEnable +#else +#define MAP_SSIIntEnable \ + SSIIntEnable +#endif +#ifdef ROM_SSIIntDisable +#define MAP_SSIIntDisable \ + ROM_SSIIntDisable +#else +#define MAP_SSIIntDisable \ + SSIIntDisable +#endif +#ifdef ROM_SSIIntStatus +#define MAP_SSIIntStatus \ + ROM_SSIIntStatus +#else +#define MAP_SSIIntStatus \ + SSIIntStatus +#endif +#ifdef ROM_SSIIntClear +#define MAP_SSIIntClear \ + ROM_SSIIntClear +#else +#define MAP_SSIIntClear \ + SSIIntClear +#endif +#ifdef ROM_SSIDataPutNonBlocking +#define MAP_SSIDataPutNonBlocking \ + ROM_SSIDataPutNonBlocking +#else +#define MAP_SSIDataPutNonBlocking \ + SSIDataPutNonBlocking +#endif +#ifdef ROM_SSIDataGet +#define MAP_SSIDataGet \ + ROM_SSIDataGet +#else +#define MAP_SSIDataGet \ + SSIDataGet +#endif +#ifdef ROM_SSIDataGetNonBlocking +#define MAP_SSIDataGetNonBlocking \ + ROM_SSIDataGetNonBlocking +#else +#define MAP_SSIDataGetNonBlocking \ + SSIDataGetNonBlocking +#endif +#ifdef ROM_SSIDMAEnable +#define MAP_SSIDMAEnable \ + ROM_SSIDMAEnable +#else +#define MAP_SSIDMAEnable \ + SSIDMAEnable +#endif +#ifdef ROM_SSIDMADisable +#define MAP_SSIDMADisable \ + ROM_SSIDMADisable +#else +#define MAP_SSIDMADisable \ + SSIDMADisable +#endif +#ifdef ROM_SSIBusy +#define MAP_SSIBusy \ + ROM_SSIBusy +#else +#define MAP_SSIBusy \ + SSIBusy +#endif +#ifdef ROM_SSIClockSourceGet +#define MAP_SSIClockSourceGet \ + ROM_SSIClockSourceGet +#else +#define MAP_SSIClockSourceGet \ + SSIClockSourceGet +#endif +#ifdef ROM_SSIClockSourceSet +#define MAP_SSIClockSourceSet \ + ROM_SSIClockSourceSet +#else +#define MAP_SSIClockSourceSet \ + SSIClockSourceSet +#endif + +//***************************************************************************** +// +// Macros for the SysCtl API. +// +//***************************************************************************** +#ifdef ROM_SysCtlSleep +#define MAP_SysCtlSleep \ + ROM_SysCtlSleep +#else +#define MAP_SysCtlSleep \ + SysCtlSleep +#endif +#ifdef ROM_SysCtlSRAMSizeGet +#define MAP_SysCtlSRAMSizeGet \ + ROM_SysCtlSRAMSizeGet +#else +#define MAP_SysCtlSRAMSizeGet \ + SysCtlSRAMSizeGet +#endif +#ifdef ROM_SysCtlFlashSizeGet +#define MAP_SysCtlFlashSizeGet \ + ROM_SysCtlFlashSizeGet +#else +#define MAP_SysCtlFlashSizeGet \ + SysCtlFlashSizeGet +#endif +#ifdef ROM_SysCtlPinPresent +#define MAP_SysCtlPinPresent \ + ROM_SysCtlPinPresent +#else +#define MAP_SysCtlPinPresent \ + SysCtlPinPresent +#endif +#ifdef ROM_SysCtlPeripheralPresent +#define MAP_SysCtlPeripheralPresent \ + ROM_SysCtlPeripheralPresent +#else +#define MAP_SysCtlPeripheralPresent \ + SysCtlPeripheralPresent +#endif +#ifdef ROM_SysCtlPeripheralReset +#define MAP_SysCtlPeripheralReset \ + ROM_SysCtlPeripheralReset +#else +#define MAP_SysCtlPeripheralReset \ + SysCtlPeripheralReset +#endif +#ifdef ROM_SysCtlPeripheralEnable +#define MAP_SysCtlPeripheralEnable \ + ROM_SysCtlPeripheralEnable +#else +#define MAP_SysCtlPeripheralEnable \ + SysCtlPeripheralEnable +#endif +#ifdef ROM_SysCtlPeripheralDisable +#define MAP_SysCtlPeripheralDisable \ + ROM_SysCtlPeripheralDisable +#else +#define MAP_SysCtlPeripheralDisable \ + SysCtlPeripheralDisable +#endif +#ifdef ROM_SysCtlPeripheralSleepEnable +#define MAP_SysCtlPeripheralSleepEnable \ + ROM_SysCtlPeripheralSleepEnable +#else +#define MAP_SysCtlPeripheralSleepEnable \ + SysCtlPeripheralSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralSleepDisable +#define MAP_SysCtlPeripheralSleepDisable \ + ROM_SysCtlPeripheralSleepDisable +#else +#define MAP_SysCtlPeripheralSleepDisable \ + SysCtlPeripheralSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepEnable +#define MAP_SysCtlPeripheralDeepSleepEnable \ + ROM_SysCtlPeripheralDeepSleepEnable +#else +#define MAP_SysCtlPeripheralDeepSleepEnable \ + SysCtlPeripheralDeepSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepDisable +#define MAP_SysCtlPeripheralDeepSleepDisable \ + ROM_SysCtlPeripheralDeepSleepDisable +#else +#define MAP_SysCtlPeripheralDeepSleepDisable \ + SysCtlPeripheralDeepSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralClockGating +#define MAP_SysCtlPeripheralClockGating \ + ROM_SysCtlPeripheralClockGating +#else +#define MAP_SysCtlPeripheralClockGating \ + SysCtlPeripheralClockGating +#endif +#ifdef ROM_SysCtlIntEnable +#define MAP_SysCtlIntEnable \ + ROM_SysCtlIntEnable +#else +#define MAP_SysCtlIntEnable \ + SysCtlIntEnable +#endif +#ifdef ROM_SysCtlIntDisable +#define MAP_SysCtlIntDisable \ + ROM_SysCtlIntDisable +#else +#define MAP_SysCtlIntDisable \ + SysCtlIntDisable +#endif +#ifdef ROM_SysCtlIntClear +#define MAP_SysCtlIntClear \ + ROM_SysCtlIntClear +#else +#define MAP_SysCtlIntClear \ + SysCtlIntClear +#endif +#ifdef ROM_SysCtlIntStatus +#define MAP_SysCtlIntStatus \ + ROM_SysCtlIntStatus +#else +#define MAP_SysCtlIntStatus \ + SysCtlIntStatus +#endif +#ifdef ROM_SysCtlLDOSet +#define MAP_SysCtlLDOSet \ + ROM_SysCtlLDOSet +#else +#define MAP_SysCtlLDOSet \ + SysCtlLDOSet +#endif +#ifdef ROM_SysCtlLDOGet +#define MAP_SysCtlLDOGet \ + ROM_SysCtlLDOGet +#else +#define MAP_SysCtlLDOGet \ + SysCtlLDOGet +#endif +#ifdef ROM_SysCtlReset +#define MAP_SysCtlReset \ + ROM_SysCtlReset +#else +#define MAP_SysCtlReset \ + SysCtlReset +#endif +#ifdef ROM_SysCtlDeepSleep +#define MAP_SysCtlDeepSleep \ + ROM_SysCtlDeepSleep +#else +#define MAP_SysCtlDeepSleep \ + SysCtlDeepSleep +#endif +#ifdef ROM_SysCtlResetCauseGet +#define MAP_SysCtlResetCauseGet \ + ROM_SysCtlResetCauseGet +#else +#define MAP_SysCtlResetCauseGet \ + SysCtlResetCauseGet +#endif +#ifdef ROM_SysCtlResetCauseClear +#define MAP_SysCtlResetCauseClear \ + ROM_SysCtlResetCauseClear +#else +#define MAP_SysCtlResetCauseClear \ + SysCtlResetCauseClear +#endif +#ifdef ROM_SysCtlClockSet +#define MAP_SysCtlClockSet \ + ROM_SysCtlClockSet +#else +#define MAP_SysCtlClockSet \ + SysCtlClockSet +#endif +#ifdef ROM_SysCtlClockGet +#define MAP_SysCtlClockGet \ + ROM_SysCtlClockGet +#else +#define MAP_SysCtlClockGet \ + SysCtlClockGet +#endif +#ifdef ROM_SysCtlPWMClockSet +#define MAP_SysCtlPWMClockSet \ + ROM_SysCtlPWMClockSet +#else +#define MAP_SysCtlPWMClockSet \ + SysCtlPWMClockSet +#endif +#ifdef ROM_SysCtlPWMClockGet +#define MAP_SysCtlPWMClockGet \ + ROM_SysCtlPWMClockGet +#else +#define MAP_SysCtlPWMClockGet \ + SysCtlPWMClockGet +#endif +#ifdef ROM_SysCtlADCSpeedSet +#define MAP_SysCtlADCSpeedSet \ + ROM_SysCtlADCSpeedSet +#else +#define MAP_SysCtlADCSpeedSet \ + SysCtlADCSpeedSet +#endif +#ifdef ROM_SysCtlADCSpeedGet +#define MAP_SysCtlADCSpeedGet \ + ROM_SysCtlADCSpeedGet +#else +#define MAP_SysCtlADCSpeedGet \ + SysCtlADCSpeedGet +#endif +#ifdef ROM_SysCtlGPIOAHBEnable +#define MAP_SysCtlGPIOAHBEnable \ + ROM_SysCtlGPIOAHBEnable +#else +#define MAP_SysCtlGPIOAHBEnable \ + SysCtlGPIOAHBEnable +#endif +#ifdef ROM_SysCtlGPIOAHBDisable +#define MAP_SysCtlGPIOAHBDisable \ + ROM_SysCtlGPIOAHBDisable +#else +#define MAP_SysCtlGPIOAHBDisable \ + SysCtlGPIOAHBDisable +#endif +#ifdef ROM_SysCtlUSBPLLEnable +#define MAP_SysCtlUSBPLLEnable \ + ROM_SysCtlUSBPLLEnable +#else +#define MAP_SysCtlUSBPLLEnable \ + SysCtlUSBPLLEnable +#endif +#ifdef ROM_SysCtlUSBPLLDisable +#define MAP_SysCtlUSBPLLDisable \ + ROM_SysCtlUSBPLLDisable +#else +#define MAP_SysCtlUSBPLLDisable \ + SysCtlUSBPLLDisable +#endif +#ifdef ROM_SysCtlI2SMClkSet +#define MAP_SysCtlI2SMClkSet \ + ROM_SysCtlI2SMClkSet +#else +#define MAP_SysCtlI2SMClkSet \ + SysCtlI2SMClkSet +#endif +#ifdef ROM_SysCtlDelay +#define MAP_SysCtlDelay \ + ROM_SysCtlDelay +#else +#define MAP_SysCtlDelay \ + SysCtlDelay +#endif +#ifdef ROM_SysCtlPeripheralReady +#define MAP_SysCtlPeripheralReady \ + ROM_SysCtlPeripheralReady +#else +#define MAP_SysCtlPeripheralReady \ + SysCtlPeripheralReady +#endif +#ifdef ROM_SysCtlPeripheralPowerOn +#define MAP_SysCtlPeripheralPowerOn \ + ROM_SysCtlPeripheralPowerOn +#else +#define MAP_SysCtlPeripheralPowerOn \ + SysCtlPeripheralPowerOn +#endif +#ifdef ROM_SysCtlPeripheralPowerOff +#define MAP_SysCtlPeripheralPowerOff \ + ROM_SysCtlPeripheralPowerOff +#else +#define MAP_SysCtlPeripheralPowerOff \ + SysCtlPeripheralPowerOff +#endif +#ifdef ROM_SysCtlMOSCConfigSet +#define MAP_SysCtlMOSCConfigSet \ + ROM_SysCtlMOSCConfigSet +#else +#define MAP_SysCtlMOSCConfigSet \ + SysCtlMOSCConfigSet +#endif +#ifdef ROM_SysCtlPIOSCCalibrate +#define MAP_SysCtlPIOSCCalibrate \ + ROM_SysCtlPIOSCCalibrate +#else +#define MAP_SysCtlPIOSCCalibrate \ + SysCtlPIOSCCalibrate +#endif +#ifdef ROM_SysCtlDeepSleepClockSet +#define MAP_SysCtlDeepSleepClockSet \ + ROM_SysCtlDeepSleepClockSet +#else +#define MAP_SysCtlDeepSleepClockSet \ + SysCtlDeepSleepClockSet +#endif + +//***************************************************************************** +// +// Macros for the SysExc API. +// +//***************************************************************************** +#ifdef ROM_SysExcIntStatus +#define MAP_SysExcIntStatus \ + ROM_SysExcIntStatus +#else +#define MAP_SysExcIntStatus \ + SysExcIntStatus +#endif +#ifdef ROM_SysExcIntClear +#define MAP_SysExcIntClear \ + ROM_SysExcIntClear +#else +#define MAP_SysExcIntClear \ + SysExcIntClear +#endif +#ifdef ROM_SysExcIntDisable +#define MAP_SysExcIntDisable \ + ROM_SysExcIntDisable +#else +#define MAP_SysExcIntDisable \ + SysExcIntDisable +#endif +#ifdef ROM_SysExcIntEnable +#define MAP_SysExcIntEnable \ + ROM_SysExcIntEnable +#else +#define MAP_SysExcIntEnable \ + SysExcIntEnable +#endif + +//***************************************************************************** +// +// Macros for the SysTick API. +// +//***************************************************************************** +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlTrigger +#define MAP_TimerControlTrigger \ + ROM_TimerControlTrigger +#else +#define MAP_TimerControlTrigger \ + TimerControlTrigger +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerRTCEnable +#define MAP_TimerRTCEnable \ + ROM_TimerRTCEnable +#else +#define MAP_TimerRTCEnable \ + TimerRTCEnable +#endif +#ifdef ROM_TimerRTCDisable +#define MAP_TimerRTCDisable \ + ROM_TimerRTCDisable +#else +#define MAP_TimerRTCDisable \ + TimerRTCDisable +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif +#ifdef ROM_TimerControlWaitOnTrigger +#define MAP_TimerControlWaitOnTrigger \ + ROM_TimerControlWaitOnTrigger +#else +#define MAP_TimerControlWaitOnTrigger \ + TimerControlWaitOnTrigger +#endif +#ifdef ROM_TimerLoadSet64 +#define MAP_TimerLoadSet64 \ + ROM_TimerLoadSet64 +#else +#define MAP_TimerLoadSet64 \ + TimerLoadSet64 +#endif +#ifdef ROM_TimerLoadGet64 +#define MAP_TimerLoadGet64 \ + ROM_TimerLoadGet64 +#else +#define MAP_TimerLoadGet64 \ + TimerLoadGet64 +#endif +#ifdef ROM_TimerValueGet64 +#define MAP_TimerValueGet64 \ + ROM_TimerValueGet64 +#else +#define MAP_TimerValueGet64 \ + TimerValueGet64 +#endif +#ifdef ROM_TimerMatchSet64 +#define MAP_TimerMatchSet64 \ + ROM_TimerMatchSet64 +#else +#define MAP_TimerMatchSet64 \ + TimerMatchSet64 +#endif +#ifdef ROM_TimerMatchGet64 +#define MAP_TimerMatchGet64 \ + ROM_TimerMatchGet64 +#else +#define MAP_TimerMatchGet64 \ + TimerMatchGet64 +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTEnableSIR +#define MAP_UARTEnableSIR \ + ROM_UARTEnableSIR +#else +#define MAP_UARTEnableSIR \ + UARTEnableSIR +#endif +#ifdef ROM_UARTDisableSIR +#define MAP_UARTDisableSIR \ + ROM_UARTDisableSIR +#else +#define MAP_UARTDisableSIR \ + UARTDisableSIR +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif +#ifdef ROM_UARTFIFOEnable +#define MAP_UARTFIFOEnable \ + ROM_UARTFIFOEnable +#else +#define MAP_UARTFIFOEnable \ + UARTFIFOEnable +#endif +#ifdef ROM_UARTFIFODisable +#define MAP_UARTFIFODisable \ + ROM_UARTFIFODisable +#else +#define MAP_UARTFIFODisable \ + UARTFIFODisable +#endif +#ifdef ROM_UARTBusy +#define MAP_UARTBusy \ + ROM_UARTBusy +#else +#define MAP_UARTBusy \ + UARTBusy +#endif +#ifdef ROM_UARTTxIntModeSet +#define MAP_UARTTxIntModeSet \ + ROM_UARTTxIntModeSet +#else +#define MAP_UARTTxIntModeSet \ + UARTTxIntModeSet +#endif +#ifdef ROM_UARTTxIntModeGet +#define MAP_UARTTxIntModeGet \ + ROM_UARTTxIntModeGet +#else +#define MAP_UARTTxIntModeGet \ + UARTTxIntModeGet +#endif +#ifdef ROM_UARTRxErrorGet +#define MAP_UARTRxErrorGet \ + ROM_UARTRxErrorGet +#else +#define MAP_UARTRxErrorGet \ + UARTRxErrorGet +#endif +#ifdef ROM_UARTRxErrorClear +#define MAP_UARTRxErrorClear \ + ROM_UARTRxErrorClear +#else +#define MAP_UARTRxErrorClear \ + UARTRxErrorClear +#endif +#ifdef ROM_UARTClockSourceSet +#define MAP_UARTClockSourceSet \ + ROM_UARTClockSourceSet +#else +#define MAP_UARTClockSourceSet \ + UARTClockSourceSet +#endif +#ifdef ROM_UARTClockSourceGet +#define MAP_UARTClockSourceGet \ + ROM_UARTClockSourceGet +#else +#define MAP_UARTClockSourceGet \ + UARTClockSourceGet +#endif +#ifdef ROM_UART9BitEnable +#define MAP_UART9BitEnable \ + ROM_UART9BitEnable +#else +#define MAP_UART9BitEnable \ + UART9BitEnable +#endif +#ifdef ROM_UART9BitDisable +#define MAP_UART9BitDisable \ + ROM_UART9BitDisable +#else +#define MAP_UART9BitDisable \ + UART9BitDisable +#endif +#ifdef ROM_UART9BitAddrSet +#define MAP_UART9BitAddrSet \ + ROM_UART9BitAddrSet +#else +#define MAP_UART9BitAddrSet \ + UART9BitAddrSet +#endif +#ifdef ROM_UART9BitAddrSend +#define MAP_UART9BitAddrSend \ + ROM_UART9BitAddrSend +#else +#define MAP_UART9BitAddrSend \ + UART9BitAddrSend +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif +#ifdef ROM_uDMAChannelSelectSecondary +#define MAP_uDMAChannelSelectSecondary \ + ROM_uDMAChannelSelectSecondary +#else +#define MAP_uDMAChannelSelectSecondary \ + uDMAChannelSelectSecondary +#endif +#ifdef ROM_uDMAChannelSelectDefault +#define MAP_uDMAChannelSelectDefault \ + ROM_uDMAChannelSelectDefault +#else +#define MAP_uDMAChannelSelectDefault \ + uDMAChannelSelectDefault +#endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif + +//***************************************************************************** +// +// Macros for the USB API. +// +//***************************************************************************** +#ifdef ROM_USBIntStatus +#define MAP_USBIntStatus \ + ROM_USBIntStatus +#else +#define MAP_USBIntStatus \ + USBIntStatus +#endif +#ifdef ROM_USBDevAddrGet +#define MAP_USBDevAddrGet \ + ROM_USBDevAddrGet +#else +#define MAP_USBDevAddrGet \ + USBDevAddrGet +#endif +#ifdef ROM_USBDevAddrSet +#define MAP_USBDevAddrSet \ + ROM_USBDevAddrSet +#else +#define MAP_USBDevAddrSet \ + USBDevAddrSet +#endif +#ifdef ROM_USBDevConnect +#define MAP_USBDevConnect \ + ROM_USBDevConnect +#else +#define MAP_USBDevConnect \ + USBDevConnect +#endif +#ifdef ROM_USBDevDisconnect +#define MAP_USBDevDisconnect \ + ROM_USBDevDisconnect +#else +#define MAP_USBDevDisconnect \ + USBDevDisconnect +#endif +#ifdef ROM_USBDevEndpointConfigSet +#define MAP_USBDevEndpointConfigSet \ + ROM_USBDevEndpointConfigSet +#else +#define MAP_USBDevEndpointConfigSet \ + USBDevEndpointConfigSet +#endif +#ifdef ROM_USBDevEndpointDataAck +#define MAP_USBDevEndpointDataAck \ + ROM_USBDevEndpointDataAck +#else +#define MAP_USBDevEndpointDataAck \ + USBDevEndpointDataAck +#endif +#ifdef ROM_USBDevEndpointStall +#define MAP_USBDevEndpointStall \ + ROM_USBDevEndpointStall +#else +#define MAP_USBDevEndpointStall \ + USBDevEndpointStall +#endif +#ifdef ROM_USBDevEndpointStallClear +#define MAP_USBDevEndpointStallClear \ + ROM_USBDevEndpointStallClear +#else +#define MAP_USBDevEndpointStallClear \ + USBDevEndpointStallClear +#endif +#ifdef ROM_USBDevEndpointStatusClear +#define MAP_USBDevEndpointStatusClear \ + ROM_USBDevEndpointStatusClear +#else +#define MAP_USBDevEndpointStatusClear \ + USBDevEndpointStatusClear +#endif +#ifdef ROM_USBEndpointDataGet +#define MAP_USBEndpointDataGet \ + ROM_USBEndpointDataGet +#else +#define MAP_USBEndpointDataGet \ + USBEndpointDataGet +#endif +#ifdef ROM_USBEndpointDataPut +#define MAP_USBEndpointDataPut \ + ROM_USBEndpointDataPut +#else +#define MAP_USBEndpointDataPut \ + USBEndpointDataPut +#endif +#ifdef ROM_USBEndpointDataSend +#define MAP_USBEndpointDataSend \ + ROM_USBEndpointDataSend +#else +#define MAP_USBEndpointDataSend \ + USBEndpointDataSend +#endif +#ifdef ROM_USBEndpointDataToggleClear +#define MAP_USBEndpointDataToggleClear \ + ROM_USBEndpointDataToggleClear +#else +#define MAP_USBEndpointDataToggleClear \ + USBEndpointDataToggleClear +#endif +#ifdef ROM_USBEndpointStatus +#define MAP_USBEndpointStatus \ + ROM_USBEndpointStatus +#else +#define MAP_USBEndpointStatus \ + USBEndpointStatus +#endif +#ifdef ROM_USBFIFOAddrGet +#define MAP_USBFIFOAddrGet \ + ROM_USBFIFOAddrGet +#else +#define MAP_USBFIFOAddrGet \ + USBFIFOAddrGet +#endif +#ifdef ROM_USBFIFOConfigGet +#define MAP_USBFIFOConfigGet \ + ROM_USBFIFOConfigGet +#else +#define MAP_USBFIFOConfigGet \ + USBFIFOConfigGet +#endif +#ifdef ROM_USBFIFOConfigSet +#define MAP_USBFIFOConfigSet \ + ROM_USBFIFOConfigSet +#else +#define MAP_USBFIFOConfigSet \ + USBFIFOConfigSet +#endif +#ifdef ROM_USBFIFOFlush +#define MAP_USBFIFOFlush \ + ROM_USBFIFOFlush +#else +#define MAP_USBFIFOFlush \ + USBFIFOFlush +#endif +#ifdef ROM_USBFrameNumberGet +#define MAP_USBFrameNumberGet \ + ROM_USBFrameNumberGet +#else +#define MAP_USBFrameNumberGet \ + USBFrameNumberGet +#endif +#ifdef ROM_USBHostAddrGet +#define MAP_USBHostAddrGet \ + ROM_USBHostAddrGet +#else +#define MAP_USBHostAddrGet \ + USBHostAddrGet +#endif +#ifdef ROM_USBHostAddrSet +#define MAP_USBHostAddrSet \ + ROM_USBHostAddrSet +#else +#define MAP_USBHostAddrSet \ + USBHostAddrSet +#endif +#ifdef ROM_USBHostEndpointConfig +#define MAP_USBHostEndpointConfig \ + ROM_USBHostEndpointConfig +#else +#define MAP_USBHostEndpointConfig \ + USBHostEndpointConfig +#endif +#ifdef ROM_USBHostEndpointDataAck +#define MAP_USBHostEndpointDataAck \ + ROM_USBHostEndpointDataAck +#else +#define MAP_USBHostEndpointDataAck \ + USBHostEndpointDataAck +#endif +#ifdef ROM_USBHostEndpointDataToggle +#define MAP_USBHostEndpointDataToggle \ + ROM_USBHostEndpointDataToggle +#else +#define MAP_USBHostEndpointDataToggle \ + USBHostEndpointDataToggle +#endif +#ifdef ROM_USBHostEndpointStatusClear +#define MAP_USBHostEndpointStatusClear \ + ROM_USBHostEndpointStatusClear +#else +#define MAP_USBHostEndpointStatusClear \ + USBHostEndpointStatusClear +#endif +#ifdef ROM_USBHostHubAddrGet +#define MAP_USBHostHubAddrGet \ + ROM_USBHostHubAddrGet +#else +#define MAP_USBHostHubAddrGet \ + USBHostHubAddrGet +#endif +#ifdef ROM_USBHostHubAddrSet +#define MAP_USBHostHubAddrSet \ + ROM_USBHostHubAddrSet +#else +#define MAP_USBHostHubAddrSet \ + USBHostHubAddrSet +#endif +#ifdef ROM_USBHostPwrDisable +#define MAP_USBHostPwrDisable \ + ROM_USBHostPwrDisable +#else +#define MAP_USBHostPwrDisable \ + USBHostPwrDisable +#endif +#ifdef ROM_USBHostPwrEnable +#define MAP_USBHostPwrEnable \ + ROM_USBHostPwrEnable +#else +#define MAP_USBHostPwrEnable \ + USBHostPwrEnable +#endif +#ifdef ROM_USBHostPwrConfig +#define MAP_USBHostPwrConfig \ + ROM_USBHostPwrConfig +#else +#define MAP_USBHostPwrConfig \ + USBHostPwrConfig +#endif +#ifdef ROM_USBHostPwrFaultDisable +#define MAP_USBHostPwrFaultDisable \ + ROM_USBHostPwrFaultDisable +#else +#define MAP_USBHostPwrFaultDisable \ + USBHostPwrFaultDisable +#endif +#ifdef ROM_USBHostPwrFaultEnable +#define MAP_USBHostPwrFaultEnable \ + ROM_USBHostPwrFaultEnable +#else +#define MAP_USBHostPwrFaultEnable \ + USBHostPwrFaultEnable +#endif +#ifdef ROM_USBHostRequestIN +#define MAP_USBHostRequestIN \ + ROM_USBHostRequestIN +#else +#define MAP_USBHostRequestIN \ + USBHostRequestIN +#endif +#ifdef ROM_USBHostRequestStatus +#define MAP_USBHostRequestStatus \ + ROM_USBHostRequestStatus +#else +#define MAP_USBHostRequestStatus \ + USBHostRequestStatus +#endif +#ifdef ROM_USBHostReset +#define MAP_USBHostReset \ + ROM_USBHostReset +#else +#define MAP_USBHostReset \ + USBHostReset +#endif +#ifdef ROM_USBHostResume +#define MAP_USBHostResume \ + ROM_USBHostResume +#else +#define MAP_USBHostResume \ + USBHostResume +#endif +#ifdef ROM_USBHostSpeedGet +#define MAP_USBHostSpeedGet \ + ROM_USBHostSpeedGet +#else +#define MAP_USBHostSpeedGet \ + USBHostSpeedGet +#endif +#ifdef ROM_USBHostSuspend +#define MAP_USBHostSuspend \ + ROM_USBHostSuspend +#else +#define MAP_USBHostSuspend \ + USBHostSuspend +#endif +#ifdef ROM_USBIntDisable +#define MAP_USBIntDisable \ + ROM_USBIntDisable +#else +#define MAP_USBIntDisable \ + USBIntDisable +#endif +#ifdef ROM_USBIntEnable +#define MAP_USBIntEnable \ + ROM_USBIntEnable +#else +#define MAP_USBIntEnable \ + USBIntEnable +#endif +#ifdef ROM_USBDevEndpointConfigGet +#define MAP_USBDevEndpointConfigGet \ + ROM_USBDevEndpointConfigGet +#else +#define MAP_USBDevEndpointConfigGet \ + USBDevEndpointConfigGet +#endif +#ifdef ROM_USBEndpointDMAEnable +#define MAP_USBEndpointDMAEnable \ + ROM_USBEndpointDMAEnable +#else +#define MAP_USBEndpointDMAEnable \ + USBEndpointDMAEnable +#endif +#ifdef ROM_USBEndpointDMADisable +#define MAP_USBEndpointDMADisable \ + ROM_USBEndpointDMADisable +#else +#define MAP_USBEndpointDMADisable \ + USBEndpointDMADisable +#endif +#ifdef ROM_USBEndpointDataAvail +#define MAP_USBEndpointDataAvail \ + ROM_USBEndpointDataAvail +#else +#define MAP_USBEndpointDataAvail \ + USBEndpointDataAvail +#endif +#ifdef ROM_USBOTGHostRequest +#define MAP_USBOTGHostRequest \ + ROM_USBOTGHostRequest +#else +#define MAP_USBOTGHostRequest \ + USBOTGHostRequest +#endif +#ifdef ROM_USBModeGet +#define MAP_USBModeGet \ + ROM_USBModeGet +#else +#define MAP_USBModeGet \ + USBModeGet +#endif +#ifdef ROM_USBEndpointDMAChannel +#define MAP_USBEndpointDMAChannel \ + ROM_USBEndpointDMAChannel +#else +#define MAP_USBEndpointDMAChannel \ + USBEndpointDMAChannel +#endif +#ifdef ROM_USBIntDisableControl +#define MAP_USBIntDisableControl \ + ROM_USBIntDisableControl +#else +#define MAP_USBIntDisableControl \ + USBIntDisableControl +#endif +#ifdef ROM_USBIntEnableControl +#define MAP_USBIntEnableControl \ + ROM_USBIntEnableControl +#else +#define MAP_USBIntEnableControl \ + USBIntEnableControl +#endif +#ifdef ROM_USBIntStatusControl +#define MAP_USBIntStatusControl \ + ROM_USBIntStatusControl +#else +#define MAP_USBIntStatusControl \ + USBIntStatusControl +#endif +#ifdef ROM_USBIntDisableEndpoint +#define MAP_USBIntDisableEndpoint \ + ROM_USBIntDisableEndpoint +#else +#define MAP_USBIntDisableEndpoint \ + USBIntDisableEndpoint +#endif +#ifdef ROM_USBIntEnableEndpoint +#define MAP_USBIntEnableEndpoint \ + ROM_USBIntEnableEndpoint +#else +#define MAP_USBIntEnableEndpoint \ + USBIntEnableEndpoint +#endif +#ifdef ROM_USBIntStatusEndpoint +#define MAP_USBIntStatusEndpoint \ + ROM_USBIntStatusEndpoint +#else +#define MAP_USBIntStatusEndpoint \ + USBIntStatusEndpoint +#endif +#ifdef ROM_USBHostMode +#define MAP_USBHostMode \ + ROM_USBHostMode +#else +#define MAP_USBHostMode \ + USBHostMode +#endif +#ifdef ROM_USBDevMode +#define MAP_USBDevMode \ + ROM_USBDevMode +#else +#define MAP_USBDevMode \ + USBDevMode +#endif +#ifdef ROM_USBPHYPowerOff +#define MAP_USBPHYPowerOff \ + ROM_USBPHYPowerOff +#else +#define MAP_USBPHYPowerOff \ + USBPHYPowerOff +#endif +#ifdef ROM_USBPHYPowerOn +#define MAP_USBPHYPowerOn \ + ROM_USBPHYPowerOn +#else +#define MAP_USBPHYPowerOn \ + USBPHYPowerOn +#endif +#ifdef ROM_USBOTGMode +#define MAP_USBOTGMode \ + ROM_USBOTGMode +#else +#define MAP_USBOTGMode \ + USBOTGMode +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogResetEnable +#define MAP_WatchdogResetEnable \ + ROM_WatchdogResetEnable +#else +#define MAP_WatchdogResetEnable \ + WatchdogResetEnable +#endif +#ifdef ROM_WatchdogResetDisable +#define MAP_WatchdogResetDisable \ + ROM_WatchdogResetDisable +#else +#define MAP_WatchdogResetDisable \ + WatchdogResetDisable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntEnable +#define MAP_WatchdogIntEnable \ + ROM_WatchdogIntEnable +#else +#define MAP_WatchdogIntEnable \ + WatchdogIntEnable +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif +#ifdef ROM_WatchdogIntTypeSet +#define MAP_WatchdogIntTypeSet \ + ROM_WatchdogIntTypeSet +#else +#define MAP_WatchdogIntTypeSet \ + WatchdogIntTypeSet +#endif + +//***************************************************************************** +// +// Macros for the Software API. +// +//***************************************************************************** +#ifdef ROM_Crc16Array +#define MAP_Crc16Array \ + ROM_Crc16Array +#else +#define MAP_Crc16Array \ + Crc16Array +#endif +#ifdef ROM_Crc16Array3 +#define MAP_Crc16Array3 \ + ROM_Crc16Array3 +#else +#define MAP_Crc16Array3 \ + Crc16Array3 +#endif +#ifdef ROM_Crc16 +#define MAP_Crc16 \ + ROM_Crc16 +#else +#define MAP_Crc16 \ + Crc16 +#endif +#ifdef ROM_Crc8CCITT +#define MAP_Crc8CCITT \ + ROM_Crc8CCITT +#else +#define MAP_Crc8CCITT \ + Crc8CCITT +#endif + +#endif // __ROM_MAP_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/ssi.h b/cpu/stellaris_common/include/stellaris_periph/ssi.h new file mode 100644 index 0000000000..81954a67b7 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/ssi.h @@ -0,0 +1,151 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values that can be passed to SSIClockSourceSet() or returned from +// SSIClockSourceGet(). +// +//***************************************************************************** +#define SSI_CLOCK_SYSTEM 0x00000000 +#define SSI_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataGetNonBlocking(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); +extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern tBoolean SSIBusy(unsigned long ulBase); +extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource); +extern unsigned long SSIClockSourceGet(unsigned long ulBase); + +//***************************************************************************** +// +// Several SSI APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define SSIConfig(a, b, c, d, e) \ + SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e) +#define SSIDataNonBlockingGet(a, b) \ + SSIDataGetNonBlocking(a, b) +#define SSIDataNonBlockingPut(a, b) \ + SSIDataPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/sysctl.h b/cpu/stellaris_common/include/stellaris_periph/sysctl.h new file mode 100644 index 0000000000..79104e5daa --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/sysctl.h @@ -0,0 +1,642 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#ifndef DEPRECATED +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#endif +#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0 +#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module +#ifndef DEPRECATED +#define SYSCTL_PERIPH_ADC 0x00100001 // ADC +#endif +#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0 +#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_PWM 0x00100010 // PWM +#endif +#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM +#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 +#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 +#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1 +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#endif +#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#endif +#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#endif +#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 +#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 +#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 +#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0 +#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H +#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J +#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA +#define SYSCTL_PERIPH_USB0 0x20100001 // USB0 +#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet +#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588 +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0 +#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1 +#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0 +#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1 +#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2 +#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0 +#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 +#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0 +#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH +#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 +#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A +#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B +#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C +#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D +#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E +#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F +#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G +#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H +#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J +#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K +#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L +#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M +#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N +#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P +#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q +#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R +#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S +#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module +#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0 +#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1 +#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 +#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 +#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 +#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 +#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0 +#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0 +#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0 +#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0 +#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 +#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0 +#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1 +#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0 +#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1 +#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 +#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 +#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0 +#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1 +#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2 +#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3 +#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 +#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 +#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 +#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 +#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 +#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 +#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 +#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 +#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0 +#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1 +#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2 +#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 +#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 +#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 +#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 +#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 +#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA +#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0 +#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0 +#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1 +#define SYSCTL_PERIPH2_HIBERNATE \ + 0xf0001400 // Hibernate + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin +#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt +#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 +#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 +#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 +#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 +#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 +#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 +#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 +#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 +#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 +#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 +#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 +#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 +#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 +#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 +#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 +#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 +#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 +#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 +#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 +#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 +#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 +#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 +#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 +#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 +#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 +#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 +#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 +#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 +#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 +#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 +#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 +#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 +#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 +#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 +#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 +#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 +#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 +#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 +#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 +#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 +#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 +#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 +#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 +#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 +#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 +#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 +#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 +#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 +#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 +#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 +#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 +#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 +#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 +#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 +#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 +#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 +#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 +#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 +#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 +#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 +#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 +#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz +#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz +#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz +#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 +#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz +#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 +#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 +#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 +#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 +#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 +#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 +#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 +#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 +#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 +#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 +#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 +#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 +#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 +#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 +#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 +#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 +#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 +#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 +#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 +#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 +#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 +#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 +#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 +#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 +#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 +#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 +#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 +#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 +#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 +#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 +#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 +#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 +#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 +#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 +#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 +#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 +#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 +#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 +#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 +#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 +#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 +#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 +#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 +#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 +#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 +#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 +#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 +#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 +#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 +#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 +#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 +#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 +#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 +#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 +#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 +#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 +#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 +#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 +#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 +#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 +#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 +#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 +#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 +#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 +#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz +#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlDelay(unsigned long ulCount); +extern void SysCtlMOSCConfigSet(unsigned long ulConfig); +extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlDeepSleepClockSet(unsigned long ulConfig); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral); +extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); +extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock, + unsigned long ulMClk); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/sysexc.h b/cpu/stellaris_common/include/stellaris_periph/sysexc.h new file mode 100644 index 0000000000..41b0e12242 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/sysexc.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// sysexc.h - Prototypes for the System Exception Module routines. +// +// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSEXC_H__ +#define __SYSEXC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and +// SysExcIntClear as the ulIntFlags parameter, and returned from +// SysExcIntStatus. +// +//***************************************************************************** +#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt +#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt +#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt +#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt +#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int +#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void SysExcIntRegister(void (*pfnHandler)(void)); +extern void SysExcIntUnregister(void); +extern void SysExcIntEnable(unsigned long ulIntFlags); +extern void SysExcIntDisable(unsigned long ulIntFlags); +extern unsigned long SysExcIntStatus(tBoolean bMasked); +extern void SysExcIntClear(unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSEXC_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/systick.h b/cpu/stellaris_common/include/stellaris_periph/systick.h new file mode 100644 index 0000000000..30c6eff6fb --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/systick.h @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/timer.h b/cpu/stellaris_common/include/stellaris_periph/timer.h new file mode 100644 index 0000000000..6f4e381df7 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/timer.h @@ -0,0 +1,236 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ulTimers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A +#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B +#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A +#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B +#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A +#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B +#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A +#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B +#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A +#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B +#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A +#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B +#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A +#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B +#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A +#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerControlWaitOnTrigger(unsigned long ulBase, + unsigned long ulTimer, + tBoolean bWait); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue); +extern unsigned long long TimerLoadGet64(unsigned long ulBase); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern unsigned long long TimerValueGet64(unsigned long ulBase); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue); +extern unsigned long long TimerMatchGet64(unsigned long ulBase); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers); + +//***************************************************************************** +// +// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used +// instead to return the timer to its reset state. +// +//***************************************************************************** +#ifndef DEPRECATED +extern void TimerQuiesce(unsigned long ulBase); +#endif + +//***************************************************************************** +// +// These values for TimerConfigure have been deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED +#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer +#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer +#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/uart.h b/cpu/stellaris_common/include/stellaris_periph/uart.h new file mode 100644 index 0000000000..610b04bcf5 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/uart.h @@ -0,0 +1,275 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask +#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask +#define UART_INT_RI 0x001 // RI Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +// and returned by UARTConfigGetExpClk in the pulConfig parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ulParity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and +// returned by UARTFIFOLevelGet in the pulTxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and +// returned by UARTFIFOLevelGet in the pulRxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 +#define UART_OUTPUT_DTR 0x00000400 + +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +#define UART_INPUT_RI 0x00000100 +#define UART_INPUT_DCD 0x00000004 +#define UART_INPUT_DSR 0x00000002 +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + +//***************************************************************************** +// +// Values that can be passed to UARTClockSourceSet() or returned from +// UARTClockSourceGet(). +// +//***************************************************************************** +#define UART_CLOCK_SYSTEM 0x00000000 +#define UART_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern void UARTFIFOEnable(unsigned long ulBase); +extern void UARTFIFODisable(unsigned long ulBase); +extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); +extern void UARTDisableSIR(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern tBoolean UARTBusy(unsigned long ulBase); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); +extern unsigned long UARTRxErrorGet(unsigned long ulBase); +extern void UARTRxErrorClear(unsigned long ulBase); +extern void UARTSmartCardEnable(unsigned long ulBase); +extern void UARTSmartCardDisable(unsigned long ulBase); +extern void UARTModemControlSet(unsigned long ulBase, + unsigned long ulControl); +extern void UARTModemControlClear(unsigned long ulBase, + unsigned long ulControl); +extern unsigned long UARTModemControlGet(unsigned long ulBase); +extern unsigned long UARTModemStatusGet(unsigned long ulBase); +extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTFlowControlGet(unsigned long ulBase); +extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); +extern unsigned long UARTTxIntModeGet(unsigned long ulBase); +extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource); +extern unsigned long UARTClockSourceGet(unsigned long ulBase); +extern void UART9BitEnable(unsigned long ulBase); +extern void UART9BitDisable(unsigned long ulBase); +extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr, + unsigned char ucMask); +extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr); + +//***************************************************************************** +// +// Several UART APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define UARTConfigSet(a, b, c) \ + UARTConfigSetExpClk(a, SysCtlClockGet(), b, c) +#define UARTConfigGet(a, b, c) \ + UARTConfigGetExpClk(a, SysCtlClockGet(), b, c) +#define UARTCharNonBlockingGet(a) \ + UARTCharGetNonBlocking(a) +#define UARTCharNonBlockingPut(a, b) \ + UARTCharPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/cpu/stellaris_common/include/stellaris_periph/watchdog.h b/cpu/stellaris_common/include/stellaris_periph/watchdog.h new file mode 100644 index 0000000000..52d6045db0 --- /dev/null +++ b/cpu/stellaris_common/include/stellaris_periph/watchdog.h @@ -0,0 +1,95 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType); +extern void WatchdogStallEnable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/cpu/stellaris_common/license.html b/cpu/stellaris_common/license.html new file mode 100644 index 0000000000..148ae00d1f --- /dev/null +++ b/cpu/stellaris_common/license.html @@ -0,0 +1,364 @@ + + + + + +

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THE LICENSED MATERIALS AND ANY REALTED DOCUMENTATION ARE PROVIDED "AS IS" AND WITH + ALL FAULTS. TI MAKES NO WARRANTY OR REPRESENTATION, WHETHER EXPRESS, IMPLIED OR STATUTORY, + REGARDING THE LICENSED MATERIALS, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES + OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY + OR COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. TI DISCLAIMS ANY WARRANTY + OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY + PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. YOU AGREE + TO USE YOUR INDEPENDENT JUDGMENT IN DEVELOPING YOUR PRODUCTS. NOTHING CONTAINED IN + THIS AGREEMENT WILL BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY TI TO MAINTAIN + PRODUCTION OF ANY TI SEMICONDUCTOR DEVICE OR OTHER HARDWARE OR SOFTWARE WITH WHICH + THE LICENSED MATERIALS MAY BE USED. +

+

IN NO EVENT SHALL TI, OR ANY APPLICABLE LICENSOR, BE LIABLE FOR ANY SPECIAL, INDIRECT, + INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED, ON ANY THEORY OF LIABILITY, + IN CONNECTION WITH OR ARISING OUT OF THIS AGREEMENT OR THE USE OF THE LICENSED MATERIALS, + REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED + DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, OUTSIDE + COMPUTER TIME, LABOR COSTS, LOSS OF DATA, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS + OF SAVINGS, OR LOSS OF USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S AGGREGATE + LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF YOUR USE OF THE LICENSED MATERIALS + EXCEED FIVE HUNDRED U.S. DOLLARS (US$500). THE EXISTENCE OF MORE THAN ONE CLAIM WILL + NOT ENLARGE OR EXTEND THESE LIMITS. +

+

Because some jurisdictions do not allow the exclusion or limitation of incidental + or consequential damages or limitation on how long an implied warranty lasts, the + above limitations or exclusions may not apply to you. +

+

7. Indemnification Disclaimer. YOU ACKNOWLEDGE AND AGREE THAT TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR + INDEMNIFY YOU AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED + ON YOUR MANUFACTURE, USE, OR DISTRIBUTION OF THE LICENSED MATERIALS OR YOUR MANUFACTURE, + USE, OFFER FOR SALE, SALE, IMPORTATION OR DISTRIBUTION OF YOUR PRODUCTS THAT INCLUDE + OR INCORPORATE THE LICENSED MATERIALS. +

+

You will defend and indemnify TI in the event of claim, liability or costs (including + reasonable attorney's fees related to Your use or any sub-licensee's use of the Licensed + Materials) relating in any way to Your violation of the terms of the License Grants + set forth in Section 2, or any other violation of other terms and conditions of this + Agreement. +

+

8. No Technical Support. TI and TI's licensors are under no obligation to install, maintain or support the + Licensed Materials. +

+

9. Notices. All notices to TI hereunder shall be delivered to Texas Instruments Incorporated, + AEC Software Operations, 12203 Southwest Freeway, Mail Station 701, Stafford, Texas + 77477, Attention: Administrator, AEC Software Operations, with a copy to Texas Instruments + Incorporated, 12203 Southwest Freeway, Mail Station 725, Stafford, Texas 77477, Attention: + Legal Department. All notices shall be deemed served when received by TI. +

+

10. Export Control. You hereby acknowledge that the Licensed Materials are subject to export control under + the U.S. Commerce Department's Export Administration Regulations ("EAR"). You further + hereby acknowledge and agree that unless prior authorization is obtained from the + U.S. Commerce Department, neither you nor your customers will export, re-export, or + release, directly or indirectly, any technology, software, or software source code + (as defined in Part 772 of the EAR), received from TI, or export, directly or indirectly, + any direct product of such technology, software, or software source code (as defined + in Part 734 of the EAR), to any destination or country to which the export, re-export, + or release of the technology, software, or software source code, or direct product + is prohibited by the EAR. You agree that none of the Licensed Materials may be downloaded + or otherwise exported or reexported (i) into (or to a national or resident of) Cuba, + Iran, North Korea, Sudan and Syria or any other country the U.S. has embargoed goods; + or (ii) to anyone on the U.S. Treasury Department's List of Specially Designated Nationals + or the U.S. Commerce Department's Denied Persons List or Entity List. You represent + and warrant that you are not located in, under the control of, or a national or resident + of any such country or on any such list and you will not use or transfer the Licensed + Materials for use in any sensitive nuclear, chemical or biological weapons, or missile + technology end-uses unless authorized by the U.S. Government by regulation or specific + license or for a military end-use in, or by any military entity of Albania, Armenia, + Azerbaijan, Belarus, Cambodia, China, Georgia, Iran, Iraq, Kazakhstan, Kyrgyzstan, + Laos, Libya, Macau, Moldova, Mongolia, Russia, Tajikistan, Turkmenistan, Ukraine, + Uzbekistan, and Vietnam. Any software export classification made by TI shall be for + TI's internal use only and shall not be construed as a representation or warranty + regarding the proper export classification for such software or whether an export + license or other documentation is required for the exportation of such software. +

+

11. Governing Law and Severability. This Agreement will be governed by and interpreted in accordance with the laws of + the State of Texas, without reference to conflict of laws principles. If for any reason + a court of competent jurisdiction finds any provision of the Agreement to be unenforceable, + that provision will be enforced to the maximum extent possible to effectuate the intent + of the parties, and the remainder of the Agreement shall continue in full force and + effect. This Agreement shall not be governed by the United Nations Convention on Contracts + for the International Sale of Goods, or by the Uniform Computer Information Transactions + Act (UCITA), as it may be enacted in the State of Texas. The parties agree that non-exclusive + jurisdiction for any dispute arising out of or relating to this Agreement lies within + the courts located in the State of Texas. Notwithstanding the foregoing, any judgment + may be enforced in any United States or foreign court, and either party may seek injunctive + relief in any United States or foreign court. +

+

12. PRC Provisions. If you are located in the People's Republic of China ("PRC") or if the Licensed Materials + will be sent to the PRC, the following provisions shall apply and shall supersede + any other provisions in this Agreement concerning the same subject matter as the following + provisions: +

+

a. Registration Requirements. You shall be solely responsible for performing all acts and obtaining all approvals + that may be required in connection with this Agreement by the government of the PRC, + including but not limited to registering pursuant to, and otherwise complying with, + the PRC Measures on the Administration of Software Products, Management Regulations + on Technology Import-Export, and Technology Import and Export Contract Registration + Management Rules. Upon receipt of such approvals from the government authorities, + you shall forward evidence of all such approvals to TI for its records. In the event + that you fail to obtain any such approval or registration, you shall be solely responsible + for any and all losses, damages or costs resulting therefrom, and shall indemnify + TI for all such losses, damages or costs. +

+

b. Governing Language. This Agreement is written and executed in the English language. If a translation of + this Agreement is required for any purpose, including but not limited to registration + of the Agreement pursuant to any governmental laws, regulations or rules, you shall + be solely responsible for creating such translation. Any translation of this Agreement + into a language other than English is intended solely in order to comply with such + laws or for reference purposes, and the English language version shall be authoritative + and controlling. +

+

c. Export Control. +

+

(i). Diversions of Technology. You hereby agree that unless prior authorization is obtained from the U.S. Department + of Commerce, neither you nor your subsidiaries or affiliates shall knowingly export, + re-export, or release, directly or indirectly, any technology, software, or software + source code (as defined in Part 772 of the Export Administration Regulations of the + U.S. Department of Commerce ("EAR")), received from TI or any of its affiliated companies, + or export, directly or indirectly, any direct product of such technology, software, + or software source code (as defined in Part 734 of the EAR), to any destination or + country to which the export, re-export, or release of the technology, software, software + source code, or direct product is prohibited by the EAR. +

+

(ii). Assurance of Compliance. You understand and acknowledge that products, technology (regardless of the form in + which it is provided), software or software source code, received from TI or any of + its affiliates under this Agreement may be under export control of the United States + or other countries. You shall comply with the United States and other applicable non-U.S. + laws and regulations governing the export, re-export and release of any products, + technology, software, or software source code received under this Agreement from TI + or its affiliates. You shall not undertake any action that is prohibited by the EAR. + Without limiting the generality of the foregoing, you specifically agree that you + shall not transfer or release products, technology, software, or software source code + of TI or its affiliates to, or for use by, military end users or for use in military, + missile, nuclear, biological, or chemical weapons end uses. +

+

(iii). Licenses. Each party shall secure at its own expense, such licenses and export and import documents + as are necessary for each respective party to fulfill its obligations under this Agreement. + If such licenses or government approvals cannot be obtained, TI may terminate this + Agreement, or shall otherwise be excused from the performance of any obligations it + may have under this Agreement for which the licenses or government approvals are required. +

+

13. Entire Agreement. This is the entire Agreement between you and TI, and absent a signed and effective + software license agreement related to the subject matter of this Agreement, this Agreement + supersedes any prior agreement between the parties related to the subject matter of + this Agreement. Notwithstanding the foregoing, any signed and effective software license + agreement relating to the subject matter hereof will supersede the terms of this Agreement. + No amendment or modification of this Agreement will be effective unless in writing + and signed by a duly authorized representative of TI. You hereby warrant and represent + that you have obtained all authorizations and other applicable consents required empowering + you to enter into this Agreement. +

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