cpu: boards: stm32f2/f4/f7: rework clock configuration and init
This commit is contained in:
Alexandre Abadie
parent
bcd59f9789
commit
0d786e3dbb
@ -22,108 +22,444 @@
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#include "periph/gpio.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#ifndef CLOCK_CORECLOCK
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#error "Please provide CLOCK_CORECLOCK in your board's periph_conf.h"
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/* PLL configuration */
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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/* I2S clock source */
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#ifndef CONFIG_PLLI2S_SRC
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#define CONFIG_PLLI2S_SRC (0) /* PLLI2S used as I2S clock source */
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#else
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#define CONFIG_PLLI2S_SRC (1) /* Use external I2S source */
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#endif
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#if defined(CPU_FAM_STM32F2)
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#define RCC_PLLCFGR_PLLP_Pos (16U)
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#define RCC_PLLCFGR_PLLM_Pos (0U)
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#define RCC_PLLCFGR_PLLN_Pos (6U)
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#define RCC_PLLCFGR_PLLQ_Pos (24U)
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#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
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#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
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/* Compute the bitfields for the PLL configuration */
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#define PLL_M (CONFIG_CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_N (CONFIG_CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_P (((CONFIG_CLOCK_PLL_P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
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#define PLL_Q (CONFIG_CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
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#if defined(RCC_PLLCFGR_PLLR_Pos)
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#define PLL_R (CONFIG_CLOCK_PLL_R << RCC_PLLCFGR_PLLR_Pos)
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#else
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#define PLL_R (0)
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#endif
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#if (CLOCK_ENABLE_PLL_I2S)
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#ifdef RCC_PLLI2SCFGR_PLLI2SM_Pos
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#define PLLI2S_M (CLOCK_PLL_I2S_M << RCC_PLLI2SCFGR_PLLI2SM_Pos)
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#else
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#define PLLI2S_M (0)
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#endif
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#define PLLI2S_N (CLOCK_PLL_I2S_N << RCC_PLLI2SCFGR_PLLI2SN_Pos)
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#ifdef RCC_PLLI2SCFGR_PLLI2SP_Pos
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#define PLLI2S_P (((CLOCK_PLL_I2S_P / 2) - 1) << RCC_PLLI2SCFGR_PLLI2SP_Pos)
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#else
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#define PLLI2S_P (0)
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#endif
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#ifdef RCC_PLLI2SCFGR_PLLI2SQ_Pos
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#define PLLI2S_Q (CLOCK_PLL_I2S_Q << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
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#else
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#define PLLI2S_Q (0)
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#endif
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#if defined(RCC_PLLI2SCFGR_PLLI2SR_Pos) && defined(CLOCK_PLL_I2S_R)
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#define PLLI2S_R (CLOCK_PLL_I2S_R << RCC_PLLI2SCFGR_PLLI2SR_Pos)
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#else
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#define PLLI2S_R (0)
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#endif
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#endif /* CLOCK_ENABLE_PLLI_2S */
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/* Select 48MHz clock source between PLLQ, PLLI2SQ or PLLSAIQ. This depends on
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the PLL parameters and if not possible on CPU lines which can provide 48MHz
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from PLLI2S or PLLSAI */
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#if (CLOCK_ENABLE_PLL_SAI)
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#ifdef RCC_PLLSAICFGR_PLLSAIN_Pos
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#define PLLSAI_M (CLOCK_PLL_SAI_M << RCC_PLLSAICFGR_PLLSAIM_Pos)
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/* Determine if PLL is required, even if not used as SYSCLK
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This is the case when USB is used in application and PLLQ is configured to
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output 48MHz */
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#if IS_USED(MODULE_PERIPH_USBDEV) && (CLOCK_PLLQ == MHZ(48))
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#define CLOCK_REQUIRE_PLLQ 1
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#else
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#define PLLSAI_M (0)
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#define CLOCK_REQUIRE_PLLQ 0
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#endif
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#define PLLSAI_N (CLOCK_PLL_SAI_N << RCC_PLLSAICFGR_PLLSAIN_Pos)
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#ifdef RCC_PLLSAICFGR_PLLSAIP_Pos
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#define PLLSAI_P (((CLOCK_PLL_SAI_P / 2) - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)
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#else
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#define PLLSAI_P (0)
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#endif
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#define PLLSAI_Q (CLOCK_PLL_SAI_Q << RCC_PLLSAICFGR_PLLSAIQ_Pos)
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#if defined(RCC_PLLSAICFGR_PLLSAIR_Pos) && defined(CLOCK_PLL_SAI_R)
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#define PLLSAI_R (CLOCK_PLL_SAI_R << RCC_PLLSAICFGR_PLLSAIR_Pos)
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#else
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#define PLLSAI_R (0)
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#endif
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#endif /* CLOCK_ENABLE_PLL_SAI */
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/* now we get the actual bitfields */
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#define PLL_P (((CLOCK_PLL_P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
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#define PLL_M (CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_Q (CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
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#if defined(RCC_PLLCFGR_PLLR_Pos) && defined(CLOCK_PLL_R)
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#define PLL_R (CLOCK_PLL_R << RCC_PLLCFGR_PLLR_Pos)
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/* PLLI2S can only be used for USB with F412/F413/F423 lines
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PLLI2S is only enabled if no suitable 48MHz clock source can be generated with PLLQ */
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#if (defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
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defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
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defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)) && \
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IS_USED(MODULE_PERIPH_USBDEV) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
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#define CLOCK_REQUIRE_PLLI2SR 1
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#else
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#define PLL_R (0)
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/* Disable PLLI2S if USB is not required or is required but PLLQ cannot generate 48MHz clock */
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#define CLOCK_REQUIRE_PLLI2SR 0
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#endif
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
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/* PLLSAI can only be used for USB with F446/469/479 lines and F7
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PLLSAI is only enabled if no suitable 48MHz clock source can be generated with PLLQ */
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#if (defined(CPU_LINE_STM32F446xx) || defined(CPU_LINE_STM32F469xx) || \
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defined(CPU_LINE_STM32F479xx) || defined(CPU_FAM_STM32F7)) && \
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IS_USED(MODULE_PERIPH_USBDEV) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
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#define CLOCK_REQUIRE_PLLSAIP 1
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#else
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/* Disable PLLSAI if USB is not required or is required but PLLQ cannot generate 48MHz clock */
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#define CLOCK_REQUIRE_PLLSAIP 0
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#endif
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#if IS_USED(MODULE_PERIPH_USBDEV) && \
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!(IS_ACTIVE(CLOCK_REQUIRE_PLLQ) || \
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IS_ACTIVE(CLOCK_REQUIRE_PLLI2SR) || \
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IS_ACTIVE(CLOCK_REQUIRE_PLLSAIP))
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#error No suitable 48MHz found, USB will not work
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#endif
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/* PLLI2S configuration: the following parameters configure a 48MHz I2S clock
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with HSE (8MHz) or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLLI2S_M
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/* PLLM factor is not shared with PLLI2S on F412/413/423/446 cpu lines */
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#if defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
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defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
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defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx) || \
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defined(CPU_LINE_STM32F446xx)
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#define CONFIG_CLOCK_PLLI2S_M (4)
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#else
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#define CONFIG_CLOCK_PLLI2S_M CONFIG_CLOCK_PLL_M
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLLI2S_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CONFIG_CLOCK_PLLI2S_N (192)
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#else
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#define CONFIG_CLOCK_PLLI2S_N (96)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLLI2S_P
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#define CONFIG_CLOCK_PLLI2S_P (8) /* SPDIF-Rx clock, 48MHz by default */
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#endif
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#ifndef CONFIG_CLOCK_PLLI2S_Q
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#define CONFIG_CLOCK_PLLI2S_Q (8) /* Alternative 48MHz clock (USB) and/or MCO2 PLLI2S */
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#endif
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#ifndef CONFIG_CLOCK_PLLI2S_R
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#define CONFIG_CLOCK_PLLI2S_R (8) /* I2S clock, 48MHz by default */
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#endif
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#if defined(RCC_PLLI2SCFGR_PLLI2SM_Pos)
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#define PLLI2S_M (CONFIG_CLOCK_PLLI2S_M << RCC_PLLI2SCFGR_PLLI2SM_Pos)
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#else
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#define PLLI2S_M (0)
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#endif
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#if defined(RCC_PLLI2SCFGR_PLLI2SN_Pos)
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#define PLLI2S_N (CONFIG_CLOCK_PLLI2S_N << RCC_PLLI2SCFGR_PLLI2SN_Pos)
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#else
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#define PLLI2S_N (0)
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#endif
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#if defined(RCC_PLLI2SCFGR_PLLI2SP_Pos)
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#define PLLI2S_P (((CONFIG_CLOCK_PLLI2S_P >> 1) - 1) << RCC_PLLI2SCFGR_PLLI2SP_Pos)
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#else
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#define PLLI2S_P (0)
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#endif
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#if defined(RCC_PLLI2SCFGR_PLLI2SQ_Pos)
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#define PLLI2S_Q (CONFIG_CLOCK_PLLI2S_Q << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
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#else
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#define PLLI2S_Q (0)
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#endif
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#if defined(RCC_PLLI2SCFGR_PLLI2SR_Pos)
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#define PLLI2S_R (CONFIG_CLOCK_PLLI2S_R << RCC_PLLI2SCFGR_PLLI2SR_Pos)
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#else
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#define PLLI2S_R (0)
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#endif
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/* PLLSAI configuration: the following parameters configure a 48MHz SAI clock
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with HSE (8MHz) or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLLSAI_M
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/* PLLM factor is not shared with PLLSAI on F412/413/423/446 cpu lines */
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#if defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
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defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
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defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx) || \
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defined(CPU_LINE_STM32F446xx)
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#define CONFIG_CLOCK_PLLSAI_M (4)
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#else
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#define CONFIG_CLOCK_PLLSAI_M CONFIG_CLOCK_PLL_M
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLLSAI_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CONFIG_CLOCK_PLLSAI_N (192)
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#else
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#define CONFIG_CLOCK_PLLSAI_N (96)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLLSAI_P
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#define CONFIG_CLOCK_PLLSAI_P (8) /* Alternative 48MHz clock (USB) */
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#endif
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#ifndef CONFIG_CLOCK_PLLSAI_Q
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#define CONFIG_CLOCK_PLLSAI_Q (8) /* SAI clock, 48MHz by default */
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#endif
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#ifndef CONFIG_CLOCK_PLLSAI_R
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#define CONFIG_CLOCK_PLLSAI_R (8) /* LCD clock, 48MHz by default */
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#endif
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#if defined(RCC_PLLSAICFGR_PLLSAIM_Pos)
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#define PLLSAI_M (CONFIG_CLOCK_PLLSAI_M << RCC_PLLSAICFGR_PLLSAIM_Pos)
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#else
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#define PLLSAI_M (0)
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#endif
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#if defined(RCC_PLLSAICFGR_PLLSAIN_Pos)
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#define PLLSAI_N (CONFIG_CLOCK_PLLSAI_N << RCC_PLLSAICFGR_PLLSAIN_Pos)
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#else
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#define PLLSAI_N (0)
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#endif
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#if defined(RCC_PLLSAICFGR_PLLSAIP_Pos)
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#define PLLSAI_P (((CONFIG_CLOCK_PLLSAI_P >> 1) - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)
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#else
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#define PLLSAI_P (0)
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#endif
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#if defined(RCC_PLLSAICFGR_PLLSAIQ_Pos)
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#define PLLSAI_Q (CONFIG_CLOCK_PLLSAI_Q << RCC_PLLSAICFGR_PLLSAIQ_Pos)
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#else
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#define PLLSAI_Q (0)
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#endif
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#if defined(RCC_PLLSAICFGR_PLLSAIR_Pos)
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#define PLLSAI_R (CONFIG_CLOCK_PLLSAI_R << RCC_PLLSAICFGR_PLLSAIR_Pos)
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#else
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#define PLLSAI_R (0)
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#endif
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/* Configure HLCK and PCLK prescalers */
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#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16)
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#else
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#error "Invalid APB1 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4)
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#elif CONFIG_CLOCK_APB2_DIV == 8
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8)
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#elif CONFIG_CLOCK_APB2_DIV == 16
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16)
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#else
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#error "Invalid APB2 prescaler value (only 1, 2, 4, 8 and 16 allowed)"
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#endif
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/* Deduct the needed flash wait states from the core clock frequency */
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#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
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/* we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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#define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
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#define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
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#elif defined(CPU_FAM_STM32F7)
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#define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
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#define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
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#endif
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/* Default is not configure MCO1 */
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#ifndef CONFIG_CLOCK_ENABLE_MCO1
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#define CONFIG_CLOCK_ENABLE_MCO1 0
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#endif
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#if !defined(RCC_CFGR_MCO1) && IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1)
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#error "stmclk: no MCO1 on this device"
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#endif
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/* Configure the MCO1 clock source: options are PLL (default), HSE or HSI */
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#ifndef CONFIG_CLOCK_MCO1_USE_PLL
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#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI)
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#define CONFIG_CLOCK_MCO1_USE_PLL 0
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#else
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#define CONFIG_CLOCK_MCO1_USE_PLL 1 /* Use PLL by default */
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#endif
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#endif /* CONFIG_CLOCK_MCO1_USE_PLL */
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#ifndef CONFIG_CLOCK_MCO1_USE_HSE
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#define CONFIG_CLOCK_MCO1_USE_HSE 0
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#endif /* CONFIG_CLOCK_MCO1_USE_HSE */
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#ifndef CONFIG_CLOCK_MCO1_USE_HSI
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#define CONFIG_CLOCK_MCO1_USE_HSI 0
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#endif /* CONFIG_CLOCK_MCO1_USE_HSI */
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#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI))
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#error "Cannot use PLL as MCO1 clock source with other clock"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI))
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#error "Cannot use HSE as MCO1 clock source with other clock"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI) && \
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(IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL))
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#error "Cannot use HSI as MCO1 clock source with other clock"
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL)
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#define CLOCK_MCO1_SRC (RCC_CFGR_MCO1_1 | RCC_CFGR_MCO1_0)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE)
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#define CLOCK_MCO1_SRC (RCC_CFGR_MCO1_1)
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#elif IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSI)
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#define CLOCK_MCO1_SRC (0)
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#else
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#error "Invalid MCO1 clock source selection"
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#endif
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/* Configure the MCO1 prescaler: options are 1 to 5 */
|
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#ifndef CONFIG_CLOCK_MCO1_PRE
|
||||
#define CONFIG_CLOCK_MCO1_PRE (1)
|
||||
#endif
|
||||
|
||||
#if CONFIG_CLOCK_MCO1_PRE == 1
|
||||
#define CLOCK_MCO1_PRE (0)
|
||||
#elif CONFIG_CLOCK_MCO1_PRE == 2
|
||||
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2)
|
||||
#elif CONFIG_CLOCK_MCO1_PRE == 3
|
||||
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_0)
|
||||
#elif CONFIG_CLOCK_MCO1_PRE == 4
|
||||
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1)
|
||||
#elif CONFIG_CLOCK_MCO1_PRE == 5
|
||||
#define CLOCK_MCO1_PRE (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0)
|
||||
#else
|
||||
#error "Invalid MCO1 prescaler"
|
||||
#endif
|
||||
|
||||
/* Default is not configure MCO2 */
|
||||
#ifndef CONFIG_CLOCK_ENABLE_MCO2
|
||||
#define CONFIG_CLOCK_ENABLE_MCO2 0
|
||||
#endif
|
||||
|
||||
#if !defined(RCC_CFGR_MCO2) && IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2)
|
||||
#error "stmclk: no MCO2 on this device"
|
||||
#endif
|
||||
|
||||
/* Configure the MCO2 clock source: options are PLL (default), HSE, HSI or LSE */
|
||||
#ifndef CONFIG_CLOCK_MCO2_USE_PLL
|
||||
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
|
||||
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK)
|
||||
#define CONFIG_CLOCK_MCO2_USE_PLL 0
|
||||
#else
|
||||
#define CONFIG_CLOCK_MCO2_USE_PLL 1 /* Use PLL by default */
|
||||
#endif
|
||||
#endif /* CONFIG_CLOCK_MCO2_USE_PLL */
|
||||
|
||||
#ifndef CONFIG_CLOCK_MCO2_USE_HSE
|
||||
#define CONFIG_CLOCK_MCO2_USE_HSE 0
|
||||
#endif /* CONFIG_CLOCK_MCO2_USE_HSE */
|
||||
|
||||
#ifndef CONFIG_CLOCK_MCO2_USE_PLLI2S
|
||||
#define CONFIG_CLOCK_MCO2_USE_PLLI2S 0
|
||||
#endif /* CONFIG_CLOCK_MCO2_USE_PLLI2S */
|
||||
|
||||
#ifndef CONFIG_CLOCK_MCO2_USE_SYSCLK
|
||||
#define CONFIG_CLOCK_MCO2_USE_SYSCLK 0
|
||||
#endif /* CONFIG_CLOCK_MCO2_USE_SYSCLK */
|
||||
|
||||
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL) && \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
|
||||
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK))
|
||||
#error "Cannot use PLL as MCO2 clock source with other clock"
|
||||
#endif
|
||||
|
||||
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) && \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
|
||||
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK))
|
||||
#error "Cannot use HSE as MCO2 clock source with other clock"
|
||||
#endif
|
||||
|
||||
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) && \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL) || \
|
||||
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK))
|
||||
#error "Cannot use PLLI2S as MCO2 clock source with other clock"
|
||||
#endif
|
||||
|
||||
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK) && \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S) || \
|
||||
IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL))
|
||||
#error "Cannot use SYSCLK as MCO2 clock source with other clock"
|
||||
#endif
|
||||
|
||||
#if IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL)
|
||||
#define CLOCK_MCO2_SRC (RCC_CFGR_MCO2_1 | RCC_CFGR_MCO2_0)
|
||||
#elif IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE)
|
||||
#define CLOCK_MCO2_SRC (RCC_CFGR_MCO2_1)
|
||||
#elif IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S)
|
||||
#define CLOCK_MCO2_SRC (RCC_CFGR_MCO2_0)
|
||||
#elif IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_SYSCLK)
|
||||
#define CLOCK_MCO2_SRC (0)
|
||||
#else
|
||||
#error "Invalid MCO2 clock source selection"
|
||||
#endif
|
||||
|
||||
/* Configure the MCO2 prescaler: options are 1 to 5 */
|
||||
#ifndef CONFIG_CLOCK_MCO2_PRE
|
||||
#define CONFIG_CLOCK_MCO2_PRE (1)
|
||||
#endif
|
||||
|
||||
#if CONFIG_CLOCK_MCO2_PRE == 1
|
||||
#define CLOCK_MCO2_PRE (0)
|
||||
#elif CONFIG_CLOCK_MCO2_PRE == 2
|
||||
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2)
|
||||
#elif CONFIG_CLOCK_MCO2_PRE == 3
|
||||
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)
|
||||
#elif CONFIG_CLOCK_MCO2_PRE == 4
|
||||
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)
|
||||
#elif CONFIG_CLOCK_MCO2_PRE == 5
|
||||
#define CLOCK_MCO2_PRE (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)
|
||||
#else
|
||||
#error "Invalid MCO1 prescaler"
|
||||
#endif
|
||||
|
||||
/* Check whether PLL must be enabled:
|
||||
- When PLL is used as SYSCLK
|
||||
- When PLLQ is required
|
||||
- When PLL is used as input source for MCO1 or MCO2
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_CLOCK_ENABLE_PLLQ) || \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1) && IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_PLL)) || \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2) && IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLL))
|
||||
#define CLOCK_ENABLE_PLL 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_PLL 0
|
||||
#endif
|
||||
|
||||
/* Check whether HSE must be enabled:
|
||||
- When HSE is used as SYSCLK
|
||||
- When PLL is used as SYSCLK and the board provides HSE (since HSE will be
|
||||
used as PLL input clock)
|
||||
- When HSE is used input source for MCO1 or MCO2
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
|
||||
(IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CLOCK_ENABLE_PLL)) || \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1) && IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE)) || \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2) && IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_HSE))
|
||||
#define CLOCK_ENABLE_HSE 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_HSE 0
|
||||
#endif
|
||||
|
||||
/* Check whether HSI must be enabled:
|
||||
- When HSI is used as SYSCLK
|
||||
- When PLL is used as SYSCLK and the board doesn't provide HSE (since HSI will be
|
||||
used as PLL input clock)
|
||||
- When HSI is used input source for MCO1
|
||||
*/
|
||||
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
|
||||
(!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CLOCK_ENABLE_PLL)) || \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1) && IS_ACTIVE(CONFIG_CLOCK_MCO1_USE_HSE))
|
||||
#define CLOCK_ENABLE_HSI 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_HSI 0
|
||||
#endif
|
||||
|
||||
/* Check whether PLLI2S must be enabled:
|
||||
- When PLLI2SR is required
|
||||
- When PLLI2S is used as input clock for MCO2
|
||||
*/
|
||||
#if IS_ACTIVE(CLOCK_REQUIRE_PLLI2SR) || \
|
||||
(IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2) && IS_ACTIVE(CONFIG_CLOCK_MCO2_USE_PLLI2S))
|
||||
#define CLOCK_ENABLE_PLLI2S 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_PLLI2S 0
|
||||
#endif
|
||||
|
||||
/* Check whether PLLSAI must be enabled */
|
||||
#if IS_ACTIVE(CLOCK_REQUIRE_PLLSAIP)
|
||||
#define CLOCK_ENABLE_PLLSAI 1
|
||||
#else
|
||||
#define CLOCK_ENABLE_PLLSAI 0
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
void stmclk_init_sysclk(void)
|
||||
{
|
||||
@ -137,8 +473,7 @@ void stmclk_init_sysclk(void)
|
||||
|
||||
/* use HSI as system clock while we do any further configuration and
|
||||
* configure the AHB and APB clock dividers as configure by the board */
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
|
||||
CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
|
||||
|
||||
/* Flash config */
|
||||
@ -147,49 +482,74 @@ void stmclk_init_sysclk(void)
|
||||
/* disable all active clocks except HSI -> resets the clk configuration */
|
||||
RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
|
||||
|
||||
#if (CLOCK_MCO1_SRC)
|
||||
#ifndef RCC_CFGR_MCO1
|
||||
#error "stmclk: no MCO1 on this device"
|
||||
#endif
|
||||
RCC->CFGR |= CLOCK_MCO1_SRC | CLOCK_MCO1_PRE;
|
||||
#endif
|
||||
#if (CLOCK_MCO2_SRC)
|
||||
#ifndef RCC_CFGR_MCO2
|
||||
#error "stmclk: no MCO2 on this device"
|
||||
#endif
|
||||
RCC->CFGR |= CLOCK_MCO2_SRC | CLOCK_MCO2_PRE;
|
||||
if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO1)) {
|
||||
RCC->CFGR |= CLOCK_MCO1_SRC | CLOCK_MCO1_PRE;
|
||||
|
||||
/* Configure GPIO pin (PA8/AF0) */
|
||||
gpio_init(GPIO_PIN(PORT_A, 8), GPIO_OUT);
|
||||
gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
|
||||
}
|
||||
|
||||
if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO2)) {
|
||||
RCC->CFGR |= CLOCK_MCO2_SRC | CLOCK_MCO2_PRE;
|
||||
|
||||
/* Configure GPIO pin (PC9/AF0) */
|
||||
gpio_init(GPIO_PIN(PORT_C, 9), GPIO_OUT);
|
||||
gpio_init_af(GPIO_PIN(PORT_C, 9), GPIO_AF0);
|
||||
}
|
||||
|
||||
/* Enable HSE if required */
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
|
||||
RCC->CR |= (RCC_CR_HSEON);
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
}
|
||||
|
||||
/* Enable PLL if required */
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
|
||||
/* now we can safely configure and start the PLL */
|
||||
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q | PLL_R);
|
||||
RCC->CR |= (RCC_CR_PLLON);
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
}
|
||||
|
||||
/* Configure SYSCLK */
|
||||
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
|
||||
/* Enable HSE as system clock */
|
||||
RCC->CFGR |= (RCC_CFGR_SW_HSE);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
|
||||
}
|
||||
else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
|
||||
/* Enable PLLP as system clock */
|
||||
RCC->CFGR |= (RCC_CFGR_SW_PLL);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
|
||||
}
|
||||
|
||||
if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
|
||||
/* Disable HSI only if not used */
|
||||
stmclk_disable_hsi();
|
||||
}
|
||||
|
||||
#if defined(RCC_CR_PLLI2SON)
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_PLLI2S)) {
|
||||
RCC->PLLI2SCFGR = (CONFIG_PLLI2S_SRC | PLLI2S_M | PLLI2S_N | PLLI2S_P | PLLI2S_Q | PLLI2S_R);
|
||||
RCC->CR |= (RCC_CR_PLLI2SON);
|
||||
while (!(RCC->CR & RCC_CR_PLLI2SRDY)) {}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* if configured, we need to enable the HSE clock now */
|
||||
#if (CLOCK_HSE)
|
||||
RCC->CR |= (RCC_CR_HSEON);
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
#if defined(RCC_CR_PLLSAION)
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_PLLSAI)) {
|
||||
RCC->PLLSAICFGR = (PLLSAI_M | PLLSAI_N | PLLSAI_P | PLLSAI_Q | PLLSAI_R);
|
||||
RCC->CR |= (RCC_CR_PLLSAION);
|
||||
while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CLOCK_USE_ALT_48MHZ
|
||||
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
|
||||
#endif
|
||||
/* now we can safely configure and start the PLL */
|
||||
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q | PLL_R);
|
||||
RCC->CR |= (RCC_CR_PLLON);
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
|
||||
/* now that the PLL is running, we use it as system clock */
|
||||
RCC->CFGR |= (RCC_CFGR_SW_PLL);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
|
||||
|
||||
stmclk_disable_hsi();
|
||||
|
||||
#if (CLOCK_ENABLE_PLL_I2S)
|
||||
RCC->PLLI2SCFGR = (CLOCK_PLL_I2S_SRC | PLLI2S_M | PLLI2S_N | PLLI2S_P | PLLI2S_Q | PLLI2S_R);
|
||||
RCC->CR |= (RCC_CR_PLLI2SON);
|
||||
while (!(RCC->CR & RCC_CR_PLLI2SRDY)) {}
|
||||
#endif /* CLOCK_ENABLE_PLLI2S */
|
||||
|
||||
#if (CLOCK_ENABLE_PLL_SAI)
|
||||
RCC->PLLSAICFGR = (PLLSAI_M | PLLSAI_N | PLLSAI_P | PLLSAI_Q | PLLSAI_R);
|
||||
RCC->CR |= (RCC_CR_PLLSAION);
|
||||
while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {}
|
||||
#if defined(RCC_DCKCFGR2_CK48MSEL)
|
||||
if (IS_ACTIVE(CLOCK_ENABLE_PLLI2S) || IS_ACTIVE(CLOCK_ENABLE_PLLSAI)) {
|
||||
/* Use PLLSAI_P or PLLI2S_Q clock source */
|
||||
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
|
||||
}
|
||||
#endif
|
||||
|
||||
irq_restore(is);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user