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Merge pull request #4115 from haukepetersen/opt_stm32f4_uart

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cpu/stm32f4: optimized UART driver
This commit is contained in:
Thomas Eichinger 2015-12-08 11:44:13 +01:00
commit 0f80e688f3
13 changed files with 405 additions and 321 deletions
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2
boards/f4vi1/include/board.h
View File

@ -38,7 +38,7 @@ extern "C" {
* @name Define UART device and baudrate for stdio * @name Define UART device and baudrate for stdio
* @{ * @{
*/ */
#define STDIO UART_0 #define STDIO UART_DEV(0)
#define STDIO_BAUDRATE (115200U) #define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U) #define STDIO_RX_BUFSIZE (64U)
/** @} */ /** @} */

41
boards/f4vi1/include/periph_conf.h
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@ -21,6 +21,8 @@
#ifndef PERIPH_CONF_H_ #ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_ #define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -41,6 +43,11 @@ extern "C" {
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
/** @} */ /** @} */
/** /**
@ -75,24 +82,26 @@ extern "C" {
* @name UART configuration * @name UART configuration
* @{ * @{
*/ */
#define UART_NUMOF (1U) static const uart_conf_t uart_config[] = {
#define UART_0_EN 1 /* device, RCC mask, RX pin, TX pin, pin AF, IRQ channel, DMA stream, DMA */
#define UART_1_EN 0 {
#define UART_IRQ_PRIO 1 USART6, /* device base register */
RCC_APB2ENR_USART6EN, /* RCC mask */
GPIO_PIN(PORT_C,7), /* RX pin */
GPIO_PIN(PORT_C,6), /* TX pin */
GPIO_AF8, /* pin AF */
USART6_IRQn, /* IRQ channel */
14, /* DMA stream */
5 /* DMA channel */
},
};
/* UART 0 device configuration */ /* assign ISR vector names */
#define UART_0_DEV USART6
#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART6EN)
#define UART_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define UART_0_CLK (84000000) /* UART clock runs with 84MHz (F_CPU / 2) */
#define UART_0_IRQ_CHAN USART6_IRQn
#define UART_0_ISR isr_usart6 #define UART_0_ISR isr_usart6
/* UART 0 pin configuration */ #define UART_0_DMA_ISR isr_dma2_stream6
#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
#define UART_0_PORT GPIOC /* deduct number of defined UART interfaces */
#define UART_0_TX_PIN 6 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
#define UART_0_RX_PIN 7
#define UART_0_AF 8
/** @} */ /** @} */
#ifdef __cplusplus #ifdef __cplusplus

4
boards/msbiot/include/board.h
View File

@ -23,8 +23,6 @@
#include "cpu.h" #include "cpu.h"
#include "periph_conf.h" #include "periph_conf.h"
#include "periph/gpio.h"
#include "periph/spi.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -59,7 +57,7 @@ extern "C" {
* @name Define UART device and baudrate for stdio * @name Define UART device and baudrate for stdio
* @{ * @{
*/ */
#define STDIO UART_0 #define STDIO UART_DEV(0)
#define STDIO_BAUDRATE (115200U) #define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U) #define STDIO_RX_BUFSIZE (64U)
/** @} */ /** @} */

90
boards/msbiot/include/periph_conf.h
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@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_ #ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_ #define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -39,6 +41,11 @@ extern "C" {
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
/** @} */ /** @} */
@ -145,53 +152,50 @@ extern "C" {
* @name UART configuration * @name UART configuration
* @{ * @{
*/ */
#define UART_NUMOF (3U) static const uart_conf_t uart_config[] = {
#define UART_0_EN 1 /* device, RCC mask, RX pin, TX pin, pin AF, IRQ channel, DMA stream, DMA */
#define UART_1_EN 1 {
#define UART_2_EN 1 USART2, /* device base register */
#define UART_IRQ_PRIO 1 RCC_APB1ENR_USART2EN, /* RCC mask */
GPIO_PIN(PORT_A,3), /* RX pin */
GPIO_PIN(PORT_A,2), /* TX pin */
GPIO_AF7, /* pin AF */
USART2_IRQn, /* IRQ channel */
6, /* DMA stream */
4 /* DMA channel */
},
{
USART1, /* device base register */
RCC_APB2ENR_USART1EN, /* RCC mask */
GPIO_PIN(PORT_A,10), /* RX pin */
GPIO_PIN(PORT_A,9), /* TX pin */
GPIO_AF7, /* pin AF */
USART1_IRQn, /* IRQ channel */
15, /* DMA stream */
4 /* DMA channel */
},
{
USART3, /* device base register */
RCC_APB1ENR_USART3EN, /* RCC mask */
GPIO_PIN(PORT_D,9), /* RX pin */
GPIO_PIN(PORT_D,8), /* TX pin */
GPIO_AF7, /* pin AF */
USART3_IRQn, /* IRQ channel */
3, /* DMA stream */
4 /* DMA channel */
},
};
/* UART 0 device configuration */ /* assign ISR vector names */
#define UART_0_DEV USART2
#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define UART_0_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
#define UART_0_IRQ_CHAN USART2_IRQn
#define UART_0_ISR isr_usart2 #define UART_0_ISR isr_usart2
/* UART 0 pin configuration */ #define UART_0_DMA_ISR isr_dma1_stream6
#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
#define UART_0_PORT GPIOA
#define UART_0_TX_PIN 2
#define UART_0_RX_PIN 3
#define UART_0_AF 7
/* UART 1 device configuration */
#define UART_1_DEV USART1
#define UART_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
#define UART_1_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define UART_1_CLK (84000000) /* UART clock runs with 84MHz (F_CPU / 2) */
#define UART_1_IRQ_CHAN USART1_IRQn
#define UART_1_ISR isr_usart1 #define UART_1_ISR isr_usart1
/* UART 1 pin configuration */ #define UART_1_DMA_ISR isr_dma2_stream7
#define UART_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
#define UART_1_PORT GPIOA
#define UART_1_TX_PIN 9
#define UART_1_RX_PIN 10
#define UART_1_AF 7
/* UART 2 device configuration */
#define UART_2_DEV USART3
#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
#define UART_2_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define UART_2_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
#define UART_2_IRQ_CHAN USART3_IRQn
#define UART_2_ISR isr_usart3 #define UART_2_ISR isr_usart3
/* UART 2 pin configuration */ #define UART_2_DMA_ISR isr_dma1_stream3
#define UART_2_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN)
#define UART_2_PORT GPIOD /* deduct number of defined UART interfaces */
#define UART_2_TX_PIN 8 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
#define UART_2_RX_PIN 9
#define UART_2_AF 7
/** @} */ /** @} */
/** /**

2
boards/nucleo-f401/include/board.h
View File

@ -47,7 +47,7 @@ extern "C" {
* @name Define UART device and baudrate for stdio * @name Define UART device and baudrate for stdio
* @{ * @{
*/ */
#define STDIO UART_0 #define STDIO UART_DEV(0)
#define STDIO_BAUDRATE (115200U) #define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U) #define STDIO_RX_BUFSIZE (64U)
/** @} */ /** @} */

41
boards/nucleo-f401/include/periph_conf.h
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@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_ #ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_ #define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -39,6 +41,11 @@ extern "C" {
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/** @} */ /** @} */
/** /**
@ -73,24 +80,26 @@ extern "C" {
* @name UART configuration * @name UART configuration
* @{ * @{
*/ */
#define UART_NUMOF (1U) static const uart_conf_t uart_config[] = {
#define UART_0_EN 1 /* device, RCC mask, RX pin, TX pin, pin AF, IRQ channel, DMA stream, DMA */
#define UART_IRQ_PRIO 1 {
#define UART_CLK (14000000U) /* UART clock runs with 14MHz */ USART2, /* device base register */
RCC_APB1ENR_USART2EN, /* RCC mask */
GPIO_PIN(PORT_A,3), /* RX pin */
GPIO_PIN(PORT_A,2), /* TX pin */
GPIO_AF7, /* pin AF */
USART2_IRQn, /* IRQ channel */
6, /* DMA stream */
4 /* DMA channel */
}
};
/* UART 0 device configuration */ /* assign ISR vector names */
#define UART_0_DEV USART2
#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define UART_0_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 42MHz (F_CPU / 2) */
#define UART_0_IRQ_CHAN USART2_IRQn
#define UART_0_ISR isr_usart2 #define UART_0_ISR isr_usart2
/* UART 0 pin configuration */ #define UART_0_DMA_ISR isr_dma1_stream6
#define UART_0_PORT GPIOA
#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) /* deduct number of defined UART interfaces */
#define UART_0_RX_PIN 3 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
#define UART_0_TX_PIN 2
#define UART_0_AF 7
/** @} */ /** @} */
/** /**

2
boards/stm32f4discovery/include/board.h
View File

@ -47,7 +47,7 @@ extern "C" {
* @name Define UART device and baudrate for stdio * @name Define UART device and baudrate for stdio
* @{ * @{
*/ */
#define STDIO UART_0 #define STDIO UART_DEV(0)
#define STDIO_BAUDRATE (115200U) #define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U) #define STDIO_RX_BUFSIZE (64U)
/** @} */ /** @} */

68
boards/stm32f4discovery/include/periph_conf.h
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@ -20,6 +20,8 @@
#ifndef PERIPH_CONF_H_ #ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_ #define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -40,6 +42,11 @@ extern "C" {
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
/** @} */ /** @} */
/** /**
@ -74,41 +81,38 @@ extern "C" {
* @name UART configuration * @name UART configuration
* @{ * @{
*/ */
#define UART_NUMOF (2U) static const uart_conf_t uart_config[] = {
#define UART_0_EN 1 /* device, RCC mask, RX pin, TX pin, pin AF, IRQ channel, DMA stream, DMA */
#define UART_1_EN 1 {
#define UART_IRQ_PRIO 1 USART2, /* device base register */
#define UART_CLK (14000000U) /* UART clock runs with 14MHz */ RCC_APB1ENR_USART2EN, /* RCC mask */
GPIO_PIN(PORT_A,3), /* RX pin */
GPIO_PIN(PORT_A,2), /* TX pin */
GPIO_AF7, /* pin AF */
USART2_IRQn, /* IRQ channel */
6, /* DMA stream */
4 /* DMA channel */
},
{
USART3, /* device base register */
RCC_APB1ENR_USART3EN, /* RCC mask */
GPIO_PIN(PORT_D,9), /* RX pin */
GPIO_PIN(PORT_D,8), /* TX pin */
GPIO_AF7, /* pin AF */
USART3_IRQn, /* IRQ channel */
3, /* DMA stream */
4 /* DMA channel */
},
};
/* assign ISR vector names */
/* UART 0 device configuration */
#define UART_0_DEV USART2
#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define UART_0_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
#define UART_0_IRQ_CHAN USART2_IRQn
#define UART_0_ISR isr_usart2 #define UART_0_ISR isr_usart2
/* UART 0 pin configuration */ #define UART_0_DMA_ISR isr_dma1_stream6
#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
#define UART_0_PORT GPIOA
#define UART_0_TX_PIN 2
#define UART_0_RX_PIN 3
#define UART_0_AF 7
/* UART 1 device configuration */
#define UART_1_DEV USART3
#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
#define UART_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define UART_1_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
#define UART_1_IRQ_CHAN USART3_IRQn
#define UART_1_ISR isr_usart3 #define UART_1_ISR isr_usart3
/* UART 1 pin configuration */ #define UART_1_DMA_ISR isr_dma1_stream3
#define UART_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN)
#define UART_1_PORT GPIOD /* deduct number of defined UART interfaces */
#define UART_1_TX_PIN 8 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
#define UART_1_RX_PIN 9
#define UART_1_AF 7
/** @} */ /** @} */
/** /**

125
cpu/stm32f4/include/periph_cpu.h
View File

@ -16,11 +16,10 @@
* @author Hauke Petersen <hauke.peterse@fu-berlin.de> * @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/ */
#ifndef CPU_PERIPH_H_ #ifndef PERIPH_CPU_H
#define CPU_PERIPH_H_ #define PERIPH_CPU_H
#include "cpu.h" #include "cpu.h"
#include "periph/dev_enums.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -44,6 +43,15 @@ typedef uint32_t gpio_t;
*/ */
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y) #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
/**
* @brief declare needed generic SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
/** /**
* @brief Available ports on the STM32F4 family * @brief Available ports on the STM32F4 family
*/ */
@ -80,6 +88,22 @@ typedef enum {
GPIO_AF14 /**< use alternate function 14 */ GPIO_AF14 /**< use alternate function 14 */
} gpio_af_t; } gpio_af_t;
/**
* @brief Structure for UART configuration data
* @{
*/
typedef struct {
USART_TypeDef *dev; /**< UART device base register address */
uint32_t rcc_mask; /**< bit in clock enable register */
gpio_t rx_pin; /**< RX pin */
gpio_t tx_pin; /**< TX pin */
gpio_af_t af; /**< alternate pin function to use */
uint8_t irqn; /**< IRQ channel */
uint8_t dma_stream; /**< DMA stream used for TX */
uint8_t dma_chan; /**< DMA channel used for TX */
} uart_conf_t;
/** @} */
/** /**
* @brief Configure the alternate function for the given pin * @brief Configure the alternate function for the given pin
* *
@ -91,17 +115,98 @@ typedef enum {
void gpio_init_af(gpio_t pin, gpio_af_t af); void gpio_init_af(gpio_t pin, gpio_af_t af);
/** /**
* @brief declare needed generic SPI functions * @brief Power on the DMA device the given stream belongs to
* @{ *
* @param[in] stream logical DMA stream
*/ */
#define PERIPH_SPI_NEEDS_TRANSFER_BYTES static inline void dma_poweron(int stream)
#define PERIPH_SPI_NEEDS_TRANSFER_REG {
#define PERIPH_SPI_NEEDS_TRANSFER_REGS if (stream < 8) {
/** @} */ RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
} else {
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
}
}
/**
* @brief Get DMA base register
*
* For simplifying DMA stream handling, we map the DMA channels transparently to
* one integer number, such that DMA1 stream0 equals 0, DMA2 stream0 equals 8,
* DMA2 stream 7 equals 15 and so on.
*
* @param[in] stream logical DMA stream
*/
static inline DMA_TypeDef *dma_base(int stream)
{
return (stream < 8) ? DMA1 : DMA2;
}
/**
* @brief Get the DMA stream base address
*
* @param[in] stream logical DMA stream
*
* @return base address for the selected DMA stream
*/
static inline DMA_Stream_TypeDef *dma_stream(int stream)
{
uint32_t base = (uint32_t)dma_base(stream);
return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
}
/**
* @brief Select high or low DMA interrupt register based on stream number
*
* @param[in] stream logical DMA stream
*
* @return 0 for streams 0-3, 1 for streams 3-7
*/
static inline int dma_hl(int stream)
{
return ((stream & 0x4) >> 2);
}
/**
* @brief Get the interrupt flag clear bit position in the DMA LIFCR register
*
* @param[in] stream logical DMA stream
*/
static inline uint32_t dma_ifc(int stream)
{
switch (stream & 0x3) {
case 0:
return (1 << 5);
case 1:
return (1 << 11);
case 2:
return (1 << 21);
case 3:
return (1 << 27);
default:
return 0;
}
}
static inline void dma_isr_enable(int stream)
{
if (stream < 7) {
NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
}
else if (stream == 8) {
NVIC_EnableIRQ(DMA1_Stream7_IRQn);
}
else if (stream < 14) {
NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + stream));
}
else if (stream < 17) {
NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + stream));
}
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* CPU_PERIPH_H_ */ #endif /* PERIPH_CPU_H */
/** @} */ /** @} */

6
cpu/stm32f4/include/stm32f401xe.h
View File

@ -241,10 +241,8 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t ISR[2]; /*!< DMA interrupt status registers, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t IFCR[2]; /*!< DMA interrupt flag clear registers, Address offset: 0x08 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef; } DMA_TypeDef;

6
cpu/stm32f4/include/stm32f407xx.h
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@ -371,10 +371,8 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t ISR[2]; /*!< DMA interrupt status registers, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t IFCR[2]; /*!< DMA interrupt flag clear registers, Address offset: 0x08 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef; } DMA_TypeDef;

6
cpu/stm32f4/include/stm32f415xx.h
View File

@ -351,10 +351,8 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t ISR[2]; /*!< DMA interrupt status registers, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t IFCR[2]; /*!< DMA interrupt flag clear registers, Address offset: 0x08 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef; } DMA_TypeDef;

333
cpu/stm32f4/periph/uart.c
View File

@ -1,9 +1,9 @@
/* /*
* Copyright (C) 2014-2015 Freie Universität Berlin * Copyright (C) 2014-2015 Freie Universität Berlin
* *
* This file is subject to the terms and conditions of the GNU Lesser General * This file is subject to the terms and conditions of the GNU Lesser
* Public License v2.1. See the file LICENSE in the top level directory for more * General Public License v2.1. See the file LICENSE in the top level
* details. * directory for more details.
*/ */
/** /**
@ -22,250 +22,211 @@
#include "cpu.h" #include "cpu.h"
#include "thread.h" #include "thread.h"
#include "sched.h" #include "sched.h"
#include "periph_conf.h" #include "mutex.h"
#include "periph/uart.h" #include "periph/uart.h"
#include "periph/gpio.h"
/** /**
* @brief Allocate memory to store the callback functions. * @brief Allocate memory to store the callback functions
*/ */
static uart_isr_ctx_t uart_config[UART_NUMOF]; static uart_isr_ctx_t uart_ctx[UART_NUMOF];
/** /**
* @todo Remodel this UART driver and merge init functions... * @brief Get the base register for the given UART device
*/ */
static int init_base(uart_t uart, uint32_t baudrate); static inline USART_TypeDef *_dev(uart_t uart)
{
return uart_config[uart].dev;
}
/**
* @brief Transmission locks
*/
static mutex_t tx_sync[UART_NUMOF];
/**
* @brief Find out which peripheral bus the UART device is connected to
*
* @return 1: APB1
* @return 2: APB2
*/
static inline int _bus(uart_t uart)
{
return (uart_config[uart].rcc_mask < RCC_APB1ENR_USART2EN) ? 2 : 1;
}
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{ {
/* do basic initialization */ USART_TypeDef *dev;
int res = init_base(uart, baudrate); DMA_Stream_TypeDef *stream;
if (res < 0) { float divider;
return res;
}
/* remember callback addresses */
uart_config[uart].rx_cb = rx_cb;
uart_config[uart].arg = arg;
/* enable receive interrupt */
switch (uart) {
#if UART_0_EN
case UART_0:
NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_0_IRQ_CHAN);
UART_0_DEV->CR1 |= USART_CR1_RXNEIE;
break;
#endif
#if UART_1_EN
case UART_1:
NVIC_SetPriority(UART_1_IRQ_CHAN, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_1_IRQ_CHAN);
UART_1_DEV->CR1 |= USART_CR1_RXNEIE;
break;
#endif
#if UART_2_EN
case UART_2:
NVIC_SetPriority(UART_2_IRQ_CHAN, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_2_IRQ_CHAN);
UART_2_DEV->CR1 |= USART_CR1_RXNEIE;
break;
#endif
}
return 0;
}
static int init_base(uart_t uart, uint32_t baudrate)
{
USART_TypeDef *dev = 0;
GPIO_TypeDef *port = 0;
uint32_t tx_pin = 0;
uint32_t rx_pin = 0;
uint8_t af = 0;
uint32_t clk = 0;
uint16_t mantissa; uint16_t mantissa;
uint8_t fraction; uint8_t fraction;
switch (uart) { /* check if given UART device does exist */
#if UART_0_EN if (uart < 0 || uart >= UART_NUMOF) {
case UART_0: return -1;
dev = UART_0_DEV;
port = UART_0_PORT;
clk = UART_0_CLK;
tx_pin = UART_0_TX_PIN;
rx_pin = UART_0_RX_PIN;
af = UART_0_AF;
UART_0_CLKEN();
UART_0_PORT_CLKEN();
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
port = UART_1_PORT;
clk = UART_1_CLK;
tx_pin = UART_1_TX_PIN;
rx_pin = UART_1_RX_PIN;
af = UART_1_AF;
UART_1_CLKEN();
UART_1_PORT_CLKEN();
break;
#endif
#if UART_2_EN
case UART_2:
dev = UART_2_DEV;
port = UART_2_PORT;
clk = UART_2_CLK;
tx_pin = UART_2_TX_PIN;
rx_pin = UART_2_RX_PIN;
af = UART_2_AF;
UART_2_CLKEN();
UART_2_PORT_CLKEN();
break;
#endif
default:
return -1;
} }
/* configure pp mode with no pull for RX and TX pins */ /* get UART base address */
port->OTYPER &= ~(1 << rx_pin | 1 << tx_pin); dev = _dev(uart);
port->PUPDR &= ~(3 << (rx_pin * 2) | 3 << (tx_pin * 2)); /* remember callback addresses and argument */
uart_ctx[uart].rx_cb = rx_cb;
uart_ctx[uart].arg = arg;
/* init tx lock */
mutex_init(&tx_sync[uart]);
mutex_lock(&tx_sync[uart]);
/* configure RX and TX pins, set pin to use alternative function mode */ /* configure pins */
port->MODER &= ~(3 << (rx_pin * 2) | 3 << (tx_pin * 2)); gpio_init(uart_config[uart].rx_pin, GPIO_DIR_IN, GPIO_NOPULL);
port->MODER |= 2 << (rx_pin * 2) | 2 << (tx_pin * 2); gpio_init(uart_config[uart].tx_pin, GPIO_DIR_OUT, GPIO_NOPULL);
/* and assign alternative function */ gpio_init_af(uart_config[uart].rx_pin, uart_config[uart].af);
if (rx_pin < 8) { gpio_init_af(uart_config[uart].tx_pin, uart_config[uart].af);
port->AFR[0] &= ~(0xf << (rx_pin * 4)); /* enable UART clock */
port->AFR[0] |= af << (rx_pin * 4); uart_poweron(uart);
/* calculate and set baudrate */
if (_bus(uart) == 1) {
divider = CLOCK_APB1 / (16 * baudrate);
} }
else { else {
port->AFR[1] &= ~(0xf << ((rx_pin - 8) * 4)); divider = CLOCK_APB2 / (16 * baudrate);
port->AFR[1] |= af << ((rx_pin - 8) * 4);
} }
if (tx_pin < 8) { mantissa = (uint16_t)divider;
port->AFR[0] &= ~(0xf << (tx_pin * 4)); fraction = (uint8_t)((divider - mantissa) * 16);
port->AFR[0] |= af << (tx_pin * 4);
}
else {
port->AFR[1] &= ~(0xf << ((tx_pin - 8) * 4));
port->AFR[1] |= af << ((tx_pin - 8) * 4);
}
/* configure UART to mode 8N1 with given baudrate */
clk /= baudrate;
mantissa = (uint16_t)(clk / 16);
fraction = (uint8_t)(clk - (mantissa * 16));
dev->BRR = ((mantissa & 0x0fff) << 4) | (0x0f & fraction); dev->BRR = ((mantissa & 0x0fff) << 4) | (0x0f & fraction);
/* configure UART to 8N1 and enable receive and transmit mode */
/* enable receive and transmit mode */ dev->CR3 = USART_CR3_DMAT;
dev->CR3 = 0;
dev->CR2 = 0; dev->CR2 = 0;
dev->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE; dev->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
/* configure the DMA stream for transmission */
dma_poweron(uart_config[uart].dma_stream);
stream = dma_stream(uart_config[uart].dma_stream);
stream->CR = ((uart_config[uart].dma_chan << 25) |
DMA_SxCR_PL_0 |
DMA_SxCR_MINC |
DMA_SxCR_DIR_0 |
DMA_SxCR_TCIE);
stream->PAR = (uint32_t)&(dev->DR);
stream->FCR = 0;
/* enable global and receive interrupts */
NVIC_EnableIRQ(uart_config[uart].irqn);
dma_isr_enable(uart_config[uart].dma_stream);
dev->CR1 |= USART_CR1_RXNEIE;
return 0; return 0;
} }
void uart_write(uart_t uart, const uint8_t *data, size_t len) void uart_write(uart_t uart, const uint8_t *data, size_t len)
{ {
USART_TypeDef *dev = 0; /* in case we are inside an ISR, we need to send blocking */
if (inISR()) {
switch (uart) { /* send data by active waiting on the TXE flag */
#if UART_0_EN USART_TypeDef *dev = _dev(uart);
case UART_0: for (int i = 0; i < len; i++) {
dev = UART_0_DEV; while (!(dev->SR & USART_SR_TXE));
break; dev->DR = data[i];
#endif }
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
break;
#endif
#if UART_2_EN
case UART_2:
dev = UART_2_DEV;
break;
#endif
default:
return;
} }
else {
for (size_t i = 0; i < len; i++) { DMA_Stream_TypeDef *stream = dma_stream(uart_config[uart].dma_stream);
while (!(dev->SR & USART_SR_TXE)); /* configure and start DMA transfer */
dev->DR = data[i]; stream->M0AR = (uint32_t)data;
stream->NDTR = (uint16_t)len;
stream->CR |= DMA_SxCR_EN;
/* wait for transfer to complete */
mutex_lock(&tx_sync[uart]);
} }
} }
void uart_poweron(uart_t uart) void uart_poweron(uart_t uart)
{ {
switch (uart) { if (_bus(uart) == 1) {
#if UART_0_EN RCC->APB1ENR |= uart_config[uart].rcc_mask;
case UART_0: }
UART_0_CLKEN(); else {
break; RCC->APB2ENR |= uart_config[uart].rcc_mask;
#endif
#if UART_1_EN
case UART_1:
UART_1_CLKEN();
break;
#endif
#if UART_2_EN
case UART_2:
UART_2_CLKEN();
break;
#endif
} }
} }
void uart_poweroff(uart_t uart) void uart_poweroff(uart_t uart)
{ {
switch (uart) { if (_bus(uart) == 1) {
#if UART_0_EN RCC->APB1ENR &= ~(uart_config[uart].rcc_mask);
case UART_0: }
UART_0_CLKDIS(); else {
break; RCC->APB2ENR &= ~(uart_config[uart].rcc_mask);
#endif
#if UART_1_EN
case UART_1:
UART_1_CLKDIS();
break;
#endif
#if UART_2_EN
case UART_2:
UART_2_CLKDIS();
break;
#endif
} }
} }
static inline void irq_handler(uint8_t uartnum, USART_TypeDef *dev) static inline void irq_handler(int uart, USART_TypeDef *dev)
{ {
if (dev->SR & USART_SR_RXNE) { if (dev->SR & USART_SR_RXNE) {
char data = (char)dev->DR; char data = (char)dev->DR;
uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data); uart_ctx[uart].rx_cb(uart_ctx[uart].arg, data);
} }
if (sched_context_switch_request) { if (sched_context_switch_request) {
thread_yield(); thread_yield();
} }
} }
#if UART_0_EN static inline void dma_handler(int uart, int stream)
{
/* clear DMA done flag */
dma_base(stream)->IFCR[dma_hl(stream)] = dma_ifc(stream);
mutex_unlock(&tx_sync[uart]);
if (sched_context_switch_request) {
thread_yield();
}
}
#ifdef UART_0_ISR
void UART_0_ISR(void) void UART_0_ISR(void)
{ {
irq_handler(UART_0, UART_0_DEV); irq_handler(0, uart_config[0].dev);
}
void UART_0_DMA_ISR(void)
{
dma_handler(0, uart_config[0].dma_stream);
} }
#endif #endif
#if UART_1_EN #ifdef UART_1_ISR
void UART_1_ISR(void) void UART_1_ISR(void)
{ {
irq_handler(UART_1, UART_1_DEV); irq_handler(1, uart_config[1].dev);
}
void UART_1_DMA_ISR(void)
{
dma_handler(1, uart_config[1].dma_stream);
} }
#endif #endif
#if UART_2_EN #ifdef UART_2_ISR
void UART_2_ISR(void) void UART_2_ISR(void)
{ {
irq_handler(UART_2, UART_2_DEV); irq_handler(2, uart_config[2].dev);
}
#endif
#ifdef UART_3_ISR
void UART_3_ISR(void)
{
irq_handler(3, uart_config[3].dev);
}
#endif
#ifdef UART_4_ISR
void UART_4_ISR(void)
{
irq_handler(4, uart_config[4].dev);
}
#endif
#ifdef UART_5_ISR
void UART_5_ISR(void)
{
irq_handler(5, uart_config[5].dev);
} }
#endif #endif