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cpu/cortexm: implement sched_arch_idle() and disable idle thread

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This commit is contained in:
Kaspar Schleiser 2020-06-08 12:36:01 +02:00
parent e3f6c0f340
commit 0ff9e554eb
3 changed files with 28 additions and 0 deletions
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2
cpu/cortexm_common/Kconfig
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@ -13,11 +13,13 @@ config CPU_ARCH_ARMV7M
bool bool
select HAS_ARCH_ARM select HAS_ARCH_ARM
select HAS_ARCH_32BIT select HAS_ARCH_32BIT
select HAS_NO_IDLE_THREAD
config CPU_ARCH_ARMV8M config CPU_ARCH_ARMV8M
bool bool
select HAS_ARCH_ARM select HAS_ARCH_ARM
select HAS_ARCH_32BIT select HAS_ARCH_32BIT
select HAS_NO_IDLE_THREAD
config CPU_ARCH config CPU_ARCH
default "armv6m" if CPU_ARCH_ARMV6M default "armv6m" if CPU_ARCH_ARMV6M

5
cpu/cortexm_common/Makefile.features
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@ -30,3 +30,8 @@ else ifeq ($(CPU_CORE),cortex-m23)
else else
$(error Unkwnown cortexm core: $(CPU_CORE)) $(error Unkwnown cortexm core: $(CPU_CORE))
endif endif
# cortex-m3 and higher don't need the idle thread
ifneq (,$(filter armv7m armv8m,$(CPU_ARCH)))
FEATURES_PROVIDED += no_idle_thread
endif

21
cpu/cortexm_common/thread_arch.c
View File

@ -446,3 +446,24 @@ void __attribute__((used)) isr_svc(void)
SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
} }
#endif /* MODULE_CORTEXM_SVC */ #endif /* MODULE_CORTEXM_SVC */
void sched_arch_idle(void)
{
/* by default, PendSV has the same priority as other ISRs.
* In this function, we temporarily lower the priority (set higher value),
* allowing other ISRs to interrupt.
*
* According to [this](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHJICIE.html),
* dynamically changing the priority is not supported on CortexM0(+).
*/
NVIC_SetPriority(PendSV_IRQn, CPU_CORTEXM_PENDSV_IRQ_PRIO + 1);
__DSB();
__ISB();
#ifdef MODULE_PM_LAYERED
void pm_set_lowest(void);
pm_set_lowest();
#else
__WFI();
#endif
NVIC_SetPriority(PendSV_IRQn, CPU_CORTEXM_PENDSV_IRQ_PRIO);
}