riot-ci/RIOT
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

cpu/cortex_common: added support for Cortex-M7

Browse Source
This commit is contained in:
Hauke Petersen 2017-04-13 14:31:43 +02:00
parent f914ae4876
commit 10a7486246
4 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
cpu/cortexm_common/cortexm_init.c
View File

@ -34,14 +34,14 @@ extern const void *_isr_vectors;
void cortexm_init(void)
{
/* initialize the FPU on Cortex-M4F CPUs */
#ifdef CPU_ARCH_CORTEX_M4F
#if defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
/* give full access to the FPU */
SCB->CPACR |= (uint32_t)FULL_FPU_ACCESS;
#endif
/* configure the vector table location to internal flash */
#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
defined(CPU_ARCH_CORTEX_M4F)
defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
SCB->VTOR = (uint32_t)&_isr_vectors;
#endif

2
cpu/cortexm_common/include/vectors_cortexm.h
View File

@ -74,7 +74,7 @@ void hard_fault_default(void);
/* The following four exceptions are only present for Cortex-M3 and -M4 CPUs */
#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
defined(CPU_ARCH_CORTEX_M4F)
defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
/**
* @brief Memory management exception handler
*

6
cpu/cortexm_common/thread_arch.c
View File

@ -149,7 +149,7 @@ char *thread_arch_stack_init(thread_task_func_t task_func,
*stk = ~((uint32_t)STACK_MARKER);
}
#ifdef CPU_ARCH_CORTEX_M4F
#if defined(CPU_ARCH_CORTEX_M4F) || (CPU_ARCH_CORTEX_M7)
/* TODO: fix FPU handling for Cortex-M4f */
/*
stk--;
@ -320,7 +320,7 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
#else
"stmdb r0!,{r4-r11} \n" /* save regs */
"stmdb r0!,{lr} \n" /* exception return value */
#ifdef CPU_ARCH_CORTEX_M4F
#if defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
/* "vstmdb sp!, {s16-s31} \n" */ /* TODO save FPU registers */
#endif
#endif
@ -365,7 +365,7 @@ void __attribute__((naked)) __attribute__((used)) isr_svc(void) {
"ldr r0, [r0] \n" /* dereference TCB */
"ldr r1, [r0] \n" /* load tcb->sp to register 1 */
"ldmia r1!, {r0} \n" /* restore exception return value */
#ifdef CPU_ARCH_CORTEX_M4F
#if defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
/* "pop {s16-s31} \n" */ /* TODO load FPU registers */
#endif
"ldmia r1!, {r4-r11} \n" /* restore other registers */

4
cpu/cortexm_common/vectors_cortexm.c
View File

@ -229,6 +229,8 @@ __attribute__((used)) void hard_fault_handler(uint32_t* sp, uint32_t corrupted,
/* Initialize these variables even if they're never used uninitialized.
* Fixes wrong compiler warning by gcc < 6.0. */
uint32_t pc = 0;
/* cppcheck-suppress variableScope
* variable used in assembly-code below */
uint32_t* orig_sp = NULL;
/* Check if the ISR stack overflowed previously. Not possible to detect
@ -340,7 +342,7 @@ void hard_fault_default(void)
#endif /* DEVELHELP */
#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
defined(CPU_ARCH_CORTEX_M4F)
defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
void mem_manage_default(void)
{
core_panic(PANIC_MEM_MANAGE, "MEM MANAGE HANDLER");