Merge pull request #7658 from OTAkeys/pr/stm32_dma
cpu/stm32_common: add DMA implementation for F2/F4/F7
This commit is contained in:
Alexandre Abadie
GitHub
commit
127d41e2b4
@ -1,5 +1,6 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_dma
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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@ -71,6 +71,29 @@ extern "C" {
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#define CLOCK_USE_ALT_48MHZ (1)
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/** @} */
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/**
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* @name DMA streams configuration
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* @{
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*/
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#ifdef MODULE_PERIPH_DMA
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static const dma_conf_t dma_config[] = {
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{ .stream = 4 },
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{ .stream = 14 },
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{ .stream = 6 },
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{ .stream = 10 },
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{ .stream = 8 },
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};
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#define DMA_0_ISR isr_dma1_stream4
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#define DMA_1_ISR isr_dma2_stream6
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#define DMA_2_ISR isr_dma1_stream6
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#define DMA_3_ISR isr_dma2_stream2
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#define DMA_4_ISR isr_dma2_stream0
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#define DMA_NUMOF (sizeof(dma_config) / sizeof(dma_config[0]))
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#endif
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/** @} */
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/**
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* @name Timer configuration
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* @{
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@ -104,9 +127,9 @@ static const uart_conf_t uart_config[] = {
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#ifdef MODULE_PERIPH_DMA
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.dma = 0,
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.dma_chan = 7,
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#endif
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},
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{
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@ -118,9 +141,9 @@ static const uart_conf_t uart_config[] = {
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.tx_af = GPIO_AF8,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 5,
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.dma_chan = 4
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#ifdef MODULE_PERIPH_DMA
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.dma = 1,
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.dma_chan = 5,
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#endif
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},
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{
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@ -132,9 +155,9 @@ static const uart_conf_t uart_config[] = {
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 4,
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.dma_chan = 4
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#ifdef MODULE_PERIPH_DMA
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.dma = 3,
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.dma_chan = 4,
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#endif
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},
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};
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@ -212,7 +235,13 @@ static const spi_conf_t spi_config[] = {
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.cs_pin = GPIO_PIN(PORT_A, 4),
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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.apbbus = APB2,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 3,
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.tx_dma_chan = 2,
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.rx_dma = 4,
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.rx_dma_chan = 3,
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#endif
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}
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};
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@ -3,6 +3,7 @@
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* 2014 Freie Universität Berlin
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* 2016 TriaGnoSys GmbH
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* 2018 Kaspar Schleiser <kaspar@schleiser.de>
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* 2018 OTA keys S.A.
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*
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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@ -24,6 +25,7 @@
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Víctor Ariño <victor.arino@zii.aero>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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*
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* @}
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*/
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@ -47,6 +49,10 @@ void cpu_init(void)
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periph_clk_en(APB1, BIT_APB_PWREN);
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/* initialize the system clock as configured in the periph_conf.h */
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stmclk_init_sysclk();
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#ifdef MODULE_PERIPH_DMA
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/* initialize DMA streams */
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dma_init();
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#endif
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/* trigger static peripheral initialization */
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periph_init();
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}
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@ -218,6 +218,49 @@ typedef enum {
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#endif /* ndef DOXYGEN */
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#endif /* ndef CPU_FAM_STM32F1 */
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#ifdef MODULE_PERIPH_DMA
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/**
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* @brief DMA configuration
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*/
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typedef struct {
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int stream; /**< DMA stream */
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} dma_conf_t;
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/**
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* @brief DMA type
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*/
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typedef unsigned dma_t;
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/**
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* @brief DMA modes
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*/
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typedef enum {
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DMA_PERIPH_TO_MEM, /**< Peripheral to memory */
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DMA_MEM_TO_PERIPH, /**< Memory to peripheral */
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DMA_MEM_TO_MEM, /**< Memory to memory */
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} dma_mode_t;
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/**
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* @name DMA Increment modes
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* @{
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*/
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#define DMA_INC_SRC_ADDR (0x01)
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#define DMA_INC_DST_ADDR (0x02)
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#define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
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/** @} */
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/**
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* @name DMA data width
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* @{
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*/
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#define DMA_DATA_WIDTH_BYTE (0x00)
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#define DMA_DATA_WIDTH_HALF_WORD (0x04)
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#define DMA_DATA_WIDTH_WORD (0x08)
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#define DMA_DATA_WIDTH_MASK (0x0C)
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#define DMA_DATA_WIDTH_SHIFT (2)
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/** @} */
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#endif /* MODULE_PERIPH_DMA */
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/**
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* @brief DAC line configuration data
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*/
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@ -293,8 +336,8 @@ typedef struct {
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#endif
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uint8_t bus; /**< APB bus */
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uint8_t irqn; /**< IRQ channel */
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#if 0 /* TODO */
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uint8_t dma_stream; /**< DMA stream used for TX */
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#ifdef MODULE_PERIPH_DMA
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dma_t dma; /**< Logical DMA stream used for TX */
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uint8_t dma_chan; /**< DMA channel used for TX */
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#endif
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#ifdef MODULE_STM32_PERIPH_UART_HW_FC
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@ -321,8 +364,15 @@ typedef struct {
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#endif
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uint32_t rccmask; /**< bit in the RCC peripheral enable register */
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uint8_t apbbus; /**< APBx bus the device is connected to */
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#ifdef MODULE_PERIPH_DMA
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dma_t tx_dma; /**< Logical DMA stream used for TX */
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uint8_t tx_dma_chan; /**< DMA channel used for TX */
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dma_t rx_dma; /**< Logical DMA stream used for RX */
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uint8_t rx_dma_chan; /**< DMA channel used for RX */
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#endif
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} spi_conf_t;
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/**
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* @brief Get the actual bus clock frequency for the APB buses
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*
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@ -372,6 +422,247 @@ void gpio_init_af(gpio_t pin, gpio_af_t af);
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*/
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void gpio_init_analog(gpio_t pin);
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#ifdef MODULE_PERIPH_DMA
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/**
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* @brief DMA stream not defined
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*/
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#define DMA_STREAM_UNDEF (UINT_MAX)
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/**
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* @brief Initialize DMA
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*/
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void dma_init(void);
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/**
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* @brief Execute a DMA transfer
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*
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* This function blocks until the transfer is completed. This is a convenience
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* function which configure, start, wait and stop a DMA transfer.
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*
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* @param[in] dma logical DMA stream
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* @param[in] chan DMA channel
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* @param[in] src source buffer
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* @param[out] dst destination buffer
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* @param[in] len length to transfer
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* @param[in] mode DMA mode
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* @param[in] flags DMA configuration
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*
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* @return < 0 on error, the number of transfered bytes otherwise
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*/
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int dma_transfer(dma_t dma, int chan, const void *src, void *dst, size_t len,
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dma_mode_t mode, uint8_t flags);
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/**
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* @brief Acquire a DMA stream
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_acquire(dma_t dma);
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/**
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* @brief Release a DMA stream
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_release(dma_t dma);
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/**
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* @brief Start a DMA transfer on a stream
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*
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* Start a DMA transfer on a given stream. The stream must be configured first
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* by a @p dma_configure call.
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_start(dma_t dma);
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/**
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* @brief Suspend a DMA transfer on a stream
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*
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* @param[in] dma logical DMA stream
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*
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* @return the remaining number of bytes to transfer
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*/
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uint16_t dma_suspend(dma_t dma);
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/**
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* @brief Resume a suspended DMA transfer on a stream
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*
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* @param[in] dma logical DMA stream
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* @param[in] reamaining the remaining number of bytes to transfer
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*/
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void dma_resume(dma_t dma, uint16_t remaining);
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/**
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* @brief Stop a DMA transfer on a stream
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_stop(dma_t dma);
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/**
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* @brief Wait for the end of a transfer
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_wait(dma_t dma);
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/**
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* @brief Configure a DMA stream for a new transfer
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*
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* @param[in] dma logical DMA stream
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* @param[in] chan DMA channel
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* @param[in] src source buffer
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* @param[out] dst destination buffer
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* @param[in] len length to transfer
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* @param[in] mode DMA mode
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* @param[in] flags DMA configuration
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*
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* @return < 0 on error, 0 on success
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*/
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int dma_configure(dma_t dma, int chan, const void *src, void *dst, size_t len,
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dma_mode_t mode, uint8_t flags);
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/**
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* @brief Get DMA base register
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*
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* For simplifying DMA stream handling, we map the DMA channels transparently to
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* one integer number, such that DMA1 stream0 equals 0, DMA2 stream0 equals 8,
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* DMA2 stream 7 equals 15 and so on.
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*
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* @param[in] stream physical DMA stream
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*/
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static inline DMA_TypeDef *dma_base(int stream)
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{
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return (stream < 8) ? DMA1 : DMA2;
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}
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/**
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* @brief Power on the DMA device the given stream belongs to
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*
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* @param[in] stream physical DMA stream
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*/
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static inline void dma_poweron(int stream)
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{
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if (stream < 8) {
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periph_clk_en(AHB1, RCC_AHB1ENR_DMA1EN);
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}
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else {
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periph_clk_en(AHB1, RCC_AHB1ENR_DMA2EN);
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}
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}
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/**
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* @brief Get the DMA stream base address
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*
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* @param[in] stream physical DMA stream
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*
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* @return base address for the selected DMA stream
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*/
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static inline DMA_Stream_TypeDef *dma_stream(int stream)
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{
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uint32_t base = (uint32_t)dma_base(stream);
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return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
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}
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/**
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* @brief Select high or low DMA interrupt register based on stream number
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*
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* @param[in] stream physical DMA stream
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*
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* @return 0 for streams 0-3, 1 for streams 3-7
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*/
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static inline int dma_hl(int stream)
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{
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return ((stream & 0x4) >> 2);
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}
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/**
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* @brief Get the interrupt flag clear bit position in the DMA LIFCR register
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*
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* @param[in] stream physical DMA stream
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*/
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static inline uint32_t dma_ifc(int stream)
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{
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switch (stream & 0x3) {
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case 0:
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return (1 << 5);
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case 1:
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return (1 << 11);
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case 2:
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return (1 << 21);
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case 3:
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return (1 << 27);
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default:
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return 0;
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}
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}
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/**
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* @brief Enable the interrupt of a given stream
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*
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* @param[in] stream physical DMA stream
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*/
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static inline void dma_isr_enable(int stream)
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{
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if (stream < 7) {
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NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
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}
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else if (stream == 7) {
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NVIC_EnableIRQ(DMA1_Stream7_IRQn);
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}
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else if (stream < 13) {
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NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
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}
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else if (stream < 16) {
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NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
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}
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}
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/**
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* @brief Disable the interrupt of a given stream
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*
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* @param[in] stream physical DMA stream
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*/
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static inline void dma_isr_disable(int stream)
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{
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if (stream < 7) {
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NVIC_DisableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
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}
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else if (stream == 7) {
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NVIC_DisableIRQ(DMA1_Stream7_IRQn);
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}
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else if (stream < 13) {
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NVIC_DisableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
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}
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else if (stream < 16) {
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NVIC_DisableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
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}
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}
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/**
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* @brief Clear the interrupt of a given stream
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*
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* @param[in] stream physical DMA stream
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*/
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static inline void dma_isr_clear(int stream)
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{
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if (stream < 7) {
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NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
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}
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else if (stream == 7) {
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NVIC_ClearPendingIRQ((IRQn_Type)DMA1_Stream7_IRQn);
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}
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else if (stream < 13) {
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NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
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}
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else if (stream < 16) {
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NVIC_ClearPendingIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
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}
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}
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#endif /* MODULE_PERIPH_DMA */
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#ifdef __cplusplus
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}
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#endif
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306
cpu/stm32_common/periph/dma.c
Normal file
306
cpu/stm32_common/periph/dma.c
Normal file
@ -0,0 +1,306 @@
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/*
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* Copyright (C) 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
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* General Public License v2.1. See the file LICENSE in the top level
|
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32_common
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* @{
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*
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* @file
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* @brief Low-level DMA driver implementation
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include "periph_cpu.h"
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#include "periph_conf.h"
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#include "mutex.h"
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#include "assert.h"
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#if !(defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7))
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#error "DMA is not supported for target CPU"
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#endif
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#define DMA_STREAM_IT_MASK (DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
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DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
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DMA_LISR_TCIF0)
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struct dma_ctx {
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mutex_t conf_lock;
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mutex_t sync_lock;
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uint16_t len;
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};
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static struct dma_ctx dma_ctx[DMA_NUMOF];
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static inline uint32_t dma_all_flags(dma_t dma)
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{
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assert(dma < DMA_NUMOF);
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switch (dma_config[dma].stream & 0x3) {
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case 0: /* 0 and 4 */
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return (DMA_STREAM_IT_MASK);
|
||||
case 1: /* 1 and 5 */
|
||||
return (DMA_STREAM_IT_MASK << 6);
|
||||
case 2: /* 2 and 6 */
|
||||
return (DMA_STREAM_IT_MASK << 16);
|
||||
case 3: /* 3 and 7 */
|
||||
return (DMA_STREAM_IT_MASK << 22);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void dma_clear_all_flags(dma_t dma)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
DMA_TypeDef *stream = dma_base(dma_config[dma].stream);
|
||||
|
||||
/* Clear all flags */
|
||||
if (dma_hl(dma_config[dma].stream) == 0) {
|
||||
stream->LIFCR = dma_all_flags(dma);
|
||||
}
|
||||
else {
|
||||
stream->HIFCR = dma_all_flags(dma);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dma_init(void)
|
||||
{
|
||||
for (unsigned i = 0; i < DMA_NUMOF; i++) {
|
||||
mutex_init(&dma_ctx[i].conf_lock);
|
||||
mutex_init(&dma_ctx[i].sync_lock);
|
||||
mutex_lock(&dma_ctx[i].sync_lock);
|
||||
}
|
||||
}
|
||||
|
||||
int dma_transfer(dma_t dma, int chan, const void *src, void *dst, size_t len,
|
||||
dma_mode_t mode, uint8_t flags)
|
||||
{
|
||||
int ret = dma_configure(dma, chan, src, dst, len, mode, flags);
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
dma_start(dma);
|
||||
dma_wait(dma);
|
||||
dma_stop(dma);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
void dma_acquire(dma_t dma)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
mutex_lock(&dma_ctx[dma].conf_lock);
|
||||
}
|
||||
|
||||
void dma_release(dma_t dma)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
mutex_unlock(&dma_ctx[dma].conf_lock);
|
||||
}
|
||||
|
||||
int dma_configure(dma_t dma, int chan, const void *src, void *dst, size_t len,
|
||||
dma_mode_t mode, uint8_t flags)
|
||||
{
|
||||
assert(src != NULL);
|
||||
assert(dst != NULL);
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
int stream_n = dma_config[dma].stream;
|
||||
uint32_t inc_periph;
|
||||
uint32_t inc_mem;
|
||||
|
||||
DMA_Stream_TypeDef *stream = dma_stream(stream_n);
|
||||
dma_poweron(stream_n);
|
||||
dma_clear_all_flags(dma);
|
||||
|
||||
switch (mode) {
|
||||
case DMA_MEM_TO_MEM:
|
||||
case DMA_PERIPH_TO_MEM:
|
||||
stream->PAR = (uint32_t)src;
|
||||
stream->M0AR = (uint32_t)dst;
|
||||
inc_periph = (flags & DMA_INC_SRC_ADDR);
|
||||
inc_mem = (flags & DMA_INC_DST_ADDR) >> 1;
|
||||
break;
|
||||
case DMA_MEM_TO_PERIPH:
|
||||
stream->PAR = (uint32_t)dst;
|
||||
stream->M0AR = (uint32_t)src;
|
||||
inc_periph = (flags & DMA_INC_DST_ADDR) >> 1;
|
||||
inc_mem = (flags & DMA_INC_SRC_ADDR);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
uint32_t width = (flags & DMA_DATA_WIDTH_MASK) >> DMA_DATA_WIDTH_SHIFT;
|
||||
/* Set channel, data width, inc and mode */
|
||||
stream->CR = (chan & 0xF) << DMA_SxCR_CHSEL_Pos |
|
||||
width << DMA_SxCR_MSIZE_Pos | width << DMA_SxCR_PSIZE_Pos |
|
||||
inc_periph << DMA_SxCR_PINC_Pos | inc_mem << DMA_SxCR_MINC_Pos |
|
||||
(mode & 3) << DMA_SxCR_DIR_Pos;
|
||||
/* Enable interrupts */
|
||||
stream->CR |= DMA_SxCR_TCIE | DMA_SxCR_TEIE;
|
||||
/* Configure FIFO */
|
||||
stream->FCR = 0;
|
||||
|
||||
/* Set length */
|
||||
stream->NDTR = len;
|
||||
dma_ctx[dma].len = len;
|
||||
|
||||
dma_isr_enable(stream_n);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dma_start(dma_t dma)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
DMA_Stream_TypeDef *stream = dma_stream(dma_config[dma].stream);
|
||||
|
||||
stream->CR |= DMA_SxCR_EN;
|
||||
}
|
||||
|
||||
uint16_t dma_suspend(dma_t dma)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
int stream_n = dma_config[dma].stream;
|
||||
DMA_Stream_TypeDef *stream = dma_stream(stream_n);
|
||||
uint16_t left = 0;
|
||||
|
||||
if ((stream->CR & DMA_SxCR_EN) == DMA_SxCR_EN) {
|
||||
dma_isr_disable(stream_n);
|
||||
stream->CR &= ~(uint32_t)DMA_SxCR_EN;
|
||||
while ((stream->CR & DMA_SxCR_EN) == DMA_SxCR_EN) {}
|
||||
dma_clear_all_flags(dma);
|
||||
left = stream->NDTR;
|
||||
dma_isr_clear(stream_n);
|
||||
}
|
||||
return left;
|
||||
|
||||
}
|
||||
|
||||
void dma_resume(dma_t dma, uint16_t remaining)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
int stream_n = dma_config[dma].stream;
|
||||
DMA_Stream_TypeDef *stream = dma_stream(stream_n);
|
||||
|
||||
if (remaining > 0) {
|
||||
dma_isr_enable(stream_n);
|
||||
stream->NDTR = remaining;
|
||||
stream->M0AR += dma_ctx[dma].len - remaining;
|
||||
dma_ctx[dma].len = remaining;
|
||||
stream->CR |= (uint32_t)DMA_SxCR_EN;
|
||||
}
|
||||
}
|
||||
|
||||
void dma_stop(dma_t dma)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
DMA_Stream_TypeDef *stream = dma_stream(dma_config[dma].stream);
|
||||
|
||||
stream->CR &= ~(uint32_t)DMA_SxCR_EN;
|
||||
}
|
||||
|
||||
void dma_wait(dma_t dma)
|
||||
{
|
||||
assert(dma < DMA_NUMOF);
|
||||
|
||||
mutex_lock(&dma_ctx[dma].sync_lock);
|
||||
}
|
||||
|
||||
void dma_isr_handler(dma_t dma)
|
||||
{
|
||||
dma_clear_all_flags(dma);
|
||||
|
||||
mutex_unlock(&dma_ctx[dma].sync_lock);
|
||||
|
||||
cortexm_isr_end();
|
||||
}
|
||||
|
||||
#ifdef DMA_0_ISR
|
||||
void DMA_0_ISR(void)
|
||||
{
|
||||
dma_isr_handler(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_1_ISR
|
||||
void DMA_1_ISR(void)
|
||||
{
|
||||
dma_isr_handler(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_2_ISR
|
||||
void DMA_2_ISR(void)
|
||||
{
|
||||
dma_isr_handler(2);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_3_ISR
|
||||
void DMA_3_ISR(void)
|
||||
{
|
||||
dma_isr_handler(3);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_4_ISR
|
||||
void DMA_4_ISR(void)
|
||||
{
|
||||
dma_isr_handler(4);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_5_ISR
|
||||
void DMA_5_ISR(void)
|
||||
{
|
||||
dma_isr_handler(5);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_6_ISR
|
||||
void DMA_6_ISR(void)
|
||||
{
|
||||
dma_isr_handler(6);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_7_ISR
|
||||
void DMA_7_ISR(void)
|
||||
{
|
||||
dma_isr_handler(7);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_8_ISR
|
||||
void DMA_8_ISR(void)
|
||||
{
|
||||
dma_isr_handler(8);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DMA_9_ISR
|
||||
void DMA_9_ISR(void)
|
||||
{
|
||||
dma_isr_handler(9);
|
||||
}
|
||||
#endif
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Hamburg University of Applied Sciences
|
||||
* 2014-2017 Freie Universität Berlin
|
||||
* 2016 OTA keys S.A.
|
||||
* 2016-2017 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
@ -152,24 +152,65 @@ void spi_release(spi_t bus)
|
||||
mutex_unlock(&locks[bus]);
|
||||
}
|
||||
|
||||
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
|
||||
const void *out, void *in, size_t len)
|
||||
static inline void _wait_for_end(spi_t bus)
|
||||
{
|
||||
/* make sure the transfer is completed before continuing, see reference
|
||||
* manual(s) -> section 'Disabling the SPI' */
|
||||
while (!(dev(bus)->SR & SPI_SR_TXE)) {}
|
||||
while (dev(bus)->SR & SPI_SR_BSY) {}
|
||||
}
|
||||
|
||||
#ifdef MODULE_PERIPH_DMA
|
||||
static void _transfer_dma(spi_t bus, const void *out, void *in, size_t len)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
dma_acquire(spi_config[bus].tx_dma);
|
||||
dma_acquire(spi_config[bus].rx_dma);
|
||||
|
||||
if (!out) {
|
||||
dma_configure(spi_config[bus].tx_dma, spi_config[bus].tx_dma_chan, &tmp,
|
||||
(void *)&(dev(bus)->DR), len, DMA_MEM_TO_PERIPH, 0);
|
||||
}
|
||||
else {
|
||||
dma_configure(spi_config[bus].tx_dma, spi_config[bus].tx_dma_chan, out,
|
||||
(void *)&(dev(bus)->DR), len, DMA_MEM_TO_PERIPH, DMA_INC_SRC_ADDR);
|
||||
}
|
||||
if (!in) {
|
||||
dma_configure(spi_config[bus].rx_dma, spi_config[bus].rx_dma_chan,
|
||||
(void *)&(dev(bus)->DR), &tmp, len, DMA_PERIPH_TO_MEM, 0);
|
||||
}
|
||||
else {
|
||||
dma_configure(spi_config[bus].rx_dma, spi_config[bus].rx_dma_chan,
|
||||
(void *)&(dev(bus)->DR), in, len, DMA_PERIPH_TO_MEM, DMA_INC_DST_ADDR);
|
||||
}
|
||||
dev(bus)->CR2 |= SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN;
|
||||
|
||||
dma_start(spi_config[bus].rx_dma);
|
||||
dma_start(spi_config[bus].tx_dma);
|
||||
|
||||
dma_wait(spi_config[bus].rx_dma);
|
||||
dma_wait(spi_config[bus].tx_dma);
|
||||
|
||||
dev(bus)->CR2 &= ~(SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
|
||||
|
||||
dma_stop(spi_config[bus].tx_dma);
|
||||
dma_stop(spi_config[bus].rx_dma);
|
||||
|
||||
dma_release(spi_config[bus].tx_dma);
|
||||
dma_release(spi_config[bus].rx_dma);
|
||||
|
||||
_wait_for_end(bus);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void _transfer_no_dma(spi_t bus, const void *out, void *in, size_t len)
|
||||
{
|
||||
const uint8_t *outbuf = out;
|
||||
uint8_t *inbuf = in;
|
||||
|
||||
/* make sure at least one input or one output buffer is given */
|
||||
assert(outbuf || inbuf);
|
||||
|
||||
/* we need to recast the data register to uint_8 to force 8-bit access */
|
||||
volatile uint8_t *DR = (volatile uint8_t*)&(dev(bus)->DR);
|
||||
|
||||
/* active the given chip select line */
|
||||
dev(bus)->CR1 |= (SPI_CR1_SPE); /* this pulls the HW CS line low */
|
||||
if ((cs != SPI_HWCS_MASK) && (cs != SPI_CS_UNDEF)) {
|
||||
gpio_clear((gpio_t)cs);
|
||||
}
|
||||
|
||||
/* transfer data, use shortpath if only sending data */
|
||||
if (!inbuf) {
|
||||
for (size_t i = 0; i < len; i++) {
|
||||
@ -200,10 +241,32 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure the transfer is completed before continuing, see reference
|
||||
* manual(s) -> section 'Disabling the SPI' */
|
||||
while (!(dev(bus)->SR & SPI_SR_TXE)) {}
|
||||
while (dev(bus)->SR & SPI_SR_BSY) {}
|
||||
_wait_for_end(bus);
|
||||
}
|
||||
|
||||
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
|
||||
const void *out, void *in, size_t len)
|
||||
{
|
||||
/* make sure at least one input or one output buffer is given */
|
||||
assert(out || in);
|
||||
|
||||
/* active the given chip select line */
|
||||
dev(bus)->CR1 |= (SPI_CR1_SPE); /* this pulls the HW CS line low */
|
||||
if ((cs != SPI_HWCS_MASK) && (cs != SPI_CS_UNDEF)) {
|
||||
gpio_clear((gpio_t)cs);
|
||||
}
|
||||
|
||||
#ifdef MODULE_PERIPH_DMA
|
||||
if (spi_config[bus].tx_dma != DMA_STREAM_UNDEF
|
||||
&& spi_config[bus].rx_dma != DMA_STREAM_UNDEF) {
|
||||
_transfer_dma(bus, out, in, len);
|
||||
}
|
||||
else {
|
||||
#endif
|
||||
_transfer_no_dma(bus, out, in, len);
|
||||
#ifdef MODULE_PERIPH_DMA
|
||||
}
|
||||
#endif
|
||||
|
||||
/* release the chip select if not specified differently */
|
||||
if ((!cont) && (cs != SPI_CS_UNDEF)) {
|
||||
|
||||
@ -118,24 +118,21 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
|
||||
return UART_OK;
|
||||
}
|
||||
|
||||
void uart_write(uart_t uart, const uint8_t *data, size_t len)
|
||||
static inline void send_byte(uart_t uart, uint8_t byte)
|
||||
{
|
||||
assert(uart < UART_NUMOF);
|
||||
|
||||
for (size_t i = 0; i < len; i++) {
|
||||
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
|
||||
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
|
||||
|| defined(CPU_FAM_STM32F7)
|
||||
while (!(dev(uart)->ISR & USART_ISR_TXE)) {}
|
||||
dev(uart)->TDR = data[i];
|
||||
dev(uart)->TDR = byte;
|
||||
#else
|
||||
while (!(dev(uart)->SR & USART_SR_TXE)) {}
|
||||
dev(uart)->DR = data[i];
|
||||
dev(uart)->DR = byte;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure the function is synchronous by waiting for the transfer to
|
||||
* finish */
|
||||
static inline void wait_for_tx_complete(uart_t uart)
|
||||
{
|
||||
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
|
||||
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
|
||||
|| defined(CPU_FAM_STM32F7)
|
||||
@ -145,6 +142,57 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
|
||||
#endif
|
||||
}
|
||||
|
||||
void uart_write(uart_t uart, const uint8_t *data, size_t len)
|
||||
{
|
||||
assert(uart < UART_NUMOF);
|
||||
|
||||
#ifdef MODULE_PERIPH_DMA
|
||||
if (!len) {
|
||||
return;
|
||||
}
|
||||
if (uart_config[uart].dma != DMA_STREAM_UNDEF) {
|
||||
if (irq_is_in()) {
|
||||
uint16_t todo = 0;
|
||||
if (dev(uart)->CR3 & USART_CR3_DMAT) {
|
||||
/* DMA transfer for UART on-going */
|
||||
todo = dma_suspend(uart_config[uart].dma);
|
||||
}
|
||||
if (todo) {
|
||||
dma_stop(uart_config[uart].dma);
|
||||
dev(uart)->CR3 &= ~USART_CR3_DMAT;
|
||||
}
|
||||
for (unsigned i = 0; i < len; i++) {
|
||||
send_byte(uart, data[i]);
|
||||
}
|
||||
if (todo > 0) {
|
||||
wait_for_tx_complete(uart);
|
||||
dev(uart)->CR3 |= USART_CR3_DMAT;
|
||||
dma_resume(uart_config[uart].dma, todo);
|
||||
}
|
||||
}
|
||||
else {
|
||||
dma_acquire(uart_config[uart].dma);
|
||||
dev(uart)->CR3 |= USART_CR3_DMAT;
|
||||
dma_transfer(uart_config[uart].dma, uart_config[uart].dma_chan, data,
|
||||
(void *)&dev(uart)->DR, len, DMA_MEM_TO_PERIPH, DMA_INC_SRC_ADDR);
|
||||
dma_release(uart_config[uart].dma);
|
||||
|
||||
/* make sure the function is synchronous by waiting for the transfer to
|
||||
* finish */
|
||||
wait_for_tx_complete(uart);
|
||||
dev(uart)->CR3 &= ~USART_CR3_DMAT;
|
||||
}
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
for (size_t i = 0; i < len; i++) {
|
||||
send_byte(uart, data[i]);
|
||||
}
|
||||
/* make sure the function is synchronous by waiting for the transfer to
|
||||
* finish */
|
||||
wait_for_tx_complete(uart);
|
||||
}
|
||||
|
||||
void uart_poweron(uart_t uart)
|
||||
{
|
||||
assert(uart < UART_NUMOF);
|
||||
|
||||
@ -76,101 +76,6 @@ typedef enum {
|
||||
} adc_res_t;
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Power on the DMA device the given stream belongs to
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*/
|
||||
static inline void dma_poweron(int stream)
|
||||
{
|
||||
if (stream < 8) {
|
||||
periph_clk_en(AHB1, RCC_AHB1ENR_DMA1EN);
|
||||
} else {
|
||||
periph_clk_en(AHB1, RCC_AHB1ENR_DMA2EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DMA base register
|
||||
*
|
||||
* For simplifying DMA stream handling, we map the DMA channels transparently to
|
||||
* one integer number, such that DMA1 stream0 equals 0, DMA2 stream0 equals 8,
|
||||
* DMA2 stream 7 equals 15 and so on.
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*/
|
||||
static inline DMA_TypeDef *dma_base(int stream)
|
||||
{
|
||||
return (stream < 8) ? DMA1 : DMA2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the DMA stream base address
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*
|
||||
* @return base address for the selected DMA stream
|
||||
*/
|
||||
static inline DMA_Stream_TypeDef *dma_stream(int stream)
|
||||
{
|
||||
uint32_t base = (uint32_t)dma_base(stream);
|
||||
return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select high or low DMA interrupt register based on stream number
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*
|
||||
* @return 0 for streams 0-3, 1 for streams 3-7
|
||||
*/
|
||||
static inline int dma_hl(int stream)
|
||||
{
|
||||
return ((stream & 0x4) >> 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the interrupt flag clear bit position in the DMA LIFCR register
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*/
|
||||
static inline uint32_t dma_ifc(int stream)
|
||||
{
|
||||
switch (stream & 0x3) {
|
||||
case 0: /* 0 and 4 */
|
||||
return (1 << 5);
|
||||
case 1: /* 1 and 5 */
|
||||
return (1 << 11);
|
||||
case 2: /* 2 and 6 */
|
||||
return (1 << 21);
|
||||
case 3: /* 3 and 7 */
|
||||
return (1 << 27);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA interrupts
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*/
|
||||
static inline void dma_isr_enable(int stream)
|
||||
{
|
||||
if (stream < 7) {
|
||||
NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
|
||||
}
|
||||
else if (stream == 7) {
|
||||
NVIC_EnableIRQ(DMA1_Stream7_IRQn);
|
||||
}
|
||||
else if (stream < 13) {
|
||||
NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
|
||||
}
|
||||
else if (stream < 16) {
|
||||
NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -89,98 +89,6 @@ typedef struct {
|
||||
uint8_t chan; /**< CPU ADC channel connected to the pin */
|
||||
} adc_conf_t;
|
||||
|
||||
/**
|
||||
* @brief Power on the DMA device the given stream belongs to
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*/
|
||||
static inline void dma_poweron(int stream)
|
||||
{
|
||||
if (stream < 8) {
|
||||
periph_clk_en(AHB1, RCC_AHB1ENR_DMA1EN);
|
||||
}
|
||||
else {
|
||||
periph_clk_en(AHB1, RCC_AHB1ENR_DMA2EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DMA base register
|
||||
*
|
||||
* For simplifying DMA stream handling, we map the DMA channels transparently to
|
||||
* one integer number, such that DMA1 stream0 equals 0, DMA2 stream0 equals 8,
|
||||
* DMA2 stream 7 equals 15 and so on.
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*/
|
||||
static inline DMA_TypeDef *dma_base(int stream)
|
||||
{
|
||||
return (stream < 8) ? DMA1 : DMA2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the DMA stream base address
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*
|
||||
* @return base address for the selected DMA stream
|
||||
*/
|
||||
static inline DMA_Stream_TypeDef *dma_stream(int stream)
|
||||
{
|
||||
uint32_t base = (uint32_t)dma_base(stream);
|
||||
|
||||
return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select high or low DMA interrupt register based on stream number
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*
|
||||
* @return 0 for streams 0-3, 1 for streams 3-7
|
||||
*/
|
||||
static inline int dma_hl(int stream)
|
||||
{
|
||||
return ((stream & 0x4) >> 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the interrupt flag clear bit position in the DMA LIFCR register
|
||||
*
|
||||
* @param[in] stream logical DMA stream
|
||||
*/
|
||||
static inline uint32_t dma_ifc(int stream)
|
||||
{
|
||||
switch (stream & 0x3) {
|
||||
case 0:
|
||||
return (1 << 5);
|
||||
case 1:
|
||||
return (1 << 11);
|
||||
case 2:
|
||||
return (1 << 21);
|
||||
case 3:
|
||||
return (1 << 27);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void dma_isr_enable(int stream)
|
||||
{
|
||||
if (stream < 7) {
|
||||
NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
|
||||
}
|
||||
else if (stream == 7) {
|
||||
NVIC_EnableIRQ(DMA1_Stream7_IRQn);
|
||||
}
|
||||
else if (stream < 13) {
|
||||
NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
|
||||
}
|
||||
else if (stream < 16) {
|
||||
NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
5
tests/periph_dma/Makefile
Normal file
5
tests/periph_dma/Makefile
Normal file
@ -0,0 +1,5 @@
|
||||
include ../Makefile.tests_common
|
||||
|
||||
FEATURES_REQUIRED = periph_dma
|
||||
|
||||
include $(RIOTBASE)/Makefile.include
|
||||
27
tests/periph_dma/main.c
Normal file
27
tests/periph_dma/main.c
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2018 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup tests
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Dummy test application for DMA peripheral
|
||||
*
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
puts("DMA dummy test app");
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user