Merge pull request #8939 from aabadie/pr/boards/nucleo-l4r5zi

boards/nucleo-l4r5zi: initial basic support

boards/common/nucleo144/include/board.h

@@ -37,7 +37,7 @@ extern "C" {
  * @name    LED pin definitions and handlers
  * @{
  */
-#if defined(CPU_MODEL_STM32L496ZG)
+#if defined(CPU_MODEL_STM32L496ZG) || defined(CPU_MODEL_STM32L4R5ZI)
 #define LED0_PORT           GPIOC
 #define LED0_PIN            GPIO_PIN(PORT_C, 7)
 #define LED0_MASK           (1 << 7)

boards/nucleo-l4r5zi/Makefile

@@ -0,0 +1,4 @@
+MODULE = board
+DIRS = $(RIOTBOARD)/common/nucleo
+
+include $(RIOTBASE)/Makefile.base

boards/nucleo-l4r5zi/Makefile.dep

@@ -0,0 +1,3 @@
+FEATURES_REQUIRED += periph_lpuart
+
+include $(RIOTBOARD)/common/nucleo/Makefile.dep

boards/nucleo-l4r5zi/Makefile.features

@@ -0,0 +1,16 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_lpuart
+FEATURES_PROVIDED += periph_rtc
+FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Put other features for this board (in alphabetical order)
+FEATURES_PROVIDED += riotboot
+
+# load the common Makefile.features for Nucleo boards
+include $(RIOTBOARD)/common/nucleo144/Makefile.features
+
+-include $(RIOTCPU)/stm32l4/Makefile.features

boards/nucleo-l4r5zi/Makefile.include

@@ -0,0 +1,10 @@
+## the cpu to build for
+export CPU = stm32l4
+export CPU_MODEL = stm32l4r5zi
+
+# stdio is available over st-link
+PORT_LINUX ?= /dev/ttyACM0
+PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
+
+# load the common Makefile.include for Nucleo boards
+include $(RIOTBOARD)/common/nucleo144/Makefile.include

boards/nucleo-l4r5zi/doc.txt

@@ -0,0 +1,33 @@
+/**
+ * @defgroup    boards_nucleo144-l4r5 STM32 Nucleo-L4R5ZI
+ * @ingroup     boards_common_nucleo144
+ * @brief       Support for the STM32 Nucleo-L4R5ZI
+
+## Overview
+
+The Nucleo-L4R5ZI is a board from ST's Nucleo family supporting a ARM Cortex-M4
+STM32L4R5ZI microcontroller with 640Kb of RAM and 2Mb of ROM Flash.
+
+## Flashing the device
+
+The ST Nucleo-L4R5ZI board includes an on-board ST-LINK programmer and can be
+flashed using OpenOCD.
+@note The latest release of OpenOCD doesn't contain support for this board,
+so a recent development version (including  http://openocd.zylin.com/#/c/4777)
+must be built from source to be able to flash this board.
+
+To flash this board, just use the following command:
+
+```
+make BOARD=nucleo-l4r5zi flash -C examples/hello-world
+```
+
+### STDIO
+
+STDIO is available via the ST-Link programmer.
+
+Use the `term` targed to open a terminal:
+
+    make BOARD=nucleo-l4r5zi -C examples/hello-world term
+
+ */

boards/nucleo-l4r5zi/include/periph_conf.h

@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2018 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nucleo144-l4r5
+ * @{
+ *
+ * @file
+ * @brief       Peripheral MCU configuration for the nucleo-l4r5zi board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+#include "cfg_i2c1_pb8_pb9.h"
+#include "cfg_rtt_default.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Clock system configuration
+ * @{
+ */
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE           (0)
+
+#ifndef CLOCK_LSE
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE           (1)
+#endif
+
+/* 0: enable MSI only if HSE isn't available
+ * 1: always enable MSI (e.g. if USB or RNG is used)*/
+#define CLOCK_MSI_ENABLE    (1)
+
+#ifndef CLOCK_MSI_LSE_PLL
+/* 0: disable Hardware auto calibration with LSE
+ * 1: enable Hardware auto calibration with LSE (PLL-mode)
+ * Same as with CLOCK_LSE above this defaults to 0 because LSE is
+ * mandatory for MSI/LSE-trimming to work */
+#define CLOCK_MSI_LSE_PLL   (0)
+#endif
+
+/* give the target core clock (HCLK) frequency [in Hz], maximum: 120MHz */
+#define CLOCK_CORECLOCK     (120000000U)
+/* PLL configuration: make sure your values are legit! */
+#define CLOCK_PLL_M         (6)
+#define CLOCK_PLL_N         (30)
+#define CLOCK_PLL_R         (2)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV4
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 4)
+#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV2
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 2)
+/** @} */
+
+/**
+ * @name    Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR1_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
+};
+
+#define TIMER_0_ISR         isr_tim5
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @name    UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {
+        .dev        = LPUART1,
+        .rcc_mask   = RCC_APB1ENR2_LPUART1EN,
+        .rx_pin     = GPIO_PIN(PORT_G, 8),
+        .tx_pin     = GPIO_PIN(PORT_G, 7),
+        .rx_af      = GPIO_AF8,
+        .tx_af      = GPIO_AF8,
+        .bus        = APB12,
+        .irqn       = LPUART1_IRQn,
+        .type       = STM32_LPUART,
+        .clk_src    = 0,
+    },
+    {
+        .dev        = USART3,
+        .rcc_mask   = RCC_APB1ENR1_USART3EN,
+        .rx_pin     = GPIO_PIN(PORT_D, 9),
+        .tx_pin     = GPIO_PIN(PORT_D, 8),
+        .rx_af      = GPIO_AF7,
+        .tx_af      = GPIO_AF7,
+        .bus        = APB1,
+        .irqn       = USART3_IRQn,
+        .type       = STM32_USART,
+        .clk_src    = 0, /* Use APB clock */
+#ifdef UART_USE_DMA
+        .dma_stream = 6,
+        .dma_chan   = 4
+#endif
+    }
+};
+
+#define UART_0_ISR          (isr_lpuart1)
+#define UART_1_ISR          (isr_usart3)
+
+#define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @name    SPI configuration
+ *
+ * @note    The spi_divtable is auto-generated from
+ *          `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+    {       /* for APB1 @ 30000000Hz */
+        7,  /* -> 117187Hz */
+        5,  /* -> 468750Hz */
+        4,  /* -> 937500Hz */
+        2,  /* -> 3750000Hz */
+        1   /* -> 7500000Hz */
+    },
+    {       /* for APB2 @ 60000000Hz */
+        7,  /* -> 234375Hz */
+        6,  /* -> 468750Hz */
+        5,  /* -> 937500Hz */
+        3,  /* -> 3750000Hz */
+        2   /* -> 7500000Hz */
+    }
+};
+
+static const spi_conf_t spi_config[] = {
+    {
+        .dev      = SPI1,
+        .mosi_pin = GPIO_PIN(PORT_A, 7),
+        .miso_pin = GPIO_PIN(PORT_A, 6),
+        .sclk_pin = GPIO_PIN(PORT_A, 5),
+        .cs_pin   = GPIO_UNDEF,
+        .af       = GPIO_AF5,
+        .rccmask  = RCC_APB2ENR_SPI1EN,
+        .apbbus   = APB2
+    }
+};
+
+#define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */

cpu/stm32_common/stm32_mem_lengths.mk

@@ -5,7 +5,7 @@ RAM_START_ADDR ?= 0x20000000
 # The next block takes care of setting the rigth lengths of RAM and ROM
 # for the stm32 family. Most of the CPUs should have been taken into
 # account here, so no need to assign the lengths per model.
-STM32_INFO := $(shell printf '%s' '$(CPU_MODEL)' | tr 'a-z' 'A-Z' | sed -E -e 's/^STM32(F|L)(0|1|2|3|4|7)([0-9])([0-9])(.)(.)/\1 \2 \2\3\4 \3 \4 \5 \6/')
+STM32_INFO := $(shell printf '%s' '$(CPU_MODEL)' | tr 'a-z' 'A-Z' | sed -E -e 's/^STM32(F|L)(0|1|2|3|4|7)([A-Z0-9])([0-9])(.)(.)/\1 \2 \2\3\4 \3 \4 \5 \6/')
 STM32_TYPE     := $(word 1, $(STM32_INFO))
 STM32_FAMILY   := $(word 2, $(STM32_INFO))
 STM32_MODEL    := $(word 3, $(STM32_INFO))
@@ -240,6 +240,8 @@ else ifeq ($(STM32_TYPE), L)
       RAM_LEN = 160K
     else ifeq ($(STM32_MODEL2), 9)
       RAM_LEN = 320K
+    else ifeq ($(STM32_MODEL2), R)
+      RAM_LEN = 640K
     endif
   endif
 endif

cpu/stm32l4/include/cpu_conf.h

@@ -37,6 +37,8 @@
 #include "vendor/stm32l433xx.h"
 #elif defined(CPU_MODEL_STM32L452RE)
 #include "vendor/stm32l452xx.h"
+#elif defined(CPU_MODEL_STM32L4R5ZI)
+#include "vendor/stm32l4r5xx.h"
 #endif
 
 #ifdef __cplusplus
@@ -52,6 +54,8 @@ extern "C" {
 #define CPU_IRQ_NUMOF                   (83U)
 #elif defined(CPU_MODEL_STM32L496ZG)
 #define CPU_IRQ_NUMOF                   (91U)
+#elif defined(CPU_MODEL_STM32L4R5ZI)
+#define CPU_IRQ_NUMOF                   (95U)
 #else
 #define CPU_IRQ_NUMOF                   (82U)
 #endif

cpu/stm32l4/vectors.c

@@ -60,6 +60,7 @@ WEAK_DEFAULT void isr_dma2_channel5(void);
 WEAK_DEFAULT void isr_dma2_channel6(void);
 WEAK_DEFAULT void isr_dma2_channel7(void);
 WEAK_DEFAULT void isr_dma2d(void);
+WEAK_DEFAULT void isr_dmamux1_ovr(void);
 WEAK_DEFAULT void isr_exti(void);
 WEAK_DEFAULT void isr_flash(void);
 WEAK_DEFAULT void isr_fmc(void);
@@ -76,6 +77,8 @@ WEAK_DEFAULT void isr_lcd(void);
 WEAK_DEFAULT void isr_lptim1(void);
 WEAK_DEFAULT void isr_lptim2(void);
 WEAK_DEFAULT void isr_lpuart1(void);
+WEAK_DEFAULT void isr_octospi1(void);
+WEAK_DEFAULT void isr_octospi2(void);
 WEAK_DEFAULT void isr_otg_fs(void);
 WEAK_DEFAULT void isr_pvd_pvm(void);
 WEAK_DEFAULT void isr_quadspi(void);
@@ -165,7 +168,6 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
     [DMA2_Channel6_IRQn      ] = isr_dma2_channel6,        /* [68] DMA2 Channel 6 global interrupt */
     [DMA2_Channel7_IRQn      ] = isr_dma2_channel7,        /* [69] DMA2 Channel 7 global interrupt */
     [LPUART1_IRQn            ] = isr_lpuart1,              /* [70] LP UART1 interrupt */
-    [QUADSPI_IRQn            ] = isr_quadspi,              /* [71] Quad SPI global interrupt */
     [I2C3_EV_IRQn            ] = isr_i2c3_ev,              /* [72] I2C3 event interrupt */
     [I2C3_ER_IRQn            ] = isr_i2c3_er,              /* [73] I2C3 error interrupt */
     [SAI1_IRQn               ] = isr_sai1,                 /* [74] Serial Audio Interface 1 global interrupt */
@@ -210,12 +212,16 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
     [OTG_FS_IRQn             ] = isr_otg_fs,               /* [67] USB OTG FS global Interrupt */
     [SAI2_IRQn               ] = isr_sai2,                 /* [75] Serial Audio Interface 2 global interrupt */
 #endif
-#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L476RG) || \
+#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC) || \
-    defined(CPU_MODEL_STM32L476VG) || defined(CPU_MODEL_STM32L475VG) || \
+    defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG) || \
-    defined(CPU_MODEL_STM32L496ZG)
+    defined(CPU_MODEL_STM32L475VG) || defined(CPU_MODEL_STM32L496ZG)
     [TIM7_IRQn               ] = isr_tim7,                 /* [55] TIM7 global interrupt */
+    [QUADSPI_IRQn            ] = isr_quadspi,              /* [71] Quad SPI global interrupt */
     [SWPMI1_IRQn             ] = isr_swpmi1,               /* [76] Serial Wire Interface 1 global interrupt */
 #endif
+#if defined(CPU_MODEL_STM32L452RE)
+    [QUADSPI_IRQn            ] = isr_quadspi,              /* [71] Quad SPI global interrupt */
+#endif
 #if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG)
     [LCD_IRQn                ] = isr_lcd,                  /* [78] LCD global interrupt */
 #endif
@@ -237,4 +243,38 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
     [CAN2_SCE_IRQn           ] = isr_can2_sce,             /* [89] CAN2 SCE interrupt */
     [DMA2D_IRQn              ] = isr_dma2d,                /* [90] DMA2D global interrupt */
 #endif
+#if defined(CPU_MODEL_STM32L4R5ZI)
+    [ADC1_IRQn               ] = isr_adc1,                 /* [18] ADC1 global Interrupts */
+    [TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17,   /* [26] TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+    [TIM3_IRQn               ] = isr_tim3,                 /* [29] TIM3 global Interrupt */
+    [TIM4_IRQn               ] = isr_tim4,                 /* [30] TIM4 global Interrupt */
+    [I2C2_EV_IRQn            ] = isr_i2c2_ev,              /* [33] I2C2 Event Interrupt */
+    [I2C2_ER_IRQn            ] = isr_i2c2_er,              /* [34] I2C2 Error Interrupt */
+    [SPI2_IRQn               ] = isr_spi2,                 /* [36] SPI2 global Interrupt */
+    [USART3_IRQn             ] = isr_usart3,               /* [39] USART3 global Interrupt */
+    [DFSDM1_FLT3_IRQn        ] = isr_dfsdm1_flt3,          /* [42] DFSDM1 Filter 3 global Interrupt */
+    [TIM8_BRK_IRQn           ] = isr_tim8_brk,             /* [43] TIM8 Break Interrupt */
+    [TIM8_UP_IRQn            ] = isr_tim8_up,              /* [44] TIM8 Update Interrupt */
+    [TIM8_TRG_COM_IRQn       ] = isr_tim8_trg_com,         /* [45] TIM8 Trigger and Commutation Interrupt */
+    [TIM8_CC_IRQn            ] = isr_tim8_cc,              /* [46] TIM8 Capture Compare Interrupt */
+    [FMC_IRQn                ] = isr_fmc,                  /* [48] FMC global Interrupt */
+    [SDMMC1_IRQn             ] = isr_sdmmc1,               /* [49] SDMMC1 global Interrupt */
+    [TIM5_IRQn               ] = isr_tim5,                 /* [50] TIM5 global Interrupt */
+    [UART4_IRQn              ] = isr_uart4,                /* [52] UART4 global Interrupt */
+    [UART5_IRQn              ] = isr_uart5,                /* [53] UART5 global Interrupt */
+    [TIM7_IRQn               ] = isr_tim7,                 /* [55] TIM7 global interrupt */
+    [DFSDM1_FLT0_IRQn        ] = isr_dfsdm1_flt0,          /* [61] DFSDM1 Filter 0 global Interrupt */
+    [DFSDM1_FLT1_IRQn        ] = isr_dfsdm1_flt1,          /* [62] DFSDM1 Filter 1 global Interrupt */
+    [DFSDM1_FLT2_IRQn        ] = isr_dfsdm1_flt2,          /* [63] DFSDM1 Filter 2 global Interrupt */
+    [OTG_FS_IRQn             ] = isr_otg_fs,               /* [67] USB OTG FS global Interrupt */
+    [OCTOSPI1_IRQn           ] = isr_octospi1,             /* [71] OctoSPI1 global interrupt */
+    [SAI2_IRQn               ] = isr_sai2,                 /* [75] Serial Audio Interface 2 global interrupt */
+    [OCTOSPI2_IRQn           ] = isr_octospi2,             /* [76] OctoSPI2 global interrupt */
+    [CRS_IRQn                ] = isr_crs,                  /* [82] CRS global interrupt */
+    [I2C4_EV_IRQn            ] = isr_i2c4_ev,              /* [83] I2C4 Event interrupt */
+    [I2C4_ER_IRQn            ] = isr_i2c4_er,              /* [84] I2C4 Error interrupt */
+    [DCMI_IRQn               ] = isr_dcmi,                 /* [85] DCMI global interrupt */
+    [DMA2D_IRQn              ] = isr_dma2d,                /* [90] DMA2D global interrupt */
+    [DMAMUX1_OVR_IRQn        ] = isr_dmamux1_ovr,          /* [94] DMAMUX1 overrun global interrupt */
+#endif
 };