Merge pull request #8939 from aabadie/pr/boards/nucleo-l4r5zi
boards/nucleo-l4r5zi: initial basic support
This commit is contained in:
Francisco
GitHub
commit
14fe8f29e7
@ -37,7 +37,7 @@ extern "C" {
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* @name LED pin definitions and handlers
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* @{
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*/
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#if defined(CPU_MODEL_STM32L496ZG)
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#if defined(CPU_MODEL_STM32L496ZG) || defined(CPU_MODEL_STM32L4R5ZI)
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#define LED0_PORT GPIOC
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#define LED0_PIN GPIO_PIN(PORT_C, 7)
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#define LED0_MASK (1 << 7)
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4
boards/nucleo-l4r5zi/Makefile
Normal file
4
boards/nucleo-l4r5zi/Makefile
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@ -0,0 +1,4 @@
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MODULE = board
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DIRS = $(RIOTBOARD)/common/nucleo
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include $(RIOTBASE)/Makefile.base
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3
boards/nucleo-l4r5zi/Makefile.dep
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3
boards/nucleo-l4r5zi/Makefile.dep
Normal file
@ -0,0 +1,3 @@
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FEATURES_REQUIRED += periph_lpuart
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include $(RIOTBOARD)/common/nucleo/Makefile.dep
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16
boards/nucleo-l4r5zi/Makefile.features
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16
boards/nucleo-l4r5zi/Makefile.features
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@ -0,0 +1,16 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_lpuart
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Put other features for this board (in alphabetical order)
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FEATURES_PROVIDED += riotboot
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# load the common Makefile.features for Nucleo boards
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include $(RIOTBOARD)/common/nucleo144/Makefile.features
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-include $(RIOTCPU)/stm32l4/Makefile.features
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10
boards/nucleo-l4r5zi/Makefile.include
Normal file
10
boards/nucleo-l4r5zi/Makefile.include
Normal file
@ -0,0 +1,10 @@
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## the cpu to build for
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export CPU = stm32l4
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export CPU_MODEL = stm32l4r5zi
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# stdio is available over st-link
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/common/nucleo144/Makefile.include
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33
boards/nucleo-l4r5zi/doc.txt
Normal file
33
boards/nucleo-l4r5zi/doc.txt
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@ -0,0 +1,33 @@
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/**
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* @defgroup boards_nucleo144-l4r5 STM32 Nucleo-L4R5ZI
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* @ingroup boards_common_nucleo144
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* @brief Support for the STM32 Nucleo-L4R5ZI
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## Overview
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The Nucleo-L4R5ZI is a board from ST's Nucleo family supporting a ARM Cortex-M4
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STM32L4R5ZI microcontroller with 640Kb of RAM and 2Mb of ROM Flash.
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## Flashing the device
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The ST Nucleo-L4R5ZI board includes an on-board ST-LINK programmer and can be
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flashed using OpenOCD.
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@note The latest release of OpenOCD doesn't contain support for this board,
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so a recent development version (including http://openocd.zylin.com/#/c/4777)
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must be built from source to be able to flash this board.
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To flash this board, just use the following command:
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```
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make BOARD=nucleo-l4r5zi flash -C examples/hello-world
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```
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### STDIO
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STDIO is available via the ST-Link programmer.
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Use the `term` targed to open a terminal:
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make BOARD=nucleo-l4r5zi -C examples/hello-world term
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*/
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176
boards/nucleo-l4r5zi/include/periph_conf.h
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176
boards/nucleo-l4r5zi/include/periph_conf.h
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@ -0,0 +1,176 @@
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/*
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* Copyright (C) 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo144-l4r5
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-l4r5zi board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_rtt_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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#ifndef CLOCK_LSE
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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#endif
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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#ifndef CLOCK_MSI_LSE_PLL
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
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* Same as with CLOCK_LSE above this defaults to 0 because LSE is
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* mandatory for MSI/LSE-trimming to work */
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#define CLOCK_MSI_LSE_PLL (0)
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#endif
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 120MHz */
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#define CLOCK_CORECLOCK (120000000U)
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/* PLL configuration: make sure your values are legit! */
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (30)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR1_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim5
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = LPUART1,
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.rcc_mask = RCC_APB1ENR2_LPUART1EN,
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.rx_pin = GPIO_PIN(PORT_G, 8),
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.tx_pin = GPIO_PIN(PORT_G, 7),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB12,
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.irqn = LPUART1_IRQn,
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.type = STM32_LPUART,
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.clk_src = 0,
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},
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR1_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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.type = STM32_USART,
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.clk_src = 0, /* Use APB clock */
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_lpuart1)
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#define UART_1_ISR (isr_usart3)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 30000000Hz */
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7, /* -> 117187Hz */
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5, /* -> 468750Hz */
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4, /* -> 937500Hz */
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2, /* -> 3750000Hz */
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1 /* -> 7500000Hz */
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},
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{ /* for APB2 @ 60000000Hz */
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7, /* -> 234375Hz */
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6, /* -> 468750Hz */
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5, /* -> 937500Hz */
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3, /* -> 3750000Hz */
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2 /* -> 7500000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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@ -5,7 +5,7 @@ RAM_START_ADDR ?= 0x20000000
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# The next block takes care of setting the rigth lengths of RAM and ROM
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# for the stm32 family. Most of the CPUs should have been taken into
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# account here, so no need to assign the lengths per model.
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STM32_INFO := $(shell printf '%s' '$(CPU_MODEL)' | tr 'a-z' 'A-Z' | sed -E -e 's/^STM32(F|L)(0|1|2|3|4|7)([0-9])([0-9])(.)(.)/\1 \2 \2\3\4 \3 \4 \5 \6/')
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STM32_INFO := $(shell printf '%s' '$(CPU_MODEL)' | tr 'a-z' 'A-Z' | sed -E -e 's/^STM32(F|L)(0|1|2|3|4|7)([A-Z0-9])([0-9])(.)(.)/\1 \2 \2\3\4 \3 \4 \5 \6/')
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STM32_TYPE := $(word 1, $(STM32_INFO))
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STM32_FAMILY := $(word 2, $(STM32_INFO))
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STM32_MODEL := $(word 3, $(STM32_INFO))
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@ -240,6 +240,8 @@ else ifeq ($(STM32_TYPE), L)
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RAM_LEN = 160K
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else ifeq ($(STM32_MODEL2), 9)
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RAM_LEN = 320K
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else ifeq ($(STM32_MODEL2), R)
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RAM_LEN = 640K
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endif
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endif
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endif
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@ -37,6 +37,8 @@
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#include "vendor/stm32l433xx.h"
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#elif defined(CPU_MODEL_STM32L452RE)
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#include "vendor/stm32l452xx.h"
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#elif defined(CPU_MODEL_STM32L4R5ZI)
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#include "vendor/stm32l4r5xx.h"
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#endif
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#ifdef __cplusplus
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@ -52,6 +54,8 @@ extern "C" {
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#define CPU_IRQ_NUMOF (83U)
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#elif defined(CPU_MODEL_STM32L496ZG)
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#define CPU_IRQ_NUMOF (91U)
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#elif defined(CPU_MODEL_STM32L4R5ZI)
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#define CPU_IRQ_NUMOF (95U)
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#else
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#define CPU_IRQ_NUMOF (82U)
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#endif
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20141
cpu/stm32l4/include/vendor/stm32l4r5xx.h
vendored
Normal file
20141
cpu/stm32l4/include/vendor/stm32l4r5xx.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
@ -60,6 +60,7 @@ WEAK_DEFAULT void isr_dma2_channel5(void);
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WEAK_DEFAULT void isr_dma2_channel6(void);
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WEAK_DEFAULT void isr_dma2_channel7(void);
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WEAK_DEFAULT void isr_dma2d(void);
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WEAK_DEFAULT void isr_dmamux1_ovr(void);
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WEAK_DEFAULT void isr_exti(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_fmc(void);
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@ -76,6 +77,8 @@ WEAK_DEFAULT void isr_lcd(void);
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WEAK_DEFAULT void isr_lptim1(void);
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WEAK_DEFAULT void isr_lptim2(void);
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WEAK_DEFAULT void isr_lpuart1(void);
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WEAK_DEFAULT void isr_octospi1(void);
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WEAK_DEFAULT void isr_octospi2(void);
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WEAK_DEFAULT void isr_otg_fs(void);
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WEAK_DEFAULT void isr_pvd_pvm(void);
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WEAK_DEFAULT void isr_quadspi(void);
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@ -165,7 +168,6 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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[DMA2_Channel6_IRQn ] = isr_dma2_channel6, /* [68] DMA2 Channel 6 global interrupt */
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[DMA2_Channel7_IRQn ] = isr_dma2_channel7, /* [69] DMA2 Channel 7 global interrupt */
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[LPUART1_IRQn ] = isr_lpuart1, /* [70] LP UART1 interrupt */
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[QUADSPI_IRQn ] = isr_quadspi, /* [71] Quad SPI global interrupt */
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[I2C3_EV_IRQn ] = isr_i2c3_ev, /* [72] I2C3 event interrupt */
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[I2C3_ER_IRQn ] = isr_i2c3_er, /* [73] I2C3 error interrupt */
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[SAI1_IRQn ] = isr_sai1, /* [74] Serial Audio Interface 1 global interrupt */
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@ -210,12 +212,16 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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[OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */
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[SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */
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#endif
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#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L476RG) || \
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defined(CPU_MODEL_STM32L476VG) || defined(CPU_MODEL_STM32L475VG) || \
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defined(CPU_MODEL_STM32L496ZG)
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#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC) || \
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defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG) || \
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defined(CPU_MODEL_STM32L475VG) || defined(CPU_MODEL_STM32L496ZG)
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[TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */
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[QUADSPI_IRQn ] = isr_quadspi, /* [71] Quad SPI global interrupt */
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[SWPMI1_IRQn ] = isr_swpmi1, /* [76] Serial Wire Interface 1 global interrupt */
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#endif
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#if defined(CPU_MODEL_STM32L452RE)
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[QUADSPI_IRQn ] = isr_quadspi, /* [71] Quad SPI global interrupt */
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#endif
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#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG)
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[LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */
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#endif
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@ -237,4 +243,38 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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[CAN2_SCE_IRQn ] = isr_can2_sce, /* [89] CAN2 SCE interrupt */
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[DMA2D_IRQn ] = isr_dma2d, /* [90] DMA2D global interrupt */
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#endif
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#if defined(CPU_MODEL_STM32L4R5ZI)
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[ADC1_IRQn ] = isr_adc1, /* [18] ADC1 global Interrupts */
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[TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
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[TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */
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[TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */
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[I2C2_EV_IRQn ] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */
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[I2C2_ER_IRQn ] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */
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[SPI2_IRQn ] = isr_spi2, /* [36] SPI2 global Interrupt */
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[USART3_IRQn ] = isr_usart3, /* [39] USART3 global Interrupt */
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[DFSDM1_FLT3_IRQn ] = isr_dfsdm1_flt3, /* [42] DFSDM1 Filter 3 global Interrupt */
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[TIM8_BRK_IRQn ] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */
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[TIM8_UP_IRQn ] = isr_tim8_up, /* [44] TIM8 Update Interrupt */
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[TIM8_TRG_COM_IRQn ] = isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */
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[TIM8_CC_IRQn ] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */
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[FMC_IRQn ] = isr_fmc, /* [48] FMC global Interrupt */
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[SDMMC1_IRQn ] = isr_sdmmc1, /* [49] SDMMC1 global Interrupt */
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[TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */
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[UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */
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[UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */
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[TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */
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[DFSDM1_FLT0_IRQn ] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */
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[DFSDM1_FLT1_IRQn ] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */
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[DFSDM1_FLT2_IRQn ] = isr_dfsdm1_flt2, /* [63] DFSDM1 Filter 2 global Interrupt */
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[OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */
|
||||
[OCTOSPI1_IRQn ] = isr_octospi1, /* [71] OctoSPI1 global interrupt */
|
||||
[SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */
|
||||
[OCTOSPI2_IRQn ] = isr_octospi2, /* [76] OctoSPI2 global interrupt */
|
||||
[CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */
|
||||
[I2C4_EV_IRQn ] = isr_i2c4_ev, /* [83] I2C4 Event interrupt */
|
||||
[I2C4_ER_IRQn ] = isr_i2c4_er, /* [84] I2C4 Error interrupt */
|
||||
[DCMI_IRQn ] = isr_dcmi, /* [85] DCMI global interrupt */
|
||||
[DMA2D_IRQn ] = isr_dma2d, /* [90] DMA2D global interrupt */
|
||||
[DMAMUX1_OVR_IRQn ] = isr_dmamux1_ovr, /* [94] DMAMUX1 overrun global interrupt */
|
||||
#endif
|
||||
};
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user